From: whitequark Date: Thu, 11 Jun 2020 12:42:37 +0000 (+0000) Subject: cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. X-Git-Tag: working-ls180~475^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa04b1967076d8a97bdd8802664fd2d1a2424be2;p=yosys.git cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. --- diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index ce21cc1e6..b8acd02df 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -734,71 +734,83 @@ struct debug_item : ::cxxrtl_object { debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {} template - debug_item(value &item) { + debug_item(value &item, size_t lsb_offset = 0) { static_assert(sizeof(item) == value::chunks * sizeof(chunk_t), "value is not compatible with C layout"); - type = VALUE; - width = Bits; - depth = 1; - curr = item.data; - next = item.data; + type = VALUE; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = item.data; + next = item.data; } template - debug_item(const value &item) { + debug_item(const value &item, size_t lsb_offset = 0) { static_assert(sizeof(item) == value::chunks * sizeof(chunk_t), "value is not compatible with C layout"); - type = VALUE; - width = Bits; - depth = 1; - curr = const_cast(item.data); - next = nullptr; + type = VALUE; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = const_cast(item.data); + next = nullptr; } template - debug_item(wire &item) { + debug_item(wire &item, size_t lsb_offset = 0) { static_assert(sizeof(item.curr) == value::chunks * sizeof(chunk_t) && sizeof(item.next) == value::chunks * sizeof(chunk_t), "wire is not compatible with C layout"); - type = WIRE; - width = Bits; - depth = 1; - curr = item.curr.data; - next = item.next.data; + type = WIRE; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = item.curr.data; + next = item.next.data; } template - debug_item(memory &item) { + debug_item(memory &item, size_t zero_offset = 0) { static_assert(sizeof(item.data[0]) == value::chunks * sizeof(chunk_t), "memory is not compatible with C layout"); - type = MEMORY; - width = Width; - depth = item.data.size(); - curr = item.data.empty() ? nullptr : item.data[0].data; - next = nullptr; + type = MEMORY; + width = Width; + lsb_at = 0; + depth = item.data.size(); + zero_at = zero_offset; + curr = item.data.empty() ? nullptr : item.data[0].data; + next = nullptr; } template - debug_item(debug_alias, const value &item) { + debug_item(debug_alias, const value &item, size_t lsb_offset = 0) { static_assert(sizeof(item) == value::chunks * sizeof(chunk_t), "value is not compatible with C layout"); - type = ALIAS; - width = Bits; - depth = 1; - curr = const_cast(item.data); - next = nullptr; + type = ALIAS; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = const_cast(item.data); + next = nullptr; } template - debug_item(debug_alias, const wire &item) { + debug_item(debug_alias, const wire &item, size_t lsb_offset = 0) { static_assert(sizeof(item.curr) == value::chunks * sizeof(chunk_t) && sizeof(item.next) == value::chunks * sizeof(chunk_t), "wire is not compatible with C layout"); - type = ALIAS; - width = Bits; - depth = 1; - curr = const_cast(item.curr.data); - next = nullptr; + type = ALIAS; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = const_cast(item.curr.data); + next = nullptr; } }; static_assert(std::is_standard_layout::value, "debug_item is not compatible with C layout"); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 052053c52..dd2029dc5 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1641,17 +1641,20 @@ struct CxxrtlWorker { dump_const(debug_const_wires[wire]); f << ";\n"; f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(const_" << mangle(wire) << "));\n"; + f << ", debug_item(const_" << mangle(wire) << ", "; + f << wire->start_offset << "));\n"; count_const_wires++; } else if (debug_alias_wires.count(wire)) { // Alias of a member wire f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << "));\n"; + f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", "; + f << wire->start_offset << "));\n"; count_alias_wires++; } else if (!localized_wires.count(wire)) { // Member wire f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(" << mangle(wire) << "));\n"; + f << ", debug_item(" << mangle(wire) << ", "; + f << wire->start_offset << "));\n"; count_member_wires++; } else { count_skipped_wires++; @@ -1661,7 +1664,8 @@ struct CxxrtlWorker { if (memory_it.first[0] != '\\') continue; f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second)); - f << ", debug_item(" << mangle(memory_it.second) << "));\n"; + f << ", debug_item(" << mangle(memory_it.second) << ", "; + f << memory_it.second->start_offset << "));\n"; } for (auto cell : module->cells()) { if (is_internal_cell(cell->type)) diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h index 8bd906ea4..cdddf63f3 100644 --- a/backends/cxxrtl/cxxrtl_capi.h +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -113,9 +113,15 @@ struct cxxrtl_object { // Width of the object in bits. size_t width; + // Index of the least significant bit. + size_t lsb_at; + // Depth of the object. Only meaningful for memories; for other objects, always 1. size_t depth; + // Index of the first word. Only meaningful for memories; for other objects, always 0; + size_t zero_at; + // Bits stored in the object, as 32-bit chunks, least significant bits first. // // The width is rounded up to a multiple of 32; the padding bits are always set to 0 by