From: Aldy Hernandez Date: Tue, 8 Jan 2002 04:50:33 +0000 (+0000) Subject: 002-01-07 Aldy Hernandez X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa066a2379bafed5897d478c2dae6d953a7e4799;p=gcc.git 002-01-07 Aldy Hernandez * config/rs6000/rs6000.c (bdesc_2arg): Add altivec predicates. (altivec_init_builtins): New node v4si_ftype_v16qi_v16qi. * config/rs6000/rs6000.h (rs6000_builtins): Add enums for altivec predicates. * config/rs6000/rs6000.md: Add altivec predicate patterns. From-SVN: r48622 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 87ba57cced3..44113da7e9c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +002-01-07 Aldy Hernandez + + * config/rs6000/rs6000.c (bdesc_2arg): Add altivec predicates. + (altivec_init_builtins): New node v4si_ftype_v16qi_v16qi. + + * config/rs6000/rs6000.h (rs6000_builtins): Add enums for altivec + predicates. + + * config/rs6000/rs6000.md: Add altivec predicate patterns. + 2002-01-07 John David Anglin * pa.c (FUNC_BEGIN_PROLOG_LABEL, current_function_number): Define. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 98919c7d2ca..6466bb2c4f1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3357,6 +3357,19 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp_p, "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp_p, "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb_p, "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh_p, "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw_p, "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp_p, "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp_p, "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb_p, "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh_p, "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw_p, "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub_p, "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh_p, "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw_p, "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, }; /* Simple unary operations: VECb = foo (unsigned literal) or VECb = @@ -3998,6 +4011,12 @@ altivec_init_builtins (void) tree_cons (NULL_TREE, V4SI_type_node, endlink))); + tree v4si_ftype_v16qi_v16qi + = build_function_type (V4SI_type_node, + tree_cons (NULL_TREE, V16QI_type_node, + tree_cons (NULL_TREE, V16QI_type_node, + endlink))); + tree v4si_ftype_v8hi_v4si = build_function_type (V4SI_type_node, tree_cons (NULL_TREE, V8HI_type_node, @@ -4196,6 +4215,10 @@ altivec_init_builtins (void) else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) type = v4si_ftype_v16qi_v4si; + /* vint, vchar, vchar. */ + else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) + type = v4si_ftype_v16qi_v16qi; + /* vint, vshort, vint. */ else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) type = v4si_ftype_v8hi_v4si; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 840613a793c..2fa90b4261c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2960,5 +2960,18 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VUPKHSH, ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, - ALTIVEC_BUILTIN_VUPKLSH + ALTIVEC_BUILTIN_VUPKLSH, + ALTIVEC_BUILTIN_VCMPBFP_P, + ALTIVEC_BUILTIN_VCMPEQFP_P, + ALTIVEC_BUILTIN_VCMPEQUB_P, + ALTIVEC_BUILTIN_VCMPEQUH_P, + ALTIVEC_BUILTIN_VCMPEQUW_P, + ALTIVEC_BUILTIN_VCMPGEFP_P, + ALTIVEC_BUILTIN_VCMPGTFP_P, + ALTIVEC_BUILTIN_VCMPGTSB_P, + ALTIVEC_BUILTIN_VCMPGTSH_P, + ALTIVEC_BUILTIN_VCMPGTSW_P, + ALTIVEC_BUILTIN_VCMPGTUB_P, + ALTIVEC_BUILTIN_VCMPGTUH_P, + ALTIVEC_BUILTIN_VCMPGTUW_P }; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 79c52c235d7..131b767717d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -15272,3 +15272,109 @@ "TARGET_ALTIVEC" "vupklsh %0, %1" [(set_attr "type" "vecperm")]) + +;; AltiVec predicates. + +(define_insn "altivec_vcmpequb_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 173))] + "TARGET_ALTIVEC" + "vcmpequb. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpequh_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 174))] + "TARGET_ALTIVEC" + "vcmpequh. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpequw_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 175))] + "TARGET_ALTIVEC" + "vcmpequw. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpeqfp_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 176))] + "TARGET_ALTIVEC" + "vcmpeqfp. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtub_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 177))] + "TARGET_ALTIVEC" + "vcmpgtub. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtsb_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 178))] + "TARGET_ALTIVEC" + "vcmpgtsb. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtuw_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 179))] + "TARGET_ALTIVEC" + "vcmpgtuw. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtsw_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 180))] + "TARGET_ALTIVEC" + "vcmpgtsw. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgefp_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 181))] + "TARGET_ALTIVEC" + "vcmpgefp. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtfp_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 182))] + "TARGET_ALTIVEC" + "vcmpgtfp. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpbfp_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 183))] + "TARGET_ALTIVEC" + "vcmpbfp. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtuh_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 184))] + "TARGET_ALTIVEC" + "vcmpgtuh. %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtsh_p" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 185))] + "TARGET_ALTIVEC" + "vcmpgtsh. %0,%1,%2" +[(set_attr "type" "veccmp")])