From: Luke Kenneth Casson Leighton Date: Mon, 24 Aug 2020 14:31:09 +0000 (+0000) Subject: nuts. remove div pipe, use FSM X-Git-Tag: partial-core-ls180-gdsii~81 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa06dc39fc17aadd7651b7b43137a290c52fd06e;p=soclayout.git nuts. remove div pipe, use FSM --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index b9a3441..ea4b287 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -46966,11 +46966,11 @@ module \setup_stage wire width 1 output 45 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire width 1 output 46 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 output 47 \dividend - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 output 49 \operation wire width 1 $verilog_initial_trigger process $group_0 @@ -47345,565 +47345,6 @@ module \setup_stage end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.core_setup_stage.core" -module \core$76 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" - wire width 128 input 0 \dividend - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" - wire width 64 input 1 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 3 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 4 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 5 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 6 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 7 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 8 \compare_rhs - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - wire width 1 $verilog_initial_trigger - process $group_1 - assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_2 - assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:265" - wire width 192 \lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" - wire width 255 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" - wire width 255 $4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 255 - connect \A \dividend - connect \B 7'1000000 - connect \Y $4 - end - connect $3 $4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" - wire width 319 $6 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" - wire width 319 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" - cell $sshl $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \divisor_radicand - connect \B 8'10000000 - connect \Y $7 - end - connect $6 $7 - process $group_3 - assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" - switch \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" - attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" - case 2'01 - assign \lhs $3 [191:0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" - attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" - case 2'00 - assign \lhs $6 [191:0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:273" - attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" - case 2'10 - assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - sync init - end - process $group_4 - assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs \lhs - sync init - end - process $group_5 - assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - end - process $group_6 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.core_setup_stage" -module \core_setup_stage - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" - wire width 128 input 27 \dividend - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" - wire width 64 input 28 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" - wire width 2 input 29 \operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 30 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 31 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 32 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 33 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 41 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 47 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 48 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 49 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 50 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 51 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 52 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 53 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 54 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 55 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 56 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 57 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 58 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 59 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 60 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 61 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 62 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" - wire width 128 \core_dividend - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - cell \core$76 \core - connect \dividend \core_dividend - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \divisor_radicand$1 \core_divisor_radicand$30 - connect \operation$2 \core_operation$31 - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_dividend \dividend - sync init - end - process $group_28 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_29 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_30 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$30 - sync init - end - process $group_31 - assign \operation$29 2'00 - assign \operation$29 \core_operation$31 - sync init - end - process $group_32 - assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root \core_quotient_root - sync init - end - process $group_33 - assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand \core_root_times_radicand - sync init - end - process $group_34 - assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs \core_compare_lhs - sync init - end - process $group_35 - assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs \core_compare_rhs - sync init - end -end -attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" module \pipe_start attribute \src "simple/issuer.py:102" @@ -48111,36 +47552,24 @@ module \pipe_start wire width 1 output 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire width 1 \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 37 \p_valid_i + wire width 1 input 34 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 38 \p_ready_o + wire width 1 output 35 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 39 \muxid$1 + wire width 2 input 36 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -48215,7 +47644,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 40 \logical_op__insn_type$2 + wire width 7 input 37 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -48229,49 +47658,49 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 41 \logical_op__fn_unit$3 + wire width 11 input 38 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 42 \logical_op__imm_data__imm$4 + wire width 64 input 39 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 43 \logical_op__imm_data__imm_ok$5 + wire width 1 input 40 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 44 \logical_op__rc__rc$6 + wire width 1 input 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 45 \logical_op__rc__rc_ok$7 + wire width 1 input 42 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 46 \logical_op__oe__oe$8 + wire width 1 input 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 47 \logical_op__oe__oe_ok$9 + wire width 1 input 44 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 48 \logical_op__invert_in$10 + wire width 1 input 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 49 \logical_op__zero_a$11 + wire width 1 input 46 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 50 \logical_op__input_carry$12 + wire width 2 input 47 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 51 \logical_op__invert_out$13 + wire width 1 input 48 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 52 \logical_op__write_cr0$14 + wire width 1 input 49 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 53 \logical_op__output_carry$15 + wire width 1 input 50 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 54 \logical_op__is_32bit$16 + wire width 1 input 51 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 55 \logical_op__is_signed$17 + wire width 1 input 52 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 56 \logical_op__data_len$18 + wire width 4 input 53 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 57 \logical_op__insn$19 + wire width 32 input 54 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 58 \ra$20 + wire width 64 input 55 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 59 \rb$21 + wire width 64 input 56 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 60 \xer_so$22 + wire width 1 input 57 \xer_so$22 cell \p$73 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o @@ -48864,11 +48293,11 @@ module \pipe_start wire width 1 \setup_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire width 1 \setup_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \setup_stage_dividend - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \setup_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \setup_stage_operation cell \setup_stage \setup_stage connect \muxid \setup_stage_muxid @@ -48922,375 +48351,6 @@ module \pipe_start connect \divisor_radicand \setup_stage_divisor_radicand connect \operation \setup_stage_operation end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_setup_stage_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_setup_stage_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_setup_stage_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_setup_stage_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_setup_stage_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_setup_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_setup_stage_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_setup_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_setup_stage_logical_op__oe__oe_ok - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_setup_stage_dive_abs_ov32$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_setup_stage_dive_abs_ov64$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_setup_stage_div_by_zero$91 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_setup_stage_divisor_radicand$92 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_setup_stage_operation$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_setup_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_setup_stage_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_setup_stage_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_setup_stage_compare_rhs - cell \core_setup_stage \core_setup_stage - connect \muxid \core_setup_stage_muxid - connect \logical_op__insn_type \core_setup_stage_logical_op__insn_type - connect \logical_op__fn_unit \core_setup_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_setup_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_setup_stage_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_setup_stage_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_setup_stage_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_setup_stage_logical_op__invert_in - connect \logical_op__zero_a \core_setup_stage_logical_op__zero_a - connect \logical_op__input_carry \core_setup_stage_logical_op__input_carry - connect \logical_op__invert_out \core_setup_stage_logical_op__invert_out - connect \logical_op__write_cr0 \core_setup_stage_logical_op__write_cr0 - connect \logical_op__output_carry \core_setup_stage_logical_op__output_carry - connect \logical_op__is_32bit \core_setup_stage_logical_op__is_32bit - connect \logical_op__is_signed \core_setup_stage_logical_op__is_signed - connect \logical_op__data_len \core_setup_stage_logical_op__data_len - connect \logical_op__insn \core_setup_stage_logical_op__insn - connect \ra \core_setup_stage_ra - connect \rb \core_setup_stage_rb - connect \xer_so \core_setup_stage_xer_so - connect \divisor_neg \core_setup_stage_divisor_neg - connect \dividend_neg \core_setup_stage_dividend_neg - connect \dive_abs_ov32 \core_setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \core_setup_stage_dive_abs_ov64 - connect \div_by_zero \core_setup_stage_div_by_zero - connect \dividend \core_setup_stage_dividend - connect \divisor_radicand \core_setup_stage_divisor_radicand - connect \operation \core_setup_stage_operation - connect \muxid$1 \core_setup_stage_muxid$65 - connect \logical_op__insn_type$2 \core_setup_stage_logical_op__insn_type$66 - connect \logical_op__fn_unit$3 \core_setup_stage_logical_op__fn_unit$67 - connect \logical_op__imm_data__imm$4 \core_setup_stage_logical_op__imm_data__imm$68 - connect \logical_op__imm_data__imm_ok$5 \core_setup_stage_logical_op__imm_data__imm_ok$69 - connect \logical_op__rc__rc$6 \core_setup_stage_logical_op__rc__rc$70 - connect \logical_op__rc__rc_ok$7 \core_setup_stage_logical_op__rc__rc_ok$71 - connect \logical_op__oe__oe$8 \core_setup_stage_logical_op__oe__oe$72 - connect \logical_op__oe__oe_ok$9 \core_setup_stage_logical_op__oe__oe_ok$73 - connect \logical_op__invert_in$10 \core_setup_stage_logical_op__invert_in$74 - connect \logical_op__zero_a$11 \core_setup_stage_logical_op__zero_a$75 - connect \logical_op__input_carry$12 \core_setup_stage_logical_op__input_carry$76 - connect \logical_op__invert_out$13 \core_setup_stage_logical_op__invert_out$77 - connect \logical_op__write_cr0$14 \core_setup_stage_logical_op__write_cr0$78 - connect \logical_op__output_carry$15 \core_setup_stage_logical_op__output_carry$79 - connect \logical_op__is_32bit$16 \core_setup_stage_logical_op__is_32bit$80 - connect \logical_op__is_signed$17 \core_setup_stage_logical_op__is_signed$81 - connect \logical_op__data_len$18 \core_setup_stage_logical_op__data_len$82 - connect \logical_op__insn$19 \core_setup_stage_logical_op__insn$83 - connect \ra$20 \core_setup_stage_ra$84 - connect \rb$21 \core_setup_stage_rb$85 - connect \xer_so$22 \core_setup_stage_xer_so$86 - connect \divisor_neg$23 \core_setup_stage_divisor_neg$87 - connect \dividend_neg$24 \core_setup_stage_dividend_neg$88 - connect \dive_abs_ov32$25 \core_setup_stage_dive_abs_ov32$89 - connect \dive_abs_ov64$26 \core_setup_stage_dive_abs_ov64$90 - connect \div_by_zero$27 \core_setup_stage_div_by_zero$91 - connect \divisor_radicand$28 \core_setup_stage_divisor_radicand$92 - connect \operation$29 \core_setup_stage_operation$93 - connect \quotient_root \core_setup_stage_quotient_root - connect \root_times_radicand \core_setup_stage_root_times_radicand - connect \compare_lhs \core_setup_stage_compare_lhs - connect \compare_rhs \core_setup_stage_compare_rhs - end process $group_0 assign \input_muxid 2'00 assign \input_muxid \muxid$1 @@ -49375,102 +48435,16 @@ module \pipe_start assign \setup_stage_xer_so \input_xer_so$44 sync init end - process $group_44 - assign \core_setup_stage_muxid 2'00 - assign \core_setup_stage_muxid \setup_stage_muxid$45 - sync init - end - process $group_45 - assign \core_setup_stage_logical_op__insn_type 7'0000000 - assign \core_setup_stage_logical_op__fn_unit 11'00000000000 - assign \core_setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_setup_stage_logical_op__imm_data__imm_ok 1'0 - assign \core_setup_stage_logical_op__rc__rc 1'0 - assign \core_setup_stage_logical_op__rc__rc_ok 1'0 - assign \core_setup_stage_logical_op__oe__oe 1'0 - assign \core_setup_stage_logical_op__oe__oe_ok 1'0 - assign \core_setup_stage_logical_op__invert_in 1'0 - assign \core_setup_stage_logical_op__zero_a 1'0 - assign \core_setup_stage_logical_op__input_carry 2'00 - assign \core_setup_stage_logical_op__invert_out 1'0 - assign \core_setup_stage_logical_op__write_cr0 1'0 - assign \core_setup_stage_logical_op__output_carry 1'0 - assign \core_setup_stage_logical_op__is_32bit 1'0 - assign \core_setup_stage_logical_op__is_signed 1'0 - assign \core_setup_stage_logical_op__data_len 4'0000 - assign \core_setup_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_setup_stage_logical_op__insn \core_setup_stage_logical_op__data_len \core_setup_stage_logical_op__is_signed \core_setup_stage_logical_op__is_32bit \core_setup_stage_logical_op__output_carry \core_setup_stage_logical_op__write_cr0 \core_setup_stage_logical_op__invert_out \core_setup_stage_logical_op__input_carry \core_setup_stage_logical_op__zero_a \core_setup_stage_logical_op__invert_in { \core_setup_stage_logical_op__oe__oe_ok \core_setup_stage_logical_op__oe__oe } { \core_setup_stage_logical_op__rc__rc_ok \core_setup_stage_logical_op__rc__rc } { \core_setup_stage_logical_op__imm_data__imm_ok \core_setup_stage_logical_op__imm_data__imm } \core_setup_stage_logical_op__fn_unit \core_setup_stage_logical_op__insn_type } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$94 - process $group_63 - assign \core_setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_setup_stage_ra \ra$94 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$95 - process $group_64 - assign \core_setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_setup_stage_rb \rb$95 - sync init - end - process $group_65 - assign \core_setup_stage_xer_so 1'0 - assign \core_setup_stage_xer_so \setup_stage_xer_so$64 - sync init - end - process $group_66 - assign \core_setup_stage_divisor_neg 1'0 - assign \core_setup_stage_divisor_neg \setup_stage_divisor_neg - sync init - end - process $group_67 - assign \core_setup_stage_dividend_neg 1'0 - assign \core_setup_stage_dividend_neg \setup_stage_dividend_neg - sync init - end - process $group_68 - assign \core_setup_stage_dive_abs_ov32 1'0 - assign \core_setup_stage_dive_abs_ov32 \setup_stage_dive_abs_ov32 - sync init - end - process $group_69 - assign \core_setup_stage_dive_abs_ov64 1'0 - assign \core_setup_stage_dive_abs_ov64 \setup_stage_dive_abs_ov64 - sync init - end - process $group_70 - assign \core_setup_stage_div_by_zero 1'0 - assign \core_setup_stage_div_by_zero \setup_stage_div_by_zero - sync init - end - process $group_71 - assign \core_setup_stage_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_setup_stage_dividend \setup_stage_dividend - sync init - end - process $group_72 - assign \core_setup_stage_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_setup_stage_divisor_radicand \setup_stage_divisor_radicand - sync init - end - process $group_73 - assign \core_setup_stage_operation 2'00 - assign \core_setup_stage_operation \setup_stage_operation - sync init - end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$96 - process $group_74 - assign \p_valid_i$96 1'0 - assign \p_valid_i$96 \p_valid_i + wire width 1 \p_valid_i$65 + process $group_44 + assign \p_valid_i$65 1'0 + assign \p_valid_i$65 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_75 + process $group_45 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -49478,28 +48452,28 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $97 + wire width 1 $66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $98 + cell $and $67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$96 + connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $97 + connect \Y $66 end - process $group_76 + process $group_46 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $97 + assign \p_valid_i_p_ready_o $66 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$99 - process $group_77 - assign \muxid$99 2'00 - assign \muxid$99 \core_setup_stage_muxid$65 + wire width 2 \muxid$68 + process $group_47 + assign \muxid$68 2'00 + assign \muxid$68 \setup_stage_muxid$45 sync init end attribute \enum_base_type "MicrOp" @@ -49576,7 +48550,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$100 + wire width 7 \logical_op__insn_type$69 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -49590,168 +48564,151 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$101 + wire width 11 \logical_op__fn_unit$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$102 + wire width 64 \logical_op__imm_data__imm$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$103 + wire width 1 \logical_op__imm_data__imm_ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$104 + wire width 1 \logical_op__rc__rc$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$105 + wire width 1 \logical_op__rc__rc_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$106 + wire width 1 \logical_op__oe__oe$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$107 + wire width 1 \logical_op__oe__oe_ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$108 + wire width 1 \logical_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$109 + wire width 1 \logical_op__zero_a$78 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$110 + wire width 2 \logical_op__input_carry$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$111 + wire width 1 \logical_op__invert_out$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$112 + wire width 1 \logical_op__write_cr0$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$113 + wire width 1 \logical_op__output_carry$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$114 + wire width 1 \logical_op__is_32bit$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$115 + wire width 1 \logical_op__is_signed$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$116 + wire width 4 \logical_op__data_len$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$117 - process $group_78 - assign \logical_op__insn_type$100 7'0000000 - assign \logical_op__fn_unit$101 11'00000000000 - assign \logical_op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$103 1'0 - assign \logical_op__rc__rc$104 1'0 - assign \logical_op__rc__rc_ok$105 1'0 - assign \logical_op__oe__oe$106 1'0 - assign \logical_op__oe__oe_ok$107 1'0 - assign \logical_op__invert_in$108 1'0 - assign \logical_op__zero_a$109 1'0 - assign \logical_op__input_carry$110 2'00 - assign \logical_op__invert_out$111 1'0 - assign \logical_op__write_cr0$112 1'0 - assign \logical_op__output_carry$113 1'0 - assign \logical_op__is_32bit$114 1'0 - assign \logical_op__is_signed$115 1'0 - assign \logical_op__data_len$116 4'0000 - assign \logical_op__insn$117 32'00000000000000000000000000000000 - assign { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } { \core_setup_stage_logical_op__insn$83 \core_setup_stage_logical_op__data_len$82 \core_setup_stage_logical_op__is_signed$81 \core_setup_stage_logical_op__is_32bit$80 \core_setup_stage_logical_op__output_carry$79 \core_setup_stage_logical_op__write_cr0$78 \core_setup_stage_logical_op__invert_out$77 \core_setup_stage_logical_op__input_carry$76 \core_setup_stage_logical_op__zero_a$75 \core_setup_stage_logical_op__invert_in$74 { \core_setup_stage_logical_op__oe__oe_ok$73 \core_setup_stage_logical_op__oe__oe$72 } { \core_setup_stage_logical_op__rc__rc_ok$71 \core_setup_stage_logical_op__rc__rc$70 } { \core_setup_stage_logical_op__imm_data__imm_ok$69 \core_setup_stage_logical_op__imm_data__imm$68 } \core_setup_stage_logical_op__fn_unit$67 \core_setup_stage_logical_op__insn_type$66 } + wire width 32 \logical_op__insn$86 + process $group_48 + assign \logical_op__insn_type$69 7'0000000 + assign \logical_op__fn_unit$70 11'00000000000 + assign \logical_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$72 1'0 + assign \logical_op__rc__rc$73 1'0 + assign \logical_op__rc__rc_ok$74 1'0 + assign \logical_op__oe__oe$75 1'0 + assign \logical_op__oe__oe_ok$76 1'0 + assign \logical_op__invert_in$77 1'0 + assign \logical_op__zero_a$78 1'0 + assign \logical_op__input_carry$79 2'00 + assign \logical_op__invert_out$80 1'0 + assign \logical_op__write_cr0$81 1'0 + assign \logical_op__output_carry$82 1'0 + assign \logical_op__is_32bit$83 1'0 + assign \logical_op__is_signed$84 1'0 + assign \logical_op__data_len$85 4'0000 + assign \logical_op__insn$86 32'00000000000000000000000000000000 + assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + process $group_66 + assign \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$87 \ra$88 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$118 - process $group_96 - assign \ra$118 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$118 \core_setup_stage_ra$84 - sync init - end + wire width 64 \rb$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$119 - process $group_97 - assign \rb$119 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$119 \core_setup_stage_rb$85 + wire width 64 \rb$90 + process $group_67 + assign \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$89 \rb$90 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$120 - process $group_98 - assign \xer_so$120 1'0 - assign \xer_so$120 \core_setup_stage_xer_so$86 + wire width 1 \xer_so$91 + process $group_68 + assign \xer_so$91 1'0 + assign \xer_so$91 \setup_stage_xer_so$64 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$121 - process $group_99 - assign \divisor_neg$121 1'0 - assign \divisor_neg$121 \core_setup_stage_divisor_neg$87 + wire width 1 \divisor_neg$92 + process $group_69 + assign \divisor_neg$92 1'0 + assign \divisor_neg$92 \setup_stage_divisor_neg sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$122 - process $group_100 - assign \dividend_neg$122 1'0 - assign \dividend_neg$122 \core_setup_stage_dividend_neg$88 + wire width 1 \dividend_neg$93 + process $group_70 + assign \dividend_neg$93 1'0 + assign \dividend_neg$93 \setup_stage_dividend_neg sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$123 - process $group_101 - assign \dive_abs_ov32$123 1'0 - assign \dive_abs_ov32$123 \core_setup_stage_dive_abs_ov32$89 + wire width 1 \dive_abs_ov32$94 + process $group_71 + assign \dive_abs_ov32$94 1'0 + assign \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$124 - process $group_102 - assign \dive_abs_ov64$124 1'0 - assign \dive_abs_ov64$124 \core_setup_stage_dive_abs_ov64$90 + wire width 1 \dive_abs_ov64$95 + process $group_72 + assign \dive_abs_ov64$95 1'0 + assign \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$125 - process $group_103 - assign \div_by_zero$125 1'0 - assign \div_by_zero$125 \core_setup_stage_div_by_zero$91 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$126 - process $group_104 - assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$126 \core_setup_stage_divisor_radicand$92 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$127 - process $group_105 - assign \operation$127 2'00 - assign \operation$127 \core_setup_stage_operation$93 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$128 - process $group_106 - assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$128 \core_setup_stage_quotient_root + wire width 1 \div_by_zero$96 + process $group_73 + assign \div_by_zero$96 1'0 + assign \div_by_zero$96 \setup_stage_div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$129 - process $group_107 - assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$129 \core_setup_stage_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + process $group_74 + assign \dividend$97 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \dividend$97 \setup_stage_dividend sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$130 - process $group_108 - assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$130 \core_setup_stage_compare_lhs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + process $group_75 + assign \divisor_radicand$98 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$98 \setup_stage_divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$131 - process $group_109 - assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$131 \core_setup_stage_compare_rhs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + process $group_76 + assign \operation$99 2'00 + assign \operation$99 \setup_stage_operation sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_110 + process $group_77 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -49772,23 +48729,23 @@ module \pipe_start sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_111 + process $group_78 assign \muxid$next \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$next \muxid$99 + assign \muxid$next \muxid$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$next \muxid$99 + assign \muxid$next \muxid$68 end sync init update \muxid 2'00 sync posedge \coresync_clk update \muxid \muxid$next end - process $group_112 + process $group_79 assign \logical_op__insn_type$next \logical_op__insn_type assign \logical_op__fn_unit$next \logical_op__fn_unit assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm @@ -49811,10 +48768,10 @@ module \pipe_start switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -49865,246 +48822,198 @@ module \pipe_start update \logical_op__data_len \logical_op__data_len$next update \logical_op__insn \logical_op__insn$next end - process $group_130 + process $group_97 assign \ra$next \ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \ra$next \ra$118 + assign \ra$next \ra$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \ra$next \ra$118 + assign \ra$next \ra$87 end sync init update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk update \ra \ra$next end - process $group_131 + process $group_98 assign \rb$next \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \rb$next \rb$119 + assign \rb$next \rb$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \rb$next \rb$119 + assign \rb$next \rb$89 end sync init update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk update \rb \rb$next end - process $group_132 + process $group_99 assign \xer_so$next \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \xer_so$next \xer_so$120 + assign \xer_so$next \xer_so$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \xer_so$next \xer_so$120 + assign \xer_so$next \xer_so$91 end sync init update \xer_so 1'0 sync posedge \coresync_clk update \xer_so \xer_so$next end - process $group_133 + process $group_100 assign \divisor_neg$next \divisor_neg attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \divisor_neg$next \divisor_neg$121 + assign \divisor_neg$next \divisor_neg$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \divisor_neg$next \divisor_neg$121 + assign \divisor_neg$next \divisor_neg$92 end sync init update \divisor_neg 1'0 sync posedge \coresync_clk update \divisor_neg \divisor_neg$next end - process $group_134 + process $group_101 assign \dividend_neg$next \dividend_neg attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \dividend_neg$next \dividend_neg$122 + assign \dividend_neg$next \dividend_neg$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \dividend_neg$next \dividend_neg$122 + assign \dividend_neg$next \dividend_neg$93 end sync init update \dividend_neg 1'0 sync posedge \coresync_clk update \dividend_neg \dividend_neg$next end - process $group_135 + process $group_102 assign \dive_abs_ov32$next \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \dive_abs_ov32$next \dive_abs_ov32$123 + assign \dive_abs_ov32$next \dive_abs_ov32$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \dive_abs_ov32$next \dive_abs_ov32$123 + assign \dive_abs_ov32$next \dive_abs_ov32$94 end sync init update \dive_abs_ov32 1'0 sync posedge \coresync_clk update \dive_abs_ov32 \dive_abs_ov32$next end - process $group_136 + process $group_103 assign \dive_abs_ov64$next \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \dive_abs_ov64$next \dive_abs_ov64$124 + assign \dive_abs_ov64$next \dive_abs_ov64$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \dive_abs_ov64$next \dive_abs_ov64$124 + assign \dive_abs_ov64$next \dive_abs_ov64$95 end sync init update \dive_abs_ov64 1'0 sync posedge \coresync_clk update \dive_abs_ov64 \dive_abs_ov64$next end - process $group_137 + process $group_104 assign \div_by_zero$next \div_by_zero attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \div_by_zero$next \div_by_zero$125 + assign \div_by_zero$next \div_by_zero$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \div_by_zero$next \div_by_zero$125 + assign \div_by_zero$next \div_by_zero$96 end sync init update \div_by_zero 1'0 sync posedge \coresync_clk update \div_by_zero \div_by_zero$next end - process $group_138 - assign \divisor_radicand$next \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$next \divisor_radicand$126 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$next \divisor_radicand$126 - end - sync init - update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand \divisor_radicand$next - end - process $group_139 - assign \operation$next \operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$next \operation$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$next \operation$127 - end - sync init - update \operation 2'00 - sync posedge \coresync_clk - update \operation \operation$next - end - process $group_140 - assign \quotient_root$next \quotient_root - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$next \quotient_root$128 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$next \quotient_root$128 - end - sync init - update \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root \quotient_root$next - end - process $group_141 - assign \root_times_radicand$next \root_times_radicand + process $group_105 + assign \dividend$next \dividend attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \root_times_radicand$next \root_times_radicand$129 + assign \dividend$next \dividend$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \root_times_radicand$next \root_times_radicand$129 + assign \dividend$next \dividend$97 end sync init - update \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + update \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \root_times_radicand \root_times_radicand$next + update \dividend \dividend$next end - process $group_142 - assign \compare_lhs$next \compare_lhs + process $group_106 + assign \divisor_radicand$next \divisor_radicand attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \compare_lhs$next \compare_lhs$130 + assign \divisor_radicand$next \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \compare_lhs$next \compare_lhs$130 + assign \divisor_radicand$next \divisor_radicand$98 end sync init - update \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \compare_lhs \compare_lhs$next + update \divisor_radicand \divisor_radicand$next end - process $group_143 - assign \compare_rhs$next \compare_rhs + process $group_107 + assign \operation$next \operation attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \compare_rhs$next \compare_rhs$131 + assign \operation$next \operation$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \compare_rhs$next \compare_rhs$131 + assign \operation$next \operation$99 end sync init - update \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + update \operation 2'00 sync posedge \coresync_clk - update \compare_rhs \compare_rhs$next + update \operation \operation$next end - process $group_144 + process $group_108 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_145 + process $group_109 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end - connect \ra$94 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$95 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" -module \p$77 +module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -50132,7 +49041,7 @@ module \p$77 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" -module \n$78 +module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -50159,604 +49068,191 @@ module \n$78 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.trial0" -module \trial0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" +module \div_state_next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 output 0 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 input 2 \i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 input 3 \i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + wire width 64 input 4 \divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:82" + wire width 128 \difference + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" + wire width 129 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" + wire width 127 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" + cell $sshl $3 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 127 + connect \A \divisor + connect \B 6'111111 + connect \Y $2 end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" + wire width 129 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" + cell $sub $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 128 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 + parameter \B_WIDTH 127 + parameter \Y_WIDTH 129 + connect \A \i_dividend_quotient + connect \B $2 + connect \Y $4 end + connect $1 $4 process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end + assign \difference 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \difference $1 [127:0] sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:86" + wire width 1 \next_quotient_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" + cell $not $7 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 + connect \A \difference [127] + connect \Y $6 end - connect $7 $10 process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + assign \next_quotient_bit 1'0 + assign \next_quotient_bit $6 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \value + process $group_2 + assign \value 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" + switch { \next_quotient_bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" case 1'1 - assign \trial_compare_rhs $7 [191:0] + assign \value \difference + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:92" + case + assign \value \i_dividend_quotient end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.trial1" -module \trial1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + cell $eq $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" + wire width 8 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" + wire width 8 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" + cell $add $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known connect \B 1'1 - connect \Y $3 + connect \Y $11 end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + connect $10 $11 + process $group_3 + assign \o_q_bits_known 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" + switch { $8 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" case 1'1 - assign \dr_times_trial_bits $3 + assign \o_q_bits_known \i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" + case + assign \o_q_bits_known $10 [6:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + cell $eq $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $13 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.pe" -module \pe - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + process $group_4 + assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" case 1'1 - assign \o 1'0 + assign \o_dividend_quotient \i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" + case + assign \o_dividend_quotient { \value \next_quotient_bit } [127:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core" -module \core$79 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" +module \div_state_init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107" + wire width 128 input 0 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 output 2 \o_dividend_quotient wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 + process $group_0 + assign \o_q_bits_known 7'0000000 + assign \o_q_bits_known 7'0000000 assign $verilog_initial_trigger $verilog_initial_trigger sync init update $verilog_initial_trigger 1'0 end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'111111 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 + process $group_1 + assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \o_dividend_quotient \dividend sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0" -module \core_calculate_stage_0 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" +module \pipe_middle_0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -50831,7 +49327,7 @@ module \core_calculate_stage_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -50845,73 +49341,71 @@ module \core_calculate_stage_0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn + wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra + wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb + wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so + wire width 1 input 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg + wire width 1 input 26 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg + wire width 1 input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 + wire width 1 input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 + wire width 1 input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 35 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 + wire width 2 output 36 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -50986,7 +49480,7 @@ module \core_calculate_stage_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 + wire width 7 output 37 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -51000,112 +49494,275 @@ module \core_calculate_stage_0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 + wire width 11 output 38 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 + wire width 64 output 39 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + wire width 1 output 40 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 + wire width 1 output 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 + wire width 1 output 42 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 + wire width 1 output 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 + wire width 1 output 44 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 + wire width 1 output 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 + wire width 1 output 46 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 + wire width 2 output 47 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 + wire width 1 output 48 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 + wire width 1 output 49 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 + wire width 1 output 50 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 + wire width 1 output 51 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 + wire width 1 output 52 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 + wire width 4 output 53 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 + wire width 32 output 54 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 + wire width 64 output 55 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 + wire width 64 output 56 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 + wire width 1 output 57 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 + wire width 1 output 58 \divisor_neg$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 + wire width 1 output 59 \dividend_neg$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 + wire width 1 output 60 \dive_abs_ov32$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 + wire width 1 output 61 \dive_abs_ov64$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$79 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 + wire width 1 output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + cell \p$76 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$77 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + wire width 64 \div_state_next_divisor + cell \div_state_next \div_state_next + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \divisor \div_state_next_divisor + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 \div_state_init_o_dividend_quotient + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_q_bits_known \div_state_init_o_q_bits_known + connect \o_dividend_quotient \div_state_init_o_dividend_quotient end process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + assign \div_state_init_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \div_state_init_dividend \dividend sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28$next process $group_1 + assign \muxid$1 2'00 + assign \muxid$1 \muxid$28 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$38$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + process $group_2 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -51124,122930 +49781,663 @@ module \core_calculate_stage_0 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 { \logical_op__oe__oe_ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__rc_ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra$47 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb$48 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$49$next process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so$49 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$50$next process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg$50 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$51$next process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg$51 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$52$next process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32$52 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$53$next process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64$53 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$54$next process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero$54 sync init end process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root \div_state_next_o_dividend_quotient [63:0] sync init end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 192 $55 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 192 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \Y $55 + end process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root + assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \remainder $55 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" + wire width 1 \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" + wire width 1 \empty$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + cell $not $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" + cell $eq $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \div_state_next_o_q_bits_known + connect \B 7'1000000 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + cell $and $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $57 + connect \B $59 + connect \Y $61 + end process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand + assign \n_valid_o 1'0 + assign \n_valid_o $61 sync init end process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs + assign \p_ready_o 1'0 + assign \p_ready_o \empty sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" + wire width 7 \saved_state_q_bits_known$next process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs + assign \saved_state_q_bits_known$next \saved_state_q_bits_known + assign \saved_state_q_bits_known$next \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \saved_state_q_bits_known$next 7'0000000 + end sync init + update \saved_state_q_bits_known 7'0000000 + sync posedge \coresync_clk + update \saved_state_q_bits_known \saved_state_q_bits_known$next end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" + wire width 128 \saved_state_dividend_quotient$next process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 + assign \saved_state_dividend_quotient$next \saved_state_dividend_quotient + assign \saved_state_dividend_quotient$next \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \saved_state_dividend_quotient$next 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end sync init + update \saved_state_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \saved_state_dividend_quotient \saved_state_dividend_quotient$next end process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 + assign \div_state_next_i_q_bits_known 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + assign \div_state_next_i_q_bits_known \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + assign \div_state_next_i_q_bits_known \saved_state_q_bits_known + end sync init end process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 + assign \div_state_next_i_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + assign \div_state_next_i_dividend_quotient \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + assign \div_state_next_i_dividend_quotient \saved_state_dividend_quotient + end sync init end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$63$next process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 + assign \div_state_next_divisor 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + assign \div_state_next_divisor \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + assign \div_state_next_divisor \divisor_radicand$63 + end sync init end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.trial0" -module \trial0$81 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" + cell $and $65 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $64 end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] + process $group_37 + assign \empty$next \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \empty$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" + switch { $64 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" + case 1'1 + assign \empty$next 1'1 + end end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.trial1" -module \trial1$82 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \dr_times_trial_bits $3 + assign \empty$next 1'1 end sync init + update \empty 1'1 + sync posedge \coresync_clk + update \empty \empty$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] + process $group_38 + assign \muxid$28$next \muxid$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \muxid$28$next \muxid + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \muxid$28 2'00 + sync posedge \coresync_clk + update \muxid$28 \muxid$28$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.pe" -module \pe$83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 + process $group_39 + assign \logical_op__insn_type$29$next \logical_op__insn_type$29 + assign \logical_op__fn_unit$30$next \logical_op__fn_unit$30 + assign \logical_op__imm_data__imm$31$next \logical_op__imm_data__imm$31 + assign \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm_ok$32 + assign \logical_op__rc__rc$33$next \logical_op__rc__rc$33 + assign \logical_op__rc__rc_ok$34$next \logical_op__rc__rc_ok$34 + assign \logical_op__oe__oe$35$next \logical_op__oe__oe$35 + assign \logical_op__oe__oe_ok$36$next \logical_op__oe__oe_ok$36 + assign \logical_op__invert_in$37$next \logical_op__invert_in$37 + assign \logical_op__zero_a$38$next \logical_op__zero_a$38 + assign \logical_op__input_carry$39$next \logical_op__input_carry$39 + assign \logical_op__invert_out$40$next \logical_op__invert_out$40 + assign \logical_op__write_cr0$41$next \logical_op__write_cr0$41 + assign \logical_op__output_carry$42$next \logical_op__output_carry$42 + assign \logical_op__is_32bit$43$next \logical_op__is_32bit$43 + assign \logical_op__is_signed$44$next \logical_op__is_signed$44 + assign \logical_op__data_len$45$next \logical_op__data_len$45 + assign \logical_op__insn$46$next \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_in$37$next { \logical_op__oe__oe_ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__rc_ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core" -module \core$80 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$81 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$82 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$83 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 + assign \logical_op__imm_data__imm$31$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$32$next 1'0 + assign \logical_op__rc__rc$33$next 1'0 + assign \logical_op__rc__rc_ok$34$next 1'0 + assign \logical_op__oe__oe$35$next 1'0 + assign \logical_op__oe__oe_ok$36$next 1'0 + end + sync init + update \logical_op__insn_type$29 7'0000000 + update \logical_op__fn_unit$30 11'00000000000 + update \logical_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$32 1'0 + update \logical_op__rc__rc$33 1'0 + update \logical_op__rc__rc_ok$34 1'0 + update \logical_op__oe__oe$35 1'0 + update \logical_op__oe__oe_ok$36 1'0 + update \logical_op__invert_in$37 1'0 + update \logical_op__zero_a$38 1'0 + update \logical_op__input_carry$39 2'00 + update \logical_op__invert_out$40 1'0 + update \logical_op__write_cr0$41 1'0 + update \logical_op__output_carry$42 1'0 + update \logical_op__is_32bit$43 1'0 + update \logical_op__is_signed$44 1'0 + update \logical_op__data_len$45 4'0000 + update \logical_op__insn$46 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$29 \logical_op__insn_type$29$next + update \logical_op__fn_unit$30 \logical_op__fn_unit$30$next + update \logical_op__imm_data__imm$31 \logical_op__imm_data__imm$31$next + update \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm_ok$32$next + update \logical_op__rc__rc$33 \logical_op__rc__rc$33$next + update \logical_op__rc__rc_ok$34 \logical_op__rc__rc_ok$34$next + update \logical_op__oe__oe$35 \logical_op__oe__oe$35$next + update \logical_op__oe__oe_ok$36 \logical_op__oe__oe_ok$36$next + update \logical_op__invert_in$37 \logical_op__invert_in$37$next + update \logical_op__zero_a$38 \logical_op__zero_a$38$next + update \logical_op__input_carry$39 \logical_op__input_carry$39$next + update \logical_op__invert_out$40 \logical_op__invert_out$40$next + update \logical_op__write_cr0$41 \logical_op__write_cr0$41$next + update \logical_op__output_carry$42 \logical_op__output_carry$42$next + update \logical_op__is_32bit$43 \logical_op__is_32bit$43$next + update \logical_op__is_signed$44 \logical_op__is_signed$44$next + update \logical_op__data_len$45 \logical_op__data_len$45$next + update \logical_op__insn$46 \logical_op__insn$46$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + process $group_57 + assign \ra$47$next \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \ra$47$next \ra + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case - assign \next_bits 1'1 end sync init + update \ra$47 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$47 \ra$47$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$80 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.trial0" -module \trial0$85 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 + process $group_58 + assign \rb$48$next \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \rb$48$next \rb + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \rb$48 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$48 \rb$48$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] + process $group_59 + assign \xer_so$49$next \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \xer_so$49$next \xer_so + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \xer_so$49 1'0 + sync posedge \coresync_clk + update \xer_so$49 \xer_so$49$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.trial1" -module \trial1$86 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 + process $group_60 + assign \divisor_neg$50$next \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \divisor_neg$50$next \divisor_neg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \divisor_neg$50 1'0 + sync posedge \coresync_clk + update \divisor_neg$50 \divisor_neg$50$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] + process $group_61 + assign \dividend_neg$51$next \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \dividend_neg$51$next \dividend_neg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \dividend_neg$51 1'0 + sync posedge \coresync_clk + update \dividend_neg$51 \dividend_neg$51$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.pe" -module \pe$87 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 + process $group_62 + assign \dive_abs_ov32$52$next \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \dive_abs_ov32$52$next \dive_abs_ov32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case end sync init + update \dive_abs_ov32$52 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$52 \dive_abs_ov32$52$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core" -module \core$84 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$85 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$86 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$87 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + process $group_63 + assign \dive_abs_ov64$53$next \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \dive_abs_ov64$53$next \dive_abs_ov64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case - assign \next_bits 1'1 end sync init + update \dive_abs_ov64$53 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$53 \dive_abs_ov64$53$next end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 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\Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2" -module \core_calculate_stage_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$84 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.trial0" -module \trial0$89 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.trial1" -module \trial1$90 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.pe" -module \pe$91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core" -module \core$88 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$89 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$90 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$91 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + process $group_64 + assign \div_by_zero$54$next \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \div_by_zero$54$next \div_by_zero + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'111100 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3" -module \core_calculate_stage_3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute 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"SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$88 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init 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end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" -module \pipe_middle_0 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$77 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$78 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_0_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_0_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_0_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_0_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_0_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_0_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_0_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_0_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_0_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_0_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_0_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 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\enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute 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\enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_0_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_0_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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width 1 \core_calculate_stage_0_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_0_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_0_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_0_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_0_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_0_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_0_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_0_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_0_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_0_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_0_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_0_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_0_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_0_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_0_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_0_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_0_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_0_compare_rhs$66 - cell \core_calculate_stage_0 \core_calculate_stage_0 - connect \muxid \core_calculate_stage_0_muxid - connect \logical_op__insn_type \core_calculate_stage_0_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_0_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_0_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_0_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_0_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_0_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_0_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_0_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_0_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_0_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_0_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_0_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_0_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_0_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_0_logical_op__insn - connect \ra \core_calculate_stage_0_ra - connect \rb \core_calculate_stage_0_rb - connect \xer_so \core_calculate_stage_0_xer_so - connect \divisor_neg \core_calculate_stage_0_divisor_neg - connect \dividend_neg \core_calculate_stage_0_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_0_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_0_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_0_div_by_zero - connect \divisor_radicand \core_calculate_stage_0_divisor_radicand - connect \operation \core_calculate_stage_0_operation - connect \quotient_root \core_calculate_stage_0_quotient_root - connect \root_times_radicand \core_calculate_stage_0_root_times_radicand - connect \compare_lhs \core_calculate_stage_0_compare_lhs - connect \compare_rhs \core_calculate_stage_0_compare_rhs - connect \muxid$1 \core_calculate_stage_0_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_0_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_0_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_0_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_0_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_0_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_0_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_0_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_0_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_0_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_0_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_0_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_0_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_0_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_0_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_0_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_0_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_0_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_0_ra$53 - connect \rb$21 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"MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute 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"OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_1_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_1_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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1 \core_calculate_stage_1_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_1_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_1_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_1_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_1_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_1_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_1_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_1_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_1_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_1_root_times_radicand - attribute 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"OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute 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attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_1_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_1_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__rc__rc_ok$73 - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_1_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_1_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_1_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_1_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_1_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_1_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_1_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_1_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_1_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_1_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_1_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_1_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_1_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_1_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_1_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_1_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_1_compare_rhs$99 - cell \core_calculate_stage_1 \core_calculate_stage_1 - connect \muxid \core_calculate_stage_1_muxid - connect \logical_op__insn_type \core_calculate_stage_1_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_1_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_1_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_1_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_1_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_1_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_1_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_1_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_1_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_1_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_1_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_1_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_1_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_1_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_1_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_1_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_1_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_1_logical_op__insn - connect \ra \core_calculate_stage_1_ra - connect \rb \core_calculate_stage_1_rb - connect \xer_so \core_calculate_stage_1_xer_so - connect \divisor_neg \core_calculate_stage_1_divisor_neg - connect \dividend_neg \core_calculate_stage_1_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_1_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_1_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_1_div_by_zero - connect \divisor_radicand \core_calculate_stage_1_divisor_radicand - connect \operation \core_calculate_stage_1_operation - connect \quotient_root \core_calculate_stage_1_quotient_root - connect \root_times_radicand \core_calculate_stage_1_root_times_radicand - connect \compare_lhs \core_calculate_stage_1_compare_lhs - connect \compare_rhs \core_calculate_stage_1_compare_rhs - connect \muxid$1 \core_calculate_stage_1_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_1_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_1_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_1_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_1_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_1_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_1_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_1_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_1_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_1_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_1_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_1_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_1_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_1_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_1_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_1_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_1_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_1_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_1_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_1_ra$86 - connect \rb$21 \core_calculate_stage_1_rb$87 - connect \xer_so$22 \core_calculate_stage_1_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_1_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_1_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_1_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_1_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_1_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_1_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_1_operation$95 - connect \quotient_root$30 \core_calculate_stage_1_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_1_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_1_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_1_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_2_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_2_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_2_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_2_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_2_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_2_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_2_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_2_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_2_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_2_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_2_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_2_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_2_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_2_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_2_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_2_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_2_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_2_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_2_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_2_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_2_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_2_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_2_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_2_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_2_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_2_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_2_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_2_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_2_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_2_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_2_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_2_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_2_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_2_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_2_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_2_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_2_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_2_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_2_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_2_compare_rhs$132 - cell \core_calculate_stage_2 \core_calculate_stage_2 - connect \muxid \core_calculate_stage_2_muxid - connect \logical_op__insn_type \core_calculate_stage_2_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_2_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_2_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_2_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_2_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_2_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_2_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_2_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_2_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_2_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_2_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_2_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_2_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_2_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_2_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_2_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_2_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_2_logical_op__insn - connect \ra \core_calculate_stage_2_ra - connect \rb \core_calculate_stage_2_rb - connect \xer_so \core_calculate_stage_2_xer_so - connect \divisor_neg \core_calculate_stage_2_divisor_neg - connect \dividend_neg \core_calculate_stage_2_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_2_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_2_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_2_div_by_zero - connect \divisor_radicand \core_calculate_stage_2_divisor_radicand - connect \operation \core_calculate_stage_2_operation - connect \quotient_root \core_calculate_stage_2_quotient_root - connect \root_times_radicand \core_calculate_stage_2_root_times_radicand - connect \compare_lhs \core_calculate_stage_2_compare_lhs - connect \compare_rhs \core_calculate_stage_2_compare_rhs - connect \muxid$1 \core_calculate_stage_2_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_2_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_2_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_2_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_2_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_2_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_2_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_2_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_2_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_2_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_2_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_2_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_2_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_2_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_2_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_2_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_2_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_2_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_2_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_2_ra$119 - connect \rb$21 \core_calculate_stage_2_rb$120 - connect \xer_so$22 \core_calculate_stage_2_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_2_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_2_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_2_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_2_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_2_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_2_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_2_operation$128 - connect \quotient_root$30 \core_calculate_stage_2_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_2_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_2_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_2_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_3_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_3_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_3_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_3_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_3_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_3_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_3_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_3_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_3_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_3_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_3_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_3_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_3_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_3_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_3_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_3_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_3_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_3_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_3_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_3_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_3_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute 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attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_3_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_3_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_3_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_3_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_3_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_3_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_3_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_3_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_3_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_3_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_3_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_3_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_3_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_3_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_3_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_3_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_3_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_3_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_3_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_3_compare_rhs$165 - cell \core_calculate_stage_3 \core_calculate_stage_3 - connect \muxid \core_calculate_stage_3_muxid - connect \logical_op__insn_type \core_calculate_stage_3_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_3_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_3_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_3_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_3_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_3_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_3_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_3_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_3_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_3_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_3_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_3_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_3_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_3_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_3_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_3_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_3_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_3_logical_op__insn - connect \ra \core_calculate_stage_3_ra - connect \rb \core_calculate_stage_3_rb - connect \xer_so \core_calculate_stage_3_xer_so - connect \divisor_neg \core_calculate_stage_3_divisor_neg - connect \dividend_neg \core_calculate_stage_3_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_3_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_3_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_3_div_by_zero - connect \divisor_radicand \core_calculate_stage_3_divisor_radicand - connect \operation \core_calculate_stage_3_operation - connect \quotient_root \core_calculate_stage_3_quotient_root - connect \root_times_radicand \core_calculate_stage_3_root_times_radicand - connect \compare_lhs \core_calculate_stage_3_compare_lhs - connect \compare_rhs \core_calculate_stage_3_compare_rhs - connect \muxid$1 \core_calculate_stage_3_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_3_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_3_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_3_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_3_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_3_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_3_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_3_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_3_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_3_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_3_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_3_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_3_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_3_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_3_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_3_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_3_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_3_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_3_ra$152 - connect \rb$21 \core_calculate_stage_3_rb$153 - connect \xer_so$22 \core_calculate_stage_3_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_3_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_3_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_3_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_3_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_3_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_3_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_3_operation$161 - connect \quotient_root$30 \core_calculate_stage_3_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_3_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_3_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_3_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_0_muxid 2'00 - assign \core_calculate_stage_0_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_0_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_0_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_0_logical_op__rc__rc 1'0 - assign \core_calculate_stage_0_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_0_logical_op__oe__oe 1'0 - assign \core_calculate_stage_0_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_0_logical_op__invert_in 1'0 - assign \core_calculate_stage_0_logical_op__zero_a 1'0 - assign \core_calculate_stage_0_logical_op__input_carry 2'00 - assign \core_calculate_stage_0_logical_op__invert_out 1'0 - assign \core_calculate_stage_0_logical_op__write_cr0 1'0 - assign \core_calculate_stage_0_logical_op__output_carry 1'0 - assign \core_calculate_stage_0_logical_op__is_32bit 1'0 - assign \core_calculate_stage_0_logical_op__is_signed 1'0 - assign \core_calculate_stage_0_logical_op__data_len 4'0000 - assign \core_calculate_stage_0_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_0_logical_op__insn \core_calculate_stage_0_logical_op__data_len \core_calculate_stage_0_logical_op__is_signed \core_calculate_stage_0_logical_op__is_32bit \core_calculate_stage_0_logical_op__output_carry \core_calculate_stage_0_logical_op__write_cr0 \core_calculate_stage_0_logical_op__invert_out \core_calculate_stage_0_logical_op__input_carry \core_calculate_stage_0_logical_op__zero_a \core_calculate_stage_0_logical_op__invert_in { \core_calculate_stage_0_logical_op__oe__oe_ok \core_calculate_stage_0_logical_op__oe__oe } { \core_calculate_stage_0_logical_op__rc__rc_ok \core_calculate_stage_0_logical_op__rc__rc } { \core_calculate_stage_0_logical_op__imm_data__imm_ok \core_calculate_stage_0_logical_op__imm_data__imm } \core_calculate_stage_0_logical_op__fn_unit \core_calculate_stage_0_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_0_xer_so 1'0 - assign \core_calculate_stage_0_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_0_divisor_neg 1'0 - assign \core_calculate_stage_0_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_0_dividend_neg 1'0 - assign \core_calculate_stage_0_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_0_dive_abs_ov32 1'0 - assign \core_calculate_stage_0_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_0_dive_abs_ov64 1'0 - assign \core_calculate_stage_0_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_0_div_by_zero 1'0 - assign \core_calculate_stage_0_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_0_operation 2'00 - assign \core_calculate_stage_0_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_0_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_0_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_1_muxid 2'00 - assign \core_calculate_stage_1_muxid \core_calculate_stage_0_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_1_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_1_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_1_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_1_logical_op__rc__rc 1'0 - assign \core_calculate_stage_1_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_1_logical_op__oe__oe 1'0 - assign \core_calculate_stage_1_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_1_logical_op__invert_in 1'0 - assign \core_calculate_stage_1_logical_op__zero_a 1'0 - assign \core_calculate_stage_1_logical_op__input_carry 2'00 - assign \core_calculate_stage_1_logical_op__invert_out 1'0 - assign \core_calculate_stage_1_logical_op__write_cr0 1'0 - assign \core_calculate_stage_1_logical_op__output_carry 1'0 - assign \core_calculate_stage_1_logical_op__is_32bit 1'0 - assign \core_calculate_stage_1_logical_op__is_signed 1'0 - assign \core_calculate_stage_1_logical_op__data_len 4'0000 - assign \core_calculate_stage_1_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_1_logical_op__insn \core_calculate_stage_1_logical_op__data_len \core_calculate_stage_1_logical_op__is_signed \core_calculate_stage_1_logical_op__is_32bit \core_calculate_stage_1_logical_op__output_carry \core_calculate_stage_1_logical_op__write_cr0 \core_calculate_stage_1_logical_op__invert_out \core_calculate_stage_1_logical_op__input_carry \core_calculate_stage_1_logical_op__zero_a \core_calculate_stage_1_logical_op__invert_in { \core_calculate_stage_1_logical_op__oe__oe_ok \core_calculate_stage_1_logical_op__oe__oe } { \core_calculate_stage_1_logical_op__rc__rc_ok \core_calculate_stage_1_logical_op__rc__rc } { \core_calculate_stage_1_logical_op__imm_data__imm_ok \core_calculate_stage_1_logical_op__imm_data__imm } \core_calculate_stage_1_logical_op__fn_unit \core_calculate_stage_1_logical_op__insn_type } { \core_calculate_stage_0_logical_op__insn$52 \core_calculate_stage_0_logical_op__data_len$51 \core_calculate_stage_0_logical_op__is_signed$50 \core_calculate_stage_0_logical_op__is_32bit$49 \core_calculate_stage_0_logical_op__output_carry$48 \core_calculate_stage_0_logical_op__write_cr0$47 \core_calculate_stage_0_logical_op__invert_out$46 \core_calculate_stage_0_logical_op__input_carry$45 \core_calculate_stage_0_logical_op__zero_a$44 \core_calculate_stage_0_logical_op__invert_in$43 { \core_calculate_stage_0_logical_op__oe__oe_ok$42 \core_calculate_stage_0_logical_op__oe__oe$41 } { \core_calculate_stage_0_logical_op__rc__rc_ok$40 \core_calculate_stage_0_logical_op__rc__rc$39 } { \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 \core_calculate_stage_0_logical_op__imm_data__imm$37 } \core_calculate_stage_0_logical_op__fn_unit$36 \core_calculate_stage_0_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_ra \core_calculate_stage_0_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_rb \core_calculate_stage_0_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_1_xer_so 1'0 - assign \core_calculate_stage_1_xer_so \core_calculate_stage_0_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_1_divisor_neg 1'0 - assign \core_calculate_stage_1_divisor_neg \core_calculate_stage_0_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_1_dividend_neg 1'0 - assign \core_calculate_stage_1_dividend_neg \core_calculate_stage_0_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_1_dive_abs_ov32 1'0 - assign \core_calculate_stage_1_dive_abs_ov32 \core_calculate_stage_0_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_1_dive_abs_ov64 1'0 - assign \core_calculate_stage_1_dive_abs_ov64 \core_calculate_stage_0_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_1_div_by_zero 1'0 - assign \core_calculate_stage_1_div_by_zero \core_calculate_stage_0_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_divisor_radicand \core_calculate_stage_0_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_1_operation 2'00 - assign \core_calculate_stage_1_operation \core_calculate_stage_0_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_quotient_root \core_calculate_stage_0_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_root_times_radicand \core_calculate_stage_0_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_1_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_compare_lhs \core_calculate_stage_0_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_1_compare_rhs \core_calculate_stage_0_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_2_muxid 2'00 - assign \core_calculate_stage_2_muxid \core_calculate_stage_1_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_2_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_2_logical_op__fn_unit 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_3_logical_op__insn$151 \core_calculate_stage_3_logical_op__data_len$150 \core_calculate_stage_3_logical_op__is_signed$149 \core_calculate_stage_3_logical_op__is_32bit$148 \core_calculate_stage_3_logical_op__output_carry$147 \core_calculate_stage_3_logical_op__write_cr0$146 \core_calculate_stage_3_logical_op__invert_out$145 \core_calculate_stage_3_logical_op__input_carry$144 \core_calculate_stage_3_logical_op__zero_a$143 \core_calculate_stage_3_logical_op__invert_in$142 { \core_calculate_stage_3_logical_op__oe__oe_ok$141 \core_calculate_stage_3_logical_op__oe__oe$140 } { \core_calculate_stage_3_logical_op__rc__rc_ok$139 \core_calculate_stage_3_logical_op__rc__rc$138 } { \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 \core_calculate_stage_3_logical_op__imm_data__imm$136 } \core_calculate_stage_3_logical_op__fn_unit$135 \core_calculate_stage_3_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_3_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_3_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_3_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_3_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_3_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_3_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_3_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_3_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_3_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_3_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_3_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_3_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_3_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_3_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.p" -module \p$92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.n" -module \n$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.trial0" -module \trial0$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.trial1" -module \trial1$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.pe" -module \pe$97 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core" -module \core$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$95 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$96 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$97 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 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"OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$94 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.trial0" -module \trial0$99 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.trial1" -module \trial1$100 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.pe" -module \pe$101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core" -module \core$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$99 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$100 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$101 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe 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128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$98 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.trial0" -module \trial0$103 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.trial1" -module \trial1$104 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.pe" -module \pe$105 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core" -module \core$102 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$103 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$104 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$105 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - 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\nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$102 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.trial0" -module \trial0$107 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.trial1" -module \trial1$108 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1111000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.pe" -module \pe$109 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core" -module \core$106 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$107 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$108 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$109 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$106 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1" -module \pipe_middle_1 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$92 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$93 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_4_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_4_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_4_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_4_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_4_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_4_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_4_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_4_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_4_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_4_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_4_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_4_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_4_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_4_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_4_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_4_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_4_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_4_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_4_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_4_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_4_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_4_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_4_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_4_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_4_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_4_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_4_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_4_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_4_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_4_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_4_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_4_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_4_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_4_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_4_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_4_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_4_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_4_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_4_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_4_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_4_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_4_compare_rhs$66 - cell \core_calculate_stage_4 \core_calculate_stage_4 - connect \muxid \core_calculate_stage_4_muxid - connect \logical_op__insn_type \core_calculate_stage_4_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_4_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_4_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_4_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_4_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_4_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_4_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_4_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_4_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_4_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_4_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_4_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_4_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_4_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_4_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_4_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_4_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_4_logical_op__insn - connect \ra \core_calculate_stage_4_ra - connect \rb \core_calculate_stage_4_rb - connect \xer_so \core_calculate_stage_4_xer_so - connect \divisor_neg \core_calculate_stage_4_divisor_neg - connect \dividend_neg \core_calculate_stage_4_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_4_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_4_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_4_div_by_zero - connect \divisor_radicand \core_calculate_stage_4_divisor_radicand - connect \operation \core_calculate_stage_4_operation - connect \quotient_root \core_calculate_stage_4_quotient_root - connect \root_times_radicand \core_calculate_stage_4_root_times_radicand - connect \compare_lhs \core_calculate_stage_4_compare_lhs - connect \compare_rhs \core_calculate_stage_4_compare_rhs - connect \muxid$1 \core_calculate_stage_4_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_4_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_4_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_4_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_4_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_4_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_4_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_4_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_4_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_4_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_4_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_4_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_4_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_4_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_4_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_4_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_4_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_4_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_4_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_4_ra$53 - connect \rb$21 \core_calculate_stage_4_rb$54 - connect \xer_so$22 \core_calculate_stage_4_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_4_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_4_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_4_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_4_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_4_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_4_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_4_operation$62 - connect \quotient_root$30 \core_calculate_stage_4_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_4_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_4_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_4_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_5_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_5_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_5_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__invert_out - attribute \src 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_5_logical_op__insn_type$68 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_5_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_5_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_5_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_5_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_5_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_5_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_5_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_5_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_5_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_5_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_5_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_5_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_5_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_5_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_5_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_5_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_5_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_5_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_5_compare_rhs$99 - cell \core_calculate_stage_5 \core_calculate_stage_5 - connect \muxid \core_calculate_stage_5_muxid - connect \logical_op__insn_type \core_calculate_stage_5_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_5_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_5_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_5_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_5_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_5_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_5_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_5_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_5_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_5_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_5_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_5_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_5_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_5_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_5_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_5_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_5_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_5_logical_op__insn - connect \ra \core_calculate_stage_5_ra - connect \rb \core_calculate_stage_5_rb - connect \xer_so \core_calculate_stage_5_xer_so - connect \divisor_neg \core_calculate_stage_5_divisor_neg - connect \dividend_neg \core_calculate_stage_5_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_5_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_5_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_5_div_by_zero - connect \divisor_radicand \core_calculate_stage_5_divisor_radicand - connect \operation \core_calculate_stage_5_operation - connect \quotient_root \core_calculate_stage_5_quotient_root - connect \root_times_radicand \core_calculate_stage_5_root_times_radicand - connect \compare_lhs \core_calculate_stage_5_compare_lhs - connect \compare_rhs \core_calculate_stage_5_compare_rhs - connect \muxid$1 \core_calculate_stage_5_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_5_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_5_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_5_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_5_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_5_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_5_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_5_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_5_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_5_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_5_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_5_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_5_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_5_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_5_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_5_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_5_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_5_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_5_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_5_ra$86 - connect \rb$21 \core_calculate_stage_5_rb$87 - connect \xer_so$22 \core_calculate_stage_5_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_5_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_5_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_5_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_5_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_5_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_5_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_5_operation$95 - connect \quotient_root$30 \core_calculate_stage_5_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_5_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_5_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_5_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_6_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_6_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_6_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_6_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_6_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_6_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_6_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_6_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_6_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_6_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_6_compare_rhs$132 - cell \core_calculate_stage_6 \core_calculate_stage_6 - connect \muxid \core_calculate_stage_6_muxid - connect \logical_op__insn_type \core_calculate_stage_6_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_6_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_6_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_6_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_6_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_6_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_6_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_6_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_6_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_6_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_6_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_6_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_6_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_6_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_6_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_6_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_6_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_6_logical_op__insn - connect \ra \core_calculate_stage_6_ra - connect \rb \core_calculate_stage_6_rb - connect \xer_so \core_calculate_stage_6_xer_so - connect \divisor_neg \core_calculate_stage_6_divisor_neg - connect \dividend_neg \core_calculate_stage_6_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_6_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_6_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_6_div_by_zero - connect \divisor_radicand \core_calculate_stage_6_divisor_radicand - connect \operation \core_calculate_stage_6_operation - connect \quotient_root \core_calculate_stage_6_quotient_root - connect \root_times_radicand \core_calculate_stage_6_root_times_radicand - connect \compare_lhs \core_calculate_stage_6_compare_lhs - connect \compare_rhs \core_calculate_stage_6_compare_rhs - connect \muxid$1 \core_calculate_stage_6_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_6_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_6_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_6_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_6_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_6_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_6_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_6_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_6_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_6_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_6_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_6_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_6_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_6_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_6_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_6_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_6_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_6_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_6_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_6_ra$119 - connect \rb$21 \core_calculate_stage_6_rb$120 - connect \xer_so$22 \core_calculate_stage_6_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_6_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_6_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_6_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_6_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_6_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_6_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_6_operation$128 - connect \quotient_root$30 \core_calculate_stage_6_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_6_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_6_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_6_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_7_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_7_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_7_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_7_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_7_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_7_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_7_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_7_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_7_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_7_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_7_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_7_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_7_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 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"OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_7_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_7_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_7_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_7_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_7_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_7_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_7_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_7_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_7_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_7_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_7_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_7_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_7_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_7_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_7_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_7_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_7_compare_rhs$165 - cell \core_calculate_stage_7 \core_calculate_stage_7 - connect \muxid \core_calculate_stage_7_muxid - connect \logical_op__insn_type \core_calculate_stage_7_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_7_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_7_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_7_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_7_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_7_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_7_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_7_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_7_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_7_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_7_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_7_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_7_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_7_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_7_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_7_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_7_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_7_logical_op__insn - connect \ra \core_calculate_stage_7_ra - connect \rb \core_calculate_stage_7_rb - connect \xer_so \core_calculate_stage_7_xer_so - connect \divisor_neg \core_calculate_stage_7_divisor_neg - connect \dividend_neg \core_calculate_stage_7_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_7_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_7_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_7_div_by_zero - connect \divisor_radicand \core_calculate_stage_7_divisor_radicand - connect \operation \core_calculate_stage_7_operation - connect \quotient_root \core_calculate_stage_7_quotient_root - connect \root_times_radicand \core_calculate_stage_7_root_times_radicand - connect \compare_lhs \core_calculate_stage_7_compare_lhs - connect \compare_rhs \core_calculate_stage_7_compare_rhs - connect \muxid$1 \core_calculate_stage_7_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_7_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_7_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_7_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_7_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_7_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_7_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_7_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_7_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_7_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_7_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_7_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_7_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_7_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_7_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_7_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_7_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_7_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_7_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_7_ra$152 - connect \rb$21 \core_calculate_stage_7_rb$153 - connect \xer_so$22 \core_calculate_stage_7_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_7_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_7_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_7_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_7_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_7_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_7_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_7_operation$161 - connect \quotient_root$30 \core_calculate_stage_7_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_7_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_7_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_7_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_4_muxid 2'00 - assign \core_calculate_stage_4_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_4_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_4_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_4_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_4_logical_op__rc__rc 1'0 - assign \core_calculate_stage_4_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_4_logical_op__oe__oe 1'0 - assign \core_calculate_stage_4_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_4_logical_op__invert_in 1'0 - assign \core_calculate_stage_4_logical_op__zero_a 1'0 - assign \core_calculate_stage_4_logical_op__input_carry 2'00 - assign \core_calculate_stage_4_logical_op__invert_out 1'0 - assign \core_calculate_stage_4_logical_op__write_cr0 1'0 - assign \core_calculate_stage_4_logical_op__output_carry 1'0 - assign \core_calculate_stage_4_logical_op__is_32bit 1'0 - assign \core_calculate_stage_4_logical_op__is_signed 1'0 - assign \core_calculate_stage_4_logical_op__data_len 4'0000 - assign \core_calculate_stage_4_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_4_logical_op__insn \core_calculate_stage_4_logical_op__data_len \core_calculate_stage_4_logical_op__is_signed \core_calculate_stage_4_logical_op__is_32bit \core_calculate_stage_4_logical_op__output_carry \core_calculate_stage_4_logical_op__write_cr0 \core_calculate_stage_4_logical_op__invert_out \core_calculate_stage_4_logical_op__input_carry \core_calculate_stage_4_logical_op__zero_a \core_calculate_stage_4_logical_op__invert_in { \core_calculate_stage_4_logical_op__oe__oe_ok \core_calculate_stage_4_logical_op__oe__oe } { \core_calculate_stage_4_logical_op__rc__rc_ok \core_calculate_stage_4_logical_op__rc__rc } { \core_calculate_stage_4_logical_op__imm_data__imm_ok \core_calculate_stage_4_logical_op__imm_data__imm } \core_calculate_stage_4_logical_op__fn_unit \core_calculate_stage_4_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_4_xer_so 1'0 - assign \core_calculate_stage_4_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_4_divisor_neg 1'0 - assign \core_calculate_stage_4_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_4_dividend_neg 1'0 - assign \core_calculate_stage_4_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_4_dive_abs_ov32 1'0 - assign \core_calculate_stage_4_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_4_dive_abs_ov64 1'0 - assign \core_calculate_stage_4_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_4_div_by_zero 1'0 - assign \core_calculate_stage_4_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_4_operation 2'00 - assign \core_calculate_stage_4_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_4_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_5_muxid 2'00 - assign \core_calculate_stage_5_muxid \core_calculate_stage_4_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_5_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_5_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_5_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_5_logical_op__rc__rc 1'0 - assign \core_calculate_stage_5_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_5_logical_op__oe__oe 1'0 - assign \core_calculate_stage_5_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_5_logical_op__invert_in 1'0 - assign \core_calculate_stage_5_logical_op__zero_a 1'0 - assign \core_calculate_stage_5_logical_op__input_carry 2'00 - assign \core_calculate_stage_5_logical_op__invert_out 1'0 - assign \core_calculate_stage_5_logical_op__write_cr0 1'0 - assign \core_calculate_stage_5_logical_op__output_carry 1'0 - assign \core_calculate_stage_5_logical_op__is_32bit 1'0 - assign \core_calculate_stage_5_logical_op__is_signed 1'0 - assign \core_calculate_stage_5_logical_op__data_len 4'0000 - assign \core_calculate_stage_5_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_5_logical_op__insn \core_calculate_stage_5_logical_op__data_len \core_calculate_stage_5_logical_op__is_signed \core_calculate_stage_5_logical_op__is_32bit \core_calculate_stage_5_logical_op__output_carry \core_calculate_stage_5_logical_op__write_cr0 \core_calculate_stage_5_logical_op__invert_out \core_calculate_stage_5_logical_op__input_carry \core_calculate_stage_5_logical_op__zero_a \core_calculate_stage_5_logical_op__invert_in { \core_calculate_stage_5_logical_op__oe__oe_ok \core_calculate_stage_5_logical_op__oe__oe } { \core_calculate_stage_5_logical_op__rc__rc_ok \core_calculate_stage_5_logical_op__rc__rc } { \core_calculate_stage_5_logical_op__imm_data__imm_ok \core_calculate_stage_5_logical_op__imm_data__imm } \core_calculate_stage_5_logical_op__fn_unit \core_calculate_stage_5_logical_op__insn_type } { \core_calculate_stage_4_logical_op__insn$52 \core_calculate_stage_4_logical_op__data_len$51 \core_calculate_stage_4_logical_op__is_signed$50 \core_calculate_stage_4_logical_op__is_32bit$49 \core_calculate_stage_4_logical_op__output_carry$48 \core_calculate_stage_4_logical_op__write_cr0$47 \core_calculate_stage_4_logical_op__invert_out$46 \core_calculate_stage_4_logical_op__input_carry$45 \core_calculate_stage_4_logical_op__zero_a$44 \core_calculate_stage_4_logical_op__invert_in$43 { \core_calculate_stage_4_logical_op__oe__oe_ok$42 \core_calculate_stage_4_logical_op__oe__oe$41 } { \core_calculate_stage_4_logical_op__rc__rc_ok$40 \core_calculate_stage_4_logical_op__rc__rc$39 } { \core_calculate_stage_4_logical_op__imm_data__imm_ok$38 \core_calculate_stage_4_logical_op__imm_data__imm$37 } \core_calculate_stage_4_logical_op__fn_unit$36 \core_calculate_stage_4_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_5_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_ra \core_calculate_stage_4_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_5_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_rb \core_calculate_stage_4_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_5_xer_so 1'0 - assign \core_calculate_stage_5_xer_so \core_calculate_stage_4_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_5_divisor_neg 1'0 - assign \core_calculate_stage_5_divisor_neg \core_calculate_stage_4_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_5_dividend_neg 1'0 - assign \core_calculate_stage_5_dividend_neg \core_calculate_stage_4_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_5_dive_abs_ov32 1'0 - assign \core_calculate_stage_5_dive_abs_ov32 \core_calculate_stage_4_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_5_dive_abs_ov64 1'0 - assign \core_calculate_stage_5_dive_abs_ov64 \core_calculate_stage_4_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_5_div_by_zero 1'0 - assign \core_calculate_stage_5_div_by_zero \core_calculate_stage_4_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_divisor_radicand \core_calculate_stage_4_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_5_operation 2'00 - assign \core_calculate_stage_5_operation \core_calculate_stage_4_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_quotient_root \core_calculate_stage_4_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_root_times_radicand \core_calculate_stage_4_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_5_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_compare_lhs \core_calculate_stage_4_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_5_compare_rhs \core_calculate_stage_4_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_6_muxid 2'00 - assign \core_calculate_stage_6_muxid \core_calculate_stage_5_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_6_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_6_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_6_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_6_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_6_logical_op__rc__rc 1'0 - assign \core_calculate_stage_6_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_6_logical_op__oe__oe 1'0 - assign \core_calculate_stage_6_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_6_logical_op__invert_in 1'0 - assign \core_calculate_stage_6_logical_op__zero_a 1'0 - assign \core_calculate_stage_6_logical_op__input_carry 2'00 - assign \core_calculate_stage_6_logical_op__invert_out 1'0 - assign \core_calculate_stage_6_logical_op__write_cr0 1'0 - assign \core_calculate_stage_6_logical_op__output_carry 1'0 - assign \core_calculate_stage_6_logical_op__is_32bit 1'0 - assign \core_calculate_stage_6_logical_op__is_signed 1'0 - assign \core_calculate_stage_6_logical_op__data_len 4'0000 - assign \core_calculate_stage_6_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_6_logical_op__insn \core_calculate_stage_6_logical_op__data_len \core_calculate_stage_6_logical_op__is_signed \core_calculate_stage_6_logical_op__is_32bit \core_calculate_stage_6_logical_op__output_carry \core_calculate_stage_6_logical_op__write_cr0 \core_calculate_stage_6_logical_op__invert_out \core_calculate_stage_6_logical_op__input_carry \core_calculate_stage_6_logical_op__zero_a \core_calculate_stage_6_logical_op__invert_in { \core_calculate_stage_6_logical_op__oe__oe_ok \core_calculate_stage_6_logical_op__oe__oe } { \core_calculate_stage_6_logical_op__rc__rc_ok \core_calculate_stage_6_logical_op__rc__rc } { \core_calculate_stage_6_logical_op__imm_data__imm_ok \core_calculate_stage_6_logical_op__imm_data__imm } \core_calculate_stage_6_logical_op__fn_unit \core_calculate_stage_6_logical_op__insn_type } { \core_calculate_stage_5_logical_op__insn$85 \core_calculate_stage_5_logical_op__data_len$84 \core_calculate_stage_5_logical_op__is_signed$83 \core_calculate_stage_5_logical_op__is_32bit$82 \core_calculate_stage_5_logical_op__output_carry$81 \core_calculate_stage_5_logical_op__write_cr0$80 \core_calculate_stage_5_logical_op__invert_out$79 \core_calculate_stage_5_logical_op__input_carry$78 \core_calculate_stage_5_logical_op__zero_a$77 \core_calculate_stage_5_logical_op__invert_in$76 { \core_calculate_stage_5_logical_op__oe__oe_ok$75 \core_calculate_stage_5_logical_op__oe__oe$74 } { \core_calculate_stage_5_logical_op__rc__rc_ok$73 \core_calculate_stage_5_logical_op__rc__rc$72 } { \core_calculate_stage_5_logical_op__imm_data__imm_ok$71 \core_calculate_stage_5_logical_op__imm_data__imm$70 } \core_calculate_stage_5_logical_op__fn_unit$69 \core_calculate_stage_5_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_6_ra \core_calculate_stage_5_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_6_rb \core_calculate_stage_5_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_6_xer_so 1'0 - assign \core_calculate_stage_6_xer_so \core_calculate_stage_5_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_6_divisor_neg 1'0 - assign \core_calculate_stage_6_divisor_neg \core_calculate_stage_5_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_6_dividend_neg 1'0 - assign \core_calculate_stage_6_dividend_neg \core_calculate_stage_5_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_6_dive_abs_ov32 1'0 - assign \core_calculate_stage_6_dive_abs_ov32 \core_calculate_stage_5_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_6_dive_abs_ov64 1'0 - assign \core_calculate_stage_6_dive_abs_ov64 \core_calculate_stage_5_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_6_div_by_zero 1'0 - assign \core_calculate_stage_6_div_by_zero \core_calculate_stage_5_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_6_divisor_radicand \core_calculate_stage_5_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_6_operation 2'00 - assign \core_calculate_stage_6_operation \core_calculate_stage_5_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_6_quotient_root \core_calculate_stage_5_quotient_root$96 - sync init - end - process $group_96 - assign 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process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_7_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_7_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_7_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_7_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_7_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_7_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_7_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.p" -module \p$110 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.n" -module \n$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.trial0" -module \trial0$113 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.trial1" -module \trial1$114 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.pe" -module \pe$115 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core" -module \core$112 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$113 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$114 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$115 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$112 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.trial0" -module \trial0$117 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.trial1" -module \trial1$118 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.pe" -module \pe$119 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core" -module \core$116 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$117 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$118 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$119 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - 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"test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9" -module \core_calculate_stage_9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$116 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.trial0" -module \trial0$121 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.trial1" -module \trial1$122 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.pe" -module \pe$123 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core" -module \core$120 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$121 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$122 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$123 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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"SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$120 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.trial0" -module \trial0$125 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.trial1" -module \trial1$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.pe" -module \pe$127 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core" -module \core$124 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$125 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$126 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$127 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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\nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$124 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$110 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$111 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_8_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_8_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_8_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_8_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_8_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_8_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_8_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_8_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_8_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_8_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_8_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_8_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_8_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_8_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_8_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_8_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_8_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_8_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_8_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_8_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_8_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_8_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_8_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_8_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_8_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_8_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_8_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_8_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_8_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_8_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_8_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_8_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_8_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_8_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_8_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_8_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_8_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_8_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_8_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_8_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_8_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_8_compare_rhs$66 - cell \core_calculate_stage_8 \core_calculate_stage_8 - connect \muxid \core_calculate_stage_8_muxid - connect \logical_op__insn_type \core_calculate_stage_8_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_8_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_8_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_8_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_8_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_8_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_8_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_8_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_8_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_8_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_8_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_8_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_8_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_8_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_8_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_8_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_8_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_8_logical_op__insn - connect \ra \core_calculate_stage_8_ra - connect \rb \core_calculate_stage_8_rb - connect \xer_so \core_calculate_stage_8_xer_so - connect \divisor_neg \core_calculate_stage_8_divisor_neg - connect \dividend_neg \core_calculate_stage_8_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_8_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_8_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_8_div_by_zero - connect \divisor_radicand \core_calculate_stage_8_divisor_radicand - connect \operation \core_calculate_stage_8_operation - connect \quotient_root \core_calculate_stage_8_quotient_root - connect \root_times_radicand \core_calculate_stage_8_root_times_radicand - connect \compare_lhs \core_calculate_stage_8_compare_lhs - connect \compare_rhs \core_calculate_stage_8_compare_rhs - connect \muxid$1 \core_calculate_stage_8_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_8_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_8_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_8_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_8_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_8_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_8_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_8_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_8_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_8_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_8_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_8_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_8_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_8_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_8_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_8_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_8_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_8_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_8_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_8_ra$53 - connect \rb$21 \core_calculate_stage_8_rb$54 - connect \xer_so$22 \core_calculate_stage_8_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_8_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_8_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_8_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_8_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_8_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_8_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_8_operation$62 - connect \quotient_root$30 \core_calculate_stage_8_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_8_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_8_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_8_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_9_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_9_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_9_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_9_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_9_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_9_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_9_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_9_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_9_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_9_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_9_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_9_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_9_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_9_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_9_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_9_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_9_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_9_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_9_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_9_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_9_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_9_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_9_logical_op__insn_type$68 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_9_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_9_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_9_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_9_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_9_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_9_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_9_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_9_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_9_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_9_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_9_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_9_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_9_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_9_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_9_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_9_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_9_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_9_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_9_compare_rhs$99 - cell \core_calculate_stage_9 \core_calculate_stage_9 - connect \muxid \core_calculate_stage_9_muxid - connect \logical_op__insn_type \core_calculate_stage_9_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_9_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_9_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_9_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_9_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_9_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_9_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_9_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_9_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_9_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_9_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_9_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_9_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_9_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_9_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_9_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_9_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_9_logical_op__insn - connect \ra \core_calculate_stage_9_ra - connect \rb \core_calculate_stage_9_rb - connect \xer_so \core_calculate_stage_9_xer_so - connect \divisor_neg \core_calculate_stage_9_divisor_neg - connect \dividend_neg \core_calculate_stage_9_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_9_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_9_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_9_div_by_zero - connect \divisor_radicand \core_calculate_stage_9_divisor_radicand - connect \operation \core_calculate_stage_9_operation - connect \quotient_root \core_calculate_stage_9_quotient_root - connect \root_times_radicand \core_calculate_stage_9_root_times_radicand - connect \compare_lhs \core_calculate_stage_9_compare_lhs - connect \compare_rhs \core_calculate_stage_9_compare_rhs - connect \muxid$1 \core_calculate_stage_9_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_9_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_9_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_9_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_9_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_9_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_9_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_9_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_9_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_9_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_9_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_9_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_9_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_9_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_9_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_9_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_9_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_9_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_9_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_9_ra$86 - connect \rb$21 \core_calculate_stage_9_rb$87 - connect \xer_so$22 \core_calculate_stage_9_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_9_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_9_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_9_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_9_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_9_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_9_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_9_operation$95 - connect \quotient_root$30 \core_calculate_stage_9_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_9_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_9_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_9_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_10_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_10_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_10_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_10_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_10_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_10_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_10_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_10_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_10_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_10_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_10_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_10_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_10_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_10_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_10_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_10_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_10_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_10_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_10_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_10_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_10_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_10_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_10_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_10_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_10_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_10_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_10_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_10_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_10_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_10_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_10_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_10_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_10_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_10_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_10_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_10_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_10_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_10_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_10_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_10_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_10_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_10_compare_rhs$132 - cell \core_calculate_stage_10 \core_calculate_stage_10 - connect \muxid \core_calculate_stage_10_muxid - connect \logical_op__insn_type \core_calculate_stage_10_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_10_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_10_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_10_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_10_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_10_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_10_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_10_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_10_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_10_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_10_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_10_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_10_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_10_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_10_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_10_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_10_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_10_logical_op__insn - connect \ra \core_calculate_stage_10_ra - connect \rb \core_calculate_stage_10_rb - connect \xer_so \core_calculate_stage_10_xer_so - connect \divisor_neg \core_calculate_stage_10_divisor_neg - connect \dividend_neg \core_calculate_stage_10_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_10_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_10_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_10_div_by_zero - connect \divisor_radicand \core_calculate_stage_10_divisor_radicand - connect \operation \core_calculate_stage_10_operation - connect \quotient_root \core_calculate_stage_10_quotient_root - connect \root_times_radicand \core_calculate_stage_10_root_times_radicand - connect \compare_lhs \core_calculate_stage_10_compare_lhs - connect \compare_rhs \core_calculate_stage_10_compare_rhs - connect \muxid$1 \core_calculate_stage_10_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_10_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_10_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_10_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_10_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_10_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_10_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_10_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_10_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_10_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_10_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_10_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_10_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_10_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_10_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_10_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_10_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_10_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_10_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_10_ra$119 - connect \rb$21 \core_calculate_stage_10_rb$120 - connect \xer_so$22 \core_calculate_stage_10_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_10_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_10_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_10_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_10_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_10_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_10_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_10_operation$128 - connect \quotient_root$30 \core_calculate_stage_10_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_10_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_10_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_10_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_11_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_11_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_11_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_11_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_11_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_11_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_11_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_11_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_11_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_11_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_11_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_11_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_11_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_11_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_11_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_11_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_11_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_11_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_11_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_11_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_11_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_11_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_11_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_11_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_11_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_11_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_11_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_11_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_11_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_11_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_11_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_11_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_11_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_11_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_11_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_11_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_11_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_11_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_11_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_11_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_11_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_11_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_11_compare_rhs$165 - cell \core_calculate_stage_11 \core_calculate_stage_11 - connect \muxid \core_calculate_stage_11_muxid - connect \logical_op__insn_type \core_calculate_stage_11_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_11_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_11_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_11_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_11_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_11_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_11_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_11_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_11_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_11_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_11_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_11_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_11_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_11_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_11_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_11_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_11_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_11_logical_op__insn - connect \ra \core_calculate_stage_11_ra - connect \rb \core_calculate_stage_11_rb - connect \xer_so \core_calculate_stage_11_xer_so - connect \divisor_neg \core_calculate_stage_11_divisor_neg - connect \dividend_neg \core_calculate_stage_11_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_11_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_11_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_11_div_by_zero - connect \divisor_radicand \core_calculate_stage_11_divisor_radicand - connect \operation \core_calculate_stage_11_operation - connect \quotient_root \core_calculate_stage_11_quotient_root - connect \root_times_radicand \core_calculate_stage_11_root_times_radicand - connect \compare_lhs \core_calculate_stage_11_compare_lhs - connect \compare_rhs \core_calculate_stage_11_compare_rhs - connect \muxid$1 \core_calculate_stage_11_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_11_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_11_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_11_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_11_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_11_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_11_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_11_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_11_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_11_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_11_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_11_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_11_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_11_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_11_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_11_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_11_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_11_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_11_ra$152 - connect \rb$21 \core_calculate_stage_11_rb$153 - connect \xer_so$22 \core_calculate_stage_11_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_11_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_11_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_11_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_11_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_11_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_11_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_11_operation$161 - connect \quotient_root$30 \core_calculate_stage_11_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_11_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_11_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_11_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_8_muxid 2'00 - assign \core_calculate_stage_8_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_8_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_8_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_8_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_8_logical_op__rc__rc 1'0 - assign \core_calculate_stage_8_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_8_logical_op__oe__oe 1'0 - assign \core_calculate_stage_8_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_8_logical_op__invert_in 1'0 - assign \core_calculate_stage_8_logical_op__zero_a 1'0 - assign \core_calculate_stage_8_logical_op__input_carry 2'00 - assign \core_calculate_stage_8_logical_op__invert_out 1'0 - assign \core_calculate_stage_8_logical_op__write_cr0 1'0 - assign \core_calculate_stage_8_logical_op__output_carry 1'0 - assign \core_calculate_stage_8_logical_op__is_32bit 1'0 - assign \core_calculate_stage_8_logical_op__is_signed 1'0 - assign \core_calculate_stage_8_logical_op__data_len 4'0000 - assign \core_calculate_stage_8_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_8_logical_op__insn \core_calculate_stage_8_logical_op__data_len \core_calculate_stage_8_logical_op__is_signed \core_calculate_stage_8_logical_op__is_32bit \core_calculate_stage_8_logical_op__output_carry \core_calculate_stage_8_logical_op__write_cr0 \core_calculate_stage_8_logical_op__invert_out \core_calculate_stage_8_logical_op__input_carry \core_calculate_stage_8_logical_op__zero_a \core_calculate_stage_8_logical_op__invert_in { \core_calculate_stage_8_logical_op__oe__oe_ok \core_calculate_stage_8_logical_op__oe__oe } { \core_calculate_stage_8_logical_op__rc__rc_ok \core_calculate_stage_8_logical_op__rc__rc } { \core_calculate_stage_8_logical_op__imm_data__imm_ok \core_calculate_stage_8_logical_op__imm_data__imm } \core_calculate_stage_8_logical_op__fn_unit \core_calculate_stage_8_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_8_xer_so 1'0 - assign \core_calculate_stage_8_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_8_divisor_neg 1'0 - assign \core_calculate_stage_8_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_8_dividend_neg 1'0 - assign \core_calculate_stage_8_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_8_dive_abs_ov32 1'0 - assign \core_calculate_stage_8_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_8_dive_abs_ov64 1'0 - assign \core_calculate_stage_8_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_8_div_by_zero 1'0 - assign \core_calculate_stage_8_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_8_operation 2'00 - assign \core_calculate_stage_8_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_8_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_9_muxid 2'00 - assign \core_calculate_stage_9_muxid \core_calculate_stage_8_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_9_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_9_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_9_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_9_logical_op__rc__rc 1'0 - assign \core_calculate_stage_9_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_9_logical_op__oe__oe 1'0 - assign \core_calculate_stage_9_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_9_logical_op__invert_in 1'0 - assign \core_calculate_stage_9_logical_op__zero_a 1'0 - assign \core_calculate_stage_9_logical_op__input_carry 2'00 - assign \core_calculate_stage_9_logical_op__invert_out 1'0 - assign \core_calculate_stage_9_logical_op__write_cr0 1'0 - assign \core_calculate_stage_9_logical_op__output_carry 1'0 - assign \core_calculate_stage_9_logical_op__is_32bit 1'0 - assign \core_calculate_stage_9_logical_op__is_signed 1'0 - assign \core_calculate_stage_9_logical_op__data_len 4'0000 - assign \core_calculate_stage_9_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_9_logical_op__insn \core_calculate_stage_9_logical_op__data_len \core_calculate_stage_9_logical_op__is_signed \core_calculate_stage_9_logical_op__is_32bit \core_calculate_stage_9_logical_op__output_carry \core_calculate_stage_9_logical_op__write_cr0 \core_calculate_stage_9_logical_op__invert_out \core_calculate_stage_9_logical_op__input_carry \core_calculate_stage_9_logical_op__zero_a \core_calculate_stage_9_logical_op__invert_in { \core_calculate_stage_9_logical_op__oe__oe_ok \core_calculate_stage_9_logical_op__oe__oe } { \core_calculate_stage_9_logical_op__rc__rc_ok \core_calculate_stage_9_logical_op__rc__rc } { \core_calculate_stage_9_logical_op__imm_data__imm_ok \core_calculate_stage_9_logical_op__imm_data__imm } \core_calculate_stage_9_logical_op__fn_unit \core_calculate_stage_9_logical_op__insn_type } { \core_calculate_stage_8_logical_op__insn$52 \core_calculate_stage_8_logical_op__data_len$51 \core_calculate_stage_8_logical_op__is_signed$50 \core_calculate_stage_8_logical_op__is_32bit$49 \core_calculate_stage_8_logical_op__output_carry$48 \core_calculate_stage_8_logical_op__write_cr0$47 \core_calculate_stage_8_logical_op__invert_out$46 \core_calculate_stage_8_logical_op__input_carry$45 \core_calculate_stage_8_logical_op__zero_a$44 \core_calculate_stage_8_logical_op__invert_in$43 { \core_calculate_stage_8_logical_op__oe__oe_ok$42 \core_calculate_stage_8_logical_op__oe__oe$41 } { \core_calculate_stage_8_logical_op__rc__rc_ok$40 \core_calculate_stage_8_logical_op__rc__rc$39 } { \core_calculate_stage_8_logical_op__imm_data__imm_ok$38 \core_calculate_stage_8_logical_op__imm_data__imm$37 } \core_calculate_stage_8_logical_op__fn_unit$36 \core_calculate_stage_8_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_9_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_ra \core_calculate_stage_8_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_9_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_rb \core_calculate_stage_8_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_9_xer_so 1'0 - assign \core_calculate_stage_9_xer_so \core_calculate_stage_8_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_9_divisor_neg 1'0 - assign \core_calculate_stage_9_divisor_neg \core_calculate_stage_8_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_9_dividend_neg 1'0 - assign \core_calculate_stage_9_dividend_neg \core_calculate_stage_8_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_9_dive_abs_ov32 1'0 - assign \core_calculate_stage_9_dive_abs_ov32 \core_calculate_stage_8_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_9_dive_abs_ov64 1'0 - assign \core_calculate_stage_9_dive_abs_ov64 \core_calculate_stage_8_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_9_div_by_zero 1'0 - assign \core_calculate_stage_9_div_by_zero \core_calculate_stage_8_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_9_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_divisor_radicand \core_calculate_stage_8_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_9_operation 2'00 - assign \core_calculate_stage_9_operation \core_calculate_stage_8_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_9_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_quotient_root \core_calculate_stage_8_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_9_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_root_times_radicand \core_calculate_stage_8_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_9_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_compare_lhs \core_calculate_stage_8_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_9_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_9_compare_rhs \core_calculate_stage_8_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_10_muxid 2'00 - assign \core_calculate_stage_10_muxid \core_calculate_stage_9_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_10_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_10_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_10_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_10_logical_op__rc__rc 1'0 - assign \core_calculate_stage_10_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_10_logical_op__oe__oe 1'0 - assign \core_calculate_stage_10_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_10_logical_op__invert_in 1'0 - assign \core_calculate_stage_10_logical_op__zero_a 1'0 - assign \core_calculate_stage_10_logical_op__input_carry 2'00 - assign \core_calculate_stage_10_logical_op__invert_out 1'0 - assign \core_calculate_stage_10_logical_op__write_cr0 1'0 - assign \core_calculate_stage_10_logical_op__output_carry 1'0 - assign \core_calculate_stage_10_logical_op__is_32bit 1'0 - assign \core_calculate_stage_10_logical_op__is_signed 1'0 - assign \core_calculate_stage_10_logical_op__data_len 4'0000 - assign \core_calculate_stage_10_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_10_logical_op__insn \core_calculate_stage_10_logical_op__data_len \core_calculate_stage_10_logical_op__is_signed \core_calculate_stage_10_logical_op__is_32bit \core_calculate_stage_10_logical_op__output_carry \core_calculate_stage_10_logical_op__write_cr0 \core_calculate_stage_10_logical_op__invert_out \core_calculate_stage_10_logical_op__input_carry \core_calculate_stage_10_logical_op__zero_a \core_calculate_stage_10_logical_op__invert_in { \core_calculate_stage_10_logical_op__oe__oe_ok \core_calculate_stage_10_logical_op__oe__oe } { \core_calculate_stage_10_logical_op__rc__rc_ok \core_calculate_stage_10_logical_op__rc__rc } { \core_calculate_stage_10_logical_op__imm_data__imm_ok \core_calculate_stage_10_logical_op__imm_data__imm } \core_calculate_stage_10_logical_op__fn_unit \core_calculate_stage_10_logical_op__insn_type } { \core_calculate_stage_9_logical_op__insn$85 \core_calculate_stage_9_logical_op__data_len$84 \core_calculate_stage_9_logical_op__is_signed$83 \core_calculate_stage_9_logical_op__is_32bit$82 \core_calculate_stage_9_logical_op__output_carry$81 \core_calculate_stage_9_logical_op__write_cr0$80 \core_calculate_stage_9_logical_op__invert_out$79 \core_calculate_stage_9_logical_op__input_carry$78 \core_calculate_stage_9_logical_op__zero_a$77 \core_calculate_stage_9_logical_op__invert_in$76 { \core_calculate_stage_9_logical_op__oe__oe_ok$75 \core_calculate_stage_9_logical_op__oe__oe$74 } { \core_calculate_stage_9_logical_op__rc__rc_ok$73 \core_calculate_stage_9_logical_op__rc__rc$72 } { \core_calculate_stage_9_logical_op__imm_data__imm_ok$71 \core_calculate_stage_9_logical_op__imm_data__imm$70 } \core_calculate_stage_9_logical_op__fn_unit$69 \core_calculate_stage_9_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_ra \core_calculate_stage_9_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_rb \core_calculate_stage_9_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_10_xer_so 1'0 - assign \core_calculate_stage_10_xer_so \core_calculate_stage_9_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_10_divisor_neg 1'0 - assign \core_calculate_stage_10_divisor_neg \core_calculate_stage_9_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_10_dividend_neg 1'0 - assign \core_calculate_stage_10_dividend_neg \core_calculate_stage_9_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_10_dive_abs_ov32 1'0 - assign \core_calculate_stage_10_dive_abs_ov32 \core_calculate_stage_9_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_10_dive_abs_ov64 1'0 - assign \core_calculate_stage_10_dive_abs_ov64 \core_calculate_stage_9_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_10_div_by_zero 1'0 - assign \core_calculate_stage_10_div_by_zero \core_calculate_stage_9_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_divisor_radicand \core_calculate_stage_9_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_10_operation 2'00 - assign \core_calculate_stage_10_operation \core_calculate_stage_9_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_quotient_root \core_calculate_stage_9_quotient_root$96 - sync init - end - process $group_96 - assign \core_calculate_stage_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_root_times_radicand \core_calculate_stage_9_root_times_radicand$97 - sync init - end - process $group_97 - assign \core_calculate_stage_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_compare_lhs \core_calculate_stage_9_compare_lhs$98 - sync init - end - process $group_98 - assign \core_calculate_stage_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_10_compare_rhs \core_calculate_stage_9_compare_rhs$99 - sync init - end - process $group_99 - assign \core_calculate_stage_11_muxid 2'00 - assign \core_calculate_stage_11_muxid \core_calculate_stage_10_muxid$100 - sync init - end - process $group_100 - assign \core_calculate_stage_11_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_11_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_11_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_11_logical_op__rc__rc 1'0 - assign \core_calculate_stage_11_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_11_logical_op__oe__oe 1'0 - assign \core_calculate_stage_11_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_11_logical_op__invert_in 1'0 - assign \core_calculate_stage_11_logical_op__zero_a 1'0 - assign \core_calculate_stage_11_logical_op__input_carry 2'00 - assign \core_calculate_stage_11_logical_op__invert_out 1'0 - assign \core_calculate_stage_11_logical_op__write_cr0 1'0 - assign \core_calculate_stage_11_logical_op__output_carry 1'0 - assign \core_calculate_stage_11_logical_op__is_32bit 1'0 - assign \core_calculate_stage_11_logical_op__is_signed 1'0 - assign \core_calculate_stage_11_logical_op__data_len 4'0000 - assign \core_calculate_stage_11_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_11_logical_op__insn \core_calculate_stage_11_logical_op__data_len \core_calculate_stage_11_logical_op__is_signed \core_calculate_stage_11_logical_op__is_32bit \core_calculate_stage_11_logical_op__output_carry \core_calculate_stage_11_logical_op__write_cr0 \core_calculate_stage_11_logical_op__invert_out \core_calculate_stage_11_logical_op__input_carry \core_calculate_stage_11_logical_op__zero_a \core_calculate_stage_11_logical_op__invert_in { \core_calculate_stage_11_logical_op__oe__oe_ok \core_calculate_stage_11_logical_op__oe__oe } { \core_calculate_stage_11_logical_op__rc__rc_ok \core_calculate_stage_11_logical_op__rc__rc } { \core_calculate_stage_11_logical_op__imm_data__imm_ok \core_calculate_stage_11_logical_op__imm_data__imm } \core_calculate_stage_11_logical_op__fn_unit \core_calculate_stage_11_logical_op__insn_type } { \core_calculate_stage_10_logical_op__insn$118 \core_calculate_stage_10_logical_op__data_len$117 \core_calculate_stage_10_logical_op__is_signed$116 \core_calculate_stage_10_logical_op__is_32bit$115 \core_calculate_stage_10_logical_op__output_carry$114 \core_calculate_stage_10_logical_op__write_cr0$113 \core_calculate_stage_10_logical_op__invert_out$112 \core_calculate_stage_10_logical_op__input_carry$111 \core_calculate_stage_10_logical_op__zero_a$110 \core_calculate_stage_10_logical_op__invert_in$109 { \core_calculate_stage_10_logical_op__oe__oe_ok$108 \core_calculate_stage_10_logical_op__oe__oe$107 } { \core_calculate_stage_10_logical_op__rc__rc_ok$106 \core_calculate_stage_10_logical_op__rc__rc$105 } { \core_calculate_stage_10_logical_op__imm_data__imm_ok$104 \core_calculate_stage_10_logical_op__imm_data__imm$103 } \core_calculate_stage_10_logical_op__fn_unit$102 \core_calculate_stage_10_logical_op__insn_type$101 } - sync init - end - process $group_118 - assign \core_calculate_stage_11_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_ra \core_calculate_stage_10_ra$119 - sync init - end - process $group_119 - assign \core_calculate_stage_11_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_rb \core_calculate_stage_10_rb$120 - sync init - end - process $group_120 - assign \core_calculate_stage_11_xer_so 1'0 - assign \core_calculate_stage_11_xer_so \core_calculate_stage_10_xer_so$121 - sync init - end - process $group_121 - assign \core_calculate_stage_11_divisor_neg 1'0 - assign \core_calculate_stage_11_divisor_neg \core_calculate_stage_10_divisor_neg$122 - sync init - end - process $group_122 - assign \core_calculate_stage_11_dividend_neg 1'0 - assign \core_calculate_stage_11_dividend_neg \core_calculate_stage_10_dividend_neg$123 - sync init - end - process $group_123 - assign \core_calculate_stage_11_dive_abs_ov32 1'0 - assign \core_calculate_stage_11_dive_abs_ov32 \core_calculate_stage_10_dive_abs_ov32$124 - sync init - end - process $group_124 - assign \core_calculate_stage_11_dive_abs_ov64 1'0 - assign \core_calculate_stage_11_dive_abs_ov64 \core_calculate_stage_10_dive_abs_ov64$125 - sync init - end - process $group_125 - assign \core_calculate_stage_11_div_by_zero 1'0 - assign \core_calculate_stage_11_div_by_zero \core_calculate_stage_10_div_by_zero$126 - sync init - end - process $group_126 - assign \core_calculate_stage_11_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_divisor_radicand \core_calculate_stage_10_divisor_radicand$127 - sync init - end - process $group_127 - assign \core_calculate_stage_11_operation 2'00 - assign \core_calculate_stage_11_operation \core_calculate_stage_10_operation$128 - sync init - end - process $group_128 - assign \core_calculate_stage_11_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_quotient_root \core_calculate_stage_10_quotient_root$129 - sync init - end - process $group_129 - assign \core_calculate_stage_11_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_root_times_radicand \core_calculate_stage_10_root_times_radicand$130 - sync init - end - process $group_130 - assign \core_calculate_stage_11_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_compare_lhs \core_calculate_stage_10_compare_lhs$131 - sync init - end - process $group_131 - assign \core_calculate_stage_11_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_11_compare_rhs \core_calculate_stage_10_compare_rhs$132 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$166 - process $group_132 - assign \p_valid_i$166 1'0 - assign \p_valid_i$166 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_133 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_11_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_11_logical_op__insn$151 \core_calculate_stage_11_logical_op__data_len$150 \core_calculate_stage_11_logical_op__is_signed$149 \core_calculate_stage_11_logical_op__is_32bit$148 \core_calculate_stage_11_logical_op__output_carry$147 \core_calculate_stage_11_logical_op__write_cr0$146 \core_calculate_stage_11_logical_op__invert_out$145 \core_calculate_stage_11_logical_op__input_carry$144 \core_calculate_stage_11_logical_op__zero_a$143 \core_calculate_stage_11_logical_op__invert_in$142 { \core_calculate_stage_11_logical_op__oe__oe_ok$141 \core_calculate_stage_11_logical_op__oe__oe$140 } { \core_calculate_stage_11_logical_op__rc__rc_ok$139 \core_calculate_stage_11_logical_op__rc__rc$138 } { \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 \core_calculate_stage_11_logical_op__imm_data__imm$136 } \core_calculate_stage_11_logical_op__fn_unit$135 \core_calculate_stage_11_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_11_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_11_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_11_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_11_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_11_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_11_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_11_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_11_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_11_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_11_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_11_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_11_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_11_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_11_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.p" -module \p$128 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.n" -module \n$129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.trial0" -module \trial0$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.trial1" -module \trial1$132 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.pe" -module \pe$133 - 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\B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core" -module \core$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$131 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$132 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$133 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$130 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.trial0" -module \trial0$135 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.trial1" -module \trial1$136 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.pe" -module \pe$137 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core" -module \core$134 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$135 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$136 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$137 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 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\A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$134 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core.trial0" -module \trial0$139 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core.trial1" -module \trial1$140 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$139 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$140 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$141 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe 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width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$138 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.trial0" -module \trial0$143 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.trial1" -module \trial1$144 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1110000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.pe" -module \pe$145 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core" -module \core$142 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$143 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$144 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$145 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'110000 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15" -module \core_calculate_stage_15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$142 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { 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64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - 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192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end 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\logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$128 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$129 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_12_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_12_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_12_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_12_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_12_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_12_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_12_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_12_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_12_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_12_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_12_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_12_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_12_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_12_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_12_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_12_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_12_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_12_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_12_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_12_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_12_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_12_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_12_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_12_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_12_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_12_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_12_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_12_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_12_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_12_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_12_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_12_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_12_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_12_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_12_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_12_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_12_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_12_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_12_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_12_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_12_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_12_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_12_compare_rhs$66 - cell \core_calculate_stage_12 \core_calculate_stage_12 - connect \muxid \core_calculate_stage_12_muxid - connect \logical_op__insn_type \core_calculate_stage_12_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_12_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_12_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_12_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_12_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_12_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_12_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_12_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_12_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_12_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_12_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_12_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_12_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_12_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_12_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_12_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_12_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_12_logical_op__insn - connect \ra \core_calculate_stage_12_ra - connect \rb \core_calculate_stage_12_rb - connect \xer_so \core_calculate_stage_12_xer_so - connect \divisor_neg \core_calculate_stage_12_divisor_neg - connect \dividend_neg \core_calculate_stage_12_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_12_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_12_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_12_div_by_zero - connect \divisor_radicand \core_calculate_stage_12_divisor_radicand - connect \operation \core_calculate_stage_12_operation - connect \quotient_root \core_calculate_stage_12_quotient_root - connect \root_times_radicand \core_calculate_stage_12_root_times_radicand - connect \compare_lhs \core_calculate_stage_12_compare_lhs - connect \compare_rhs \core_calculate_stage_12_compare_rhs - connect \muxid$1 \core_calculate_stage_12_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_12_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_12_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_12_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_12_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_12_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_12_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_12_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_12_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_12_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_12_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_12_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_12_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_12_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_12_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_12_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_12_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_12_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_12_ra$53 - connect \rb$21 \core_calculate_stage_12_rb$54 - connect \xer_so$22 \core_calculate_stage_12_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_12_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_12_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_12_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_12_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_12_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_12_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_12_operation$62 - connect \quotient_root$30 \core_calculate_stage_12_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_12_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_12_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_12_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_13_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_13_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_13_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_13_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_13_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_13_logical_op__input_carry - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_13_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_13_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_13_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_13_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_13_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_13_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_13_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_13_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_13_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_13_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_13_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_13_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_13_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_13_compare_rhs - attribute \src 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_13_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_13_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_13_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_13_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_13_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_13_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_13_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_13_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_13_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_13_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_13_compare_rhs$99 - cell \core_calculate_stage_13 \core_calculate_stage_13 - connect \muxid \core_calculate_stage_13_muxid - connect \logical_op__insn_type \core_calculate_stage_13_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_13_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_13_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_13_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_13_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_13_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_13_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_13_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_13_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_13_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_13_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_13_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_13_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_13_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_13_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_13_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_13_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_13_logical_op__insn - connect \ra \core_calculate_stage_13_ra - connect \rb \core_calculate_stage_13_rb - connect \xer_so \core_calculate_stage_13_xer_so - connect \divisor_neg \core_calculate_stage_13_divisor_neg - connect \dividend_neg \core_calculate_stage_13_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_13_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_13_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_13_div_by_zero - connect \divisor_radicand \core_calculate_stage_13_divisor_radicand - connect \operation \core_calculate_stage_13_operation - connect \quotient_root \core_calculate_stage_13_quotient_root - connect \root_times_radicand \core_calculate_stage_13_root_times_radicand - connect \compare_lhs \core_calculate_stage_13_compare_lhs - connect \compare_rhs \core_calculate_stage_13_compare_rhs - connect \muxid$1 \core_calculate_stage_13_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_13_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_13_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_13_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_13_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_13_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_13_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_13_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_13_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_13_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_13_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_13_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_13_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_13_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_13_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_13_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_13_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_13_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_13_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_13_ra$86 - connect \rb$21 \core_calculate_stage_13_rb$87 - connect \xer_so$22 \core_calculate_stage_13_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_13_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_13_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_13_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_13_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_13_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_13_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_13_operation$95 - connect \quotient_root$30 \core_calculate_stage_13_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_13_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_13_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_13_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_14_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_14_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_14_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_14_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_14_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_14_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_14_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_14_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_14_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_14_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_14_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_14_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_14_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_14_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_14_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_14_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_14_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_14_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_14_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_14_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_14_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_14_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_14_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_14_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_14_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_14_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_14_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_14_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_14_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_14_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_14_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_14_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_14_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_14_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_14_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_14_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_14_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_14_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_14_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_14_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_14_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_14_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_14_compare_rhs$132 - cell \core_calculate_stage_14 \core_calculate_stage_14 - connect \muxid \core_calculate_stage_14_muxid - connect \logical_op__insn_type \core_calculate_stage_14_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_14_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_14_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_14_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_14_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_14_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_14_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_14_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_14_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_14_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_14_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_14_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_14_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_14_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_14_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_14_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_14_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_14_logical_op__insn - connect \ra \core_calculate_stage_14_ra - connect \rb \core_calculate_stage_14_rb - connect \xer_so \core_calculate_stage_14_xer_so - connect \divisor_neg \core_calculate_stage_14_divisor_neg - connect \dividend_neg \core_calculate_stage_14_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_14_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_14_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_14_div_by_zero - connect \divisor_radicand \core_calculate_stage_14_divisor_radicand - connect \operation \core_calculate_stage_14_operation - connect \quotient_root \core_calculate_stage_14_quotient_root - connect \root_times_radicand \core_calculate_stage_14_root_times_radicand - connect \compare_lhs \core_calculate_stage_14_compare_lhs - connect \compare_rhs \core_calculate_stage_14_compare_rhs - connect \muxid$1 \core_calculate_stage_14_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_14_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_14_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_14_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_14_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_14_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_14_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_14_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_14_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_14_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_14_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_14_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_14_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_14_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_14_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_14_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_14_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_14_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_14_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_14_ra$119 - connect \rb$21 \core_calculate_stage_14_rb$120 - connect \xer_so$22 \core_calculate_stage_14_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_14_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_14_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_14_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_14_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_14_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_14_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_14_operation$128 - connect \quotient_root$30 \core_calculate_stage_14_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_14_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_14_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_14_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_15_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_15_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_15_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_15_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_15_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_15_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_15_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_15_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_15_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_15_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_15_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_15_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_15_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_15_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_15_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_15_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_15_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_15_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_15_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_15_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_15_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_15_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_15_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_15_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_15_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_15_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_15_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_15_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_15_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_15_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_15_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_15_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_15_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_15_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_15_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_15_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_15_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_15_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_15_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_15_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_15_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_15_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_15_compare_rhs$165 - cell \core_calculate_stage_15 \core_calculate_stage_15 - connect \muxid \core_calculate_stage_15_muxid - connect \logical_op__insn_type \core_calculate_stage_15_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_15_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_15_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_15_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_15_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_15_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_15_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_15_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_15_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_15_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_15_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_15_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_15_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_15_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_15_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_15_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_15_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_15_logical_op__insn - connect \ra \core_calculate_stage_15_ra - connect \rb \core_calculate_stage_15_rb - connect \xer_so \core_calculate_stage_15_xer_so - connect \divisor_neg \core_calculate_stage_15_divisor_neg - connect \dividend_neg \core_calculate_stage_15_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_15_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_15_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_15_div_by_zero - connect \divisor_radicand \core_calculate_stage_15_divisor_radicand - connect \operation \core_calculate_stage_15_operation - connect \quotient_root \core_calculate_stage_15_quotient_root - connect \root_times_radicand \core_calculate_stage_15_root_times_radicand - connect \compare_lhs \core_calculate_stage_15_compare_lhs - connect \compare_rhs \core_calculate_stage_15_compare_rhs - connect \muxid$1 \core_calculate_stage_15_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_15_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_15_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_15_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_15_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_15_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_15_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_15_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_15_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_15_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_15_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_15_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_15_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_15_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_15_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_15_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_15_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_15_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_15_ra$152 - connect \rb$21 \core_calculate_stage_15_rb$153 - connect \xer_so$22 \core_calculate_stage_15_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_15_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_15_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_15_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_15_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_15_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_15_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_15_operation$161 - connect \quotient_root$30 \core_calculate_stage_15_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_15_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_15_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_15_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_12_muxid 2'00 - assign \core_calculate_stage_12_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_12_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_12_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_12_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_12_logical_op__rc__rc 1'0 - assign \core_calculate_stage_12_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_12_logical_op__oe__oe 1'0 - assign \core_calculate_stage_12_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_12_logical_op__invert_in 1'0 - assign \core_calculate_stage_12_logical_op__zero_a 1'0 - assign \core_calculate_stage_12_logical_op__input_carry 2'00 - assign \core_calculate_stage_12_logical_op__invert_out 1'0 - assign \core_calculate_stage_12_logical_op__write_cr0 1'0 - assign \core_calculate_stage_12_logical_op__output_carry 1'0 - assign \core_calculate_stage_12_logical_op__is_32bit 1'0 - assign \core_calculate_stage_12_logical_op__is_signed 1'0 - assign \core_calculate_stage_12_logical_op__data_len 4'0000 - assign \core_calculate_stage_12_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_12_logical_op__insn \core_calculate_stage_12_logical_op__data_len \core_calculate_stage_12_logical_op__is_signed \core_calculate_stage_12_logical_op__is_32bit \core_calculate_stage_12_logical_op__output_carry \core_calculate_stage_12_logical_op__write_cr0 \core_calculate_stage_12_logical_op__invert_out \core_calculate_stage_12_logical_op__input_carry \core_calculate_stage_12_logical_op__zero_a \core_calculate_stage_12_logical_op__invert_in { \core_calculate_stage_12_logical_op__oe__oe_ok \core_calculate_stage_12_logical_op__oe__oe } { \core_calculate_stage_12_logical_op__rc__rc_ok \core_calculate_stage_12_logical_op__rc__rc } { \core_calculate_stage_12_logical_op__imm_data__imm_ok \core_calculate_stage_12_logical_op__imm_data__imm } \core_calculate_stage_12_logical_op__fn_unit \core_calculate_stage_12_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_12_xer_so 1'0 - assign \core_calculate_stage_12_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_12_divisor_neg 1'0 - assign \core_calculate_stage_12_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_12_dividend_neg 1'0 - assign \core_calculate_stage_12_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_12_dive_abs_ov32 1'0 - assign \core_calculate_stage_12_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_12_dive_abs_ov64 1'0 - assign \core_calculate_stage_12_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_12_div_by_zero 1'0 - assign \core_calculate_stage_12_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_12_operation 2'00 - assign \core_calculate_stage_12_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_12_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_13_muxid 2'00 - assign \core_calculate_stage_13_muxid \core_calculate_stage_12_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_13_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_13_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_13_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_13_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_13_logical_op__rc__rc 1'0 - assign \core_calculate_stage_13_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_13_logical_op__oe__oe 1'0 - assign \core_calculate_stage_13_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_13_logical_op__invert_in 1'0 - assign \core_calculate_stage_13_logical_op__zero_a 1'0 - assign \core_calculate_stage_13_logical_op__input_carry 2'00 - assign \core_calculate_stage_13_logical_op__invert_out 1'0 - assign \core_calculate_stage_13_logical_op__write_cr0 1'0 - assign \core_calculate_stage_13_logical_op__output_carry 1'0 - assign \core_calculate_stage_13_logical_op__is_32bit 1'0 - assign \core_calculate_stage_13_logical_op__is_signed 1'0 - assign \core_calculate_stage_13_logical_op__data_len 4'0000 - assign \core_calculate_stage_13_logical_op__insn 32'00000000000000000000000000000000 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\core_calculate_stage_12_logical_op__is_signed$50 \core_calculate_stage_12_logical_op__is_32bit$49 \core_calculate_stage_12_logical_op__output_carry$48 \core_calculate_stage_12_logical_op__write_cr0$47 \core_calculate_stage_12_logical_op__invert_out$46 \core_calculate_stage_12_logical_op__input_carry$45 \core_calculate_stage_12_logical_op__zero_a$44 \core_calculate_stage_12_logical_op__invert_in$43 { \core_calculate_stage_12_logical_op__oe__oe_ok$42 \core_calculate_stage_12_logical_op__oe__oe$41 } { \core_calculate_stage_12_logical_op__rc__rc_ok$40 \core_calculate_stage_12_logical_op__rc__rc$39 } { \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 \core_calculate_stage_12_logical_op__imm_data__imm$37 } \core_calculate_stage_12_logical_op__fn_unit$36 \core_calculate_stage_12_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_13_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_13_ra 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\core_calculate_stage_12_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_14_muxid 2'00 - assign \core_calculate_stage_14_muxid \core_calculate_stage_13_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_14_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_14_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_14_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_14_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_14_logical_op__rc__rc 1'0 - assign \core_calculate_stage_14_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_14_logical_op__oe__oe 1'0 - assign \core_calculate_stage_14_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_14_logical_op__invert_in 1'0 - assign \core_calculate_stage_14_logical_op__zero_a 1'0 - assign \core_calculate_stage_14_logical_op__input_carry 2'00 - assign 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\core_calculate_stage_14_logical_op__oe__oe } { \core_calculate_stage_14_logical_op__rc__rc_ok \core_calculate_stage_14_logical_op__rc__rc } { \core_calculate_stage_14_logical_op__imm_data__imm_ok \core_calculate_stage_14_logical_op__imm_data__imm } \core_calculate_stage_14_logical_op__fn_unit \core_calculate_stage_14_logical_op__insn_type } { \core_calculate_stage_13_logical_op__insn$85 \core_calculate_stage_13_logical_op__data_len$84 \core_calculate_stage_13_logical_op__is_signed$83 \core_calculate_stage_13_logical_op__is_32bit$82 \core_calculate_stage_13_logical_op__output_carry$81 \core_calculate_stage_13_logical_op__write_cr0$80 \core_calculate_stage_13_logical_op__invert_out$79 \core_calculate_stage_13_logical_op__input_carry$78 \core_calculate_stage_13_logical_op__zero_a$77 \core_calculate_stage_13_logical_op__invert_in$76 { \core_calculate_stage_13_logical_op__oe__oe_ok$75 \core_calculate_stage_13_logical_op__oe__oe$74 } { \core_calculate_stage_13_logical_op__rc__rc_ok$73 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\enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_15_logical_op__insn$151 \core_calculate_stage_15_logical_op__data_len$150 \core_calculate_stage_15_logical_op__is_signed$149 \core_calculate_stage_15_logical_op__is_32bit$148 \core_calculate_stage_15_logical_op__output_carry$147 \core_calculate_stage_15_logical_op__write_cr0$146 \core_calculate_stage_15_logical_op__invert_out$145 \core_calculate_stage_15_logical_op__input_carry$144 \core_calculate_stage_15_logical_op__zero_a$143 \core_calculate_stage_15_logical_op__invert_in$142 { \core_calculate_stage_15_logical_op__oe__oe_ok$141 \core_calculate_stage_15_logical_op__oe__oe$140 } { \core_calculate_stage_15_logical_op__rc__rc_ok$139 \core_calculate_stage_15_logical_op__rc__rc$138 } { \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 \core_calculate_stage_15_logical_op__imm_data__imm$136 } \core_calculate_stage_15_logical_op__fn_unit$135 \core_calculate_stage_15_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_15_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_15_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_15_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_15_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_15_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_15_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_15_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_15_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_15_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_15_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_15_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_15_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_15_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_15_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.p" -module \p$146 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.n" -module \n$147 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.trial0" -module \trial0$149 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.trial1" -module \trial1$150 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.pe" -module \pe$151 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core" -module \core$148 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$149 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$150 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$151 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16" -module \core_calculate_stage_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$148 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.trial0" -module \trial0$153 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.trial1" -module \trial1$154 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.pe" -module \pe$155 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core" -module \core$152 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$153 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$154 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$155 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 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\A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$152 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.trial0" -module \trial0$157 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.trial1" -module \trial1$158 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.pe" -module \pe$159 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core" -module \core$156 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$157 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$158 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$159 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'101101 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$156 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.trial0" -module \trial0$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.trial1" -module \trial1$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.pe" -module \pe$163 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core" -module \core$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$161 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$162 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$163 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$160 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4" -module \pipe_middle_4 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute 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"ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$146 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$147 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_16_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_16_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_16_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_16_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_16_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_16_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_16_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_16_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_16_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_16_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_16_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_16_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_16_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_16_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_16_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 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"OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_16_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_16_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_16_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_16_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_16_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_16_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_16_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_16_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_16_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_16_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_16_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_16_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_16_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_16_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_16_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_16_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_16_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_16_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_16_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_16_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_16_compare_rhs$66 - cell \core_calculate_stage_16 \core_calculate_stage_16 - connect \muxid \core_calculate_stage_16_muxid - connect \logical_op__insn_type \core_calculate_stage_16_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_16_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_16_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_16_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_16_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_16_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_16_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_16_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_16_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_16_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_16_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_16_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_16_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_16_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_16_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_16_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_16_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_16_logical_op__insn - connect \ra \core_calculate_stage_16_ra - connect \rb \core_calculate_stage_16_rb - connect \xer_so \core_calculate_stage_16_xer_so - connect \divisor_neg \core_calculate_stage_16_divisor_neg - connect \dividend_neg \core_calculate_stage_16_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_16_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_16_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_16_div_by_zero - connect \divisor_radicand \core_calculate_stage_16_divisor_radicand - connect \operation \core_calculate_stage_16_operation - connect \quotient_root \core_calculate_stage_16_quotient_root - connect \root_times_radicand \core_calculate_stage_16_root_times_radicand - connect \compare_lhs \core_calculate_stage_16_compare_lhs - connect \compare_rhs \core_calculate_stage_16_compare_rhs - connect \muxid$1 \core_calculate_stage_16_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_16_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_16_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_16_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_16_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_16_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_16_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_16_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_16_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_16_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_16_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_16_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_16_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_16_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_16_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_16_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_16_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_16_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_16_ra$53 - connect \rb$21 \core_calculate_stage_16_rb$54 - connect \xer_so$22 \core_calculate_stage_16_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_16_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_16_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_16_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_16_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_16_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_16_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_16_operation$62 - connect \quotient_root$30 \core_calculate_stage_16_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_16_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_16_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_16_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_17_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute 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11 \core_calculate_stage_17_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_17_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_17_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_17_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_17_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_17_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_17_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_17_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_17_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_17_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_17_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_17_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_17_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_17_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_17_compare_rhs$99 - cell \core_calculate_stage_17 \core_calculate_stage_17 - connect \muxid \core_calculate_stage_17_muxid - connect \logical_op__insn_type \core_calculate_stage_17_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_17_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_17_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_17_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_17_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_17_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_17_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_17_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_17_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_17_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_17_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_17_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_17_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_17_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_17_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_17_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_17_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_17_logical_op__insn - connect \ra \core_calculate_stage_17_ra - connect \rb \core_calculate_stage_17_rb - connect \xer_so \core_calculate_stage_17_xer_so - connect \divisor_neg \core_calculate_stage_17_divisor_neg - connect \dividend_neg \core_calculate_stage_17_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_17_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_17_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_17_div_by_zero - connect \divisor_radicand \core_calculate_stage_17_divisor_radicand - connect \operation \core_calculate_stage_17_operation - connect \quotient_root \core_calculate_stage_17_quotient_root - connect \root_times_radicand \core_calculate_stage_17_root_times_radicand - connect \compare_lhs \core_calculate_stage_17_compare_lhs - connect \compare_rhs \core_calculate_stage_17_compare_rhs - connect \muxid$1 \core_calculate_stage_17_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_17_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_17_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_17_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_17_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_17_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_17_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_17_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_17_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_17_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_17_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_17_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_17_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_17_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_17_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_17_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_17_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_17_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_17_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_17_ra$86 - connect \rb$21 \core_calculate_stage_17_rb$87 - connect \xer_so$22 \core_calculate_stage_17_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_17_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_17_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_17_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_17_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_17_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_17_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_17_operation$95 - connect \quotient_root$30 \core_calculate_stage_17_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_17_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_17_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_17_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_18_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_18_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_18_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_18_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_18_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_18_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_18_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_18_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_18_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_18_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_18_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_18_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_18_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_18_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_18_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_18_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_18_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_18_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_18_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_18_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_18_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_18_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_18_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_18_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_18_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_18_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_18_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_18_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_18_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_18_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_18_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_18_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_18_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_18_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_18_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_18_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_18_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_18_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_18_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_18_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_18_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_18_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_18_compare_rhs$132 - cell \core_calculate_stage_18 \core_calculate_stage_18 - connect \muxid \core_calculate_stage_18_muxid - connect \logical_op__insn_type \core_calculate_stage_18_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_18_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_18_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_18_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_18_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_18_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_18_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_18_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_18_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_18_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_18_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_18_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_18_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_18_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_18_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_18_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_18_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_18_logical_op__insn - connect \ra \core_calculate_stage_18_ra - connect \rb \core_calculate_stage_18_rb - connect \xer_so \core_calculate_stage_18_xer_so - connect \divisor_neg \core_calculate_stage_18_divisor_neg - connect \dividend_neg \core_calculate_stage_18_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_18_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_18_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_18_div_by_zero - connect \divisor_radicand \core_calculate_stage_18_divisor_radicand - connect \operation \core_calculate_stage_18_operation - connect \quotient_root \core_calculate_stage_18_quotient_root - connect \root_times_radicand \core_calculate_stage_18_root_times_radicand - connect \compare_lhs \core_calculate_stage_18_compare_lhs - connect \compare_rhs \core_calculate_stage_18_compare_rhs - connect \muxid$1 \core_calculate_stage_18_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_18_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_18_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_18_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_18_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_18_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_18_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_18_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_18_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_18_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_18_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_18_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_18_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_18_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_18_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_18_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_18_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_18_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_18_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_18_ra$119 - connect \rb$21 \core_calculate_stage_18_rb$120 - connect \xer_so$22 \core_calculate_stage_18_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_18_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_18_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_18_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_18_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_18_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_18_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_18_operation$128 - connect \quotient_root$30 \core_calculate_stage_18_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_18_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_18_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_18_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_19_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute 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"OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_19_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_19_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_19_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_19_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_19_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_19_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_19_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_19_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_19_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_19_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_19_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_19_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_19_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_19_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_19_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_19_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_19_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_19_compare_rhs$165 - cell \core_calculate_stage_19 \core_calculate_stage_19 - connect \muxid \core_calculate_stage_19_muxid - connect \logical_op__insn_type \core_calculate_stage_19_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_19_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_19_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_19_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_19_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_19_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_19_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_19_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_19_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_19_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_19_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_19_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_19_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_19_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_19_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_19_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_19_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_19_logical_op__insn - connect \ra \core_calculate_stage_19_ra - connect \rb \core_calculate_stage_19_rb - connect \xer_so \core_calculate_stage_19_xer_so - connect \divisor_neg \core_calculate_stage_19_divisor_neg - connect \dividend_neg \core_calculate_stage_19_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_19_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_19_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_19_div_by_zero - connect \divisor_radicand \core_calculate_stage_19_divisor_radicand - connect \operation \core_calculate_stage_19_operation - connect \quotient_root \core_calculate_stage_19_quotient_root - connect \root_times_radicand \core_calculate_stage_19_root_times_radicand - connect \compare_lhs \core_calculate_stage_19_compare_lhs - connect \compare_rhs \core_calculate_stage_19_compare_rhs - connect \muxid$1 \core_calculate_stage_19_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_19_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_19_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_19_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_19_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_19_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_19_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_19_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_19_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_19_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_19_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_19_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_19_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_19_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_19_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_19_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_19_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_19_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_19_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_19_ra$152 - connect \rb$21 \core_calculate_stage_19_rb$153 - connect \xer_so$22 \core_calculate_stage_19_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_19_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_19_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_19_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_19_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_19_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_19_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_19_operation$161 - connect \quotient_root$30 \core_calculate_stage_19_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_19_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_19_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_19_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_16_muxid 2'00 - assign \core_calculate_stage_16_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_16_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_16_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_16_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_16_logical_op__rc__rc 1'0 - assign \core_calculate_stage_16_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_16_logical_op__oe__oe 1'0 - assign \core_calculate_stage_16_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_16_logical_op__invert_in 1'0 - assign \core_calculate_stage_16_logical_op__zero_a 1'0 - assign \core_calculate_stage_16_logical_op__input_carry 2'00 - assign \core_calculate_stage_16_logical_op__invert_out 1'0 - assign \core_calculate_stage_16_logical_op__write_cr0 1'0 - assign \core_calculate_stage_16_logical_op__output_carry 1'0 - assign \core_calculate_stage_16_logical_op__is_32bit 1'0 - assign \core_calculate_stage_16_logical_op__is_signed 1'0 - assign \core_calculate_stage_16_logical_op__data_len 4'0000 - assign \core_calculate_stage_16_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_16_logical_op__insn \core_calculate_stage_16_logical_op__data_len \core_calculate_stage_16_logical_op__is_signed \core_calculate_stage_16_logical_op__is_32bit \core_calculate_stage_16_logical_op__output_carry \core_calculate_stage_16_logical_op__write_cr0 \core_calculate_stage_16_logical_op__invert_out \core_calculate_stage_16_logical_op__input_carry \core_calculate_stage_16_logical_op__zero_a \core_calculate_stage_16_logical_op__invert_in { \core_calculate_stage_16_logical_op__oe__oe_ok \core_calculate_stage_16_logical_op__oe__oe } { \core_calculate_stage_16_logical_op__rc__rc_ok \core_calculate_stage_16_logical_op__rc__rc } { \core_calculate_stage_16_logical_op__imm_data__imm_ok \core_calculate_stage_16_logical_op__imm_data__imm } \core_calculate_stage_16_logical_op__fn_unit \core_calculate_stage_16_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_16_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_16_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_16_xer_so 1'0 - assign \core_calculate_stage_16_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_16_divisor_neg 1'0 - assign \core_calculate_stage_16_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_16_dividend_neg 1'0 - assign \core_calculate_stage_16_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_16_dive_abs_ov32 1'0 - assign \core_calculate_stage_16_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_16_dive_abs_ov64 1'0 - assign \core_calculate_stage_16_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_16_div_by_zero 1'0 - assign \core_calculate_stage_16_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_16_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_16_operation 2'00 - assign \core_calculate_stage_16_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_16_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_16_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_16_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_16_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_16_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_17_muxid 2'00 - assign \core_calculate_stage_17_muxid \core_calculate_stage_16_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_17_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_17_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_17_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_17_logical_op__rc__rc 1'0 - assign \core_calculate_stage_17_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_17_logical_op__oe__oe 1'0 - assign \core_calculate_stage_17_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_17_logical_op__invert_in 1'0 - assign \core_calculate_stage_17_logical_op__zero_a 1'0 - assign \core_calculate_stage_17_logical_op__input_carry 2'00 - assign \core_calculate_stage_17_logical_op__invert_out 1'0 - assign \core_calculate_stage_17_logical_op__write_cr0 1'0 - assign \core_calculate_stage_17_logical_op__output_carry 1'0 - assign \core_calculate_stage_17_logical_op__is_32bit 1'0 - assign \core_calculate_stage_17_logical_op__is_signed 1'0 - assign \core_calculate_stage_17_logical_op__data_len 4'0000 - assign \core_calculate_stage_17_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_17_logical_op__insn \core_calculate_stage_17_logical_op__data_len \core_calculate_stage_17_logical_op__is_signed \core_calculate_stage_17_logical_op__is_32bit \core_calculate_stage_17_logical_op__output_carry \core_calculate_stage_17_logical_op__write_cr0 \core_calculate_stage_17_logical_op__invert_out \core_calculate_stage_17_logical_op__input_carry \core_calculate_stage_17_logical_op__zero_a \core_calculate_stage_17_logical_op__invert_in { \core_calculate_stage_17_logical_op__oe__oe_ok \core_calculate_stage_17_logical_op__oe__oe } { \core_calculate_stage_17_logical_op__rc__rc_ok \core_calculate_stage_17_logical_op__rc__rc } { \core_calculate_stage_17_logical_op__imm_data__imm_ok \core_calculate_stage_17_logical_op__imm_data__imm } \core_calculate_stage_17_logical_op__fn_unit \core_calculate_stage_17_logical_op__insn_type } { \core_calculate_stage_16_logical_op__insn$52 \core_calculate_stage_16_logical_op__data_len$51 \core_calculate_stage_16_logical_op__is_signed$50 \core_calculate_stage_16_logical_op__is_32bit$49 \core_calculate_stage_16_logical_op__output_carry$48 \core_calculate_stage_16_logical_op__write_cr0$47 \core_calculate_stage_16_logical_op__invert_out$46 \core_calculate_stage_16_logical_op__input_carry$45 \core_calculate_stage_16_logical_op__zero_a$44 \core_calculate_stage_16_logical_op__invert_in$43 { \core_calculate_stage_16_logical_op__oe__oe_ok$42 \core_calculate_stage_16_logical_op__oe__oe$41 } { \core_calculate_stage_16_logical_op__rc__rc_ok$40 \core_calculate_stage_16_logical_op__rc__rc$39 } { \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 \core_calculate_stage_16_logical_op__imm_data__imm$37 } \core_calculate_stage_16_logical_op__fn_unit$36 \core_calculate_stage_16_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_17_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_ra \core_calculate_stage_16_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_17_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_rb \core_calculate_stage_16_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_17_xer_so 1'0 - assign \core_calculate_stage_17_xer_so \core_calculate_stage_16_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_17_divisor_neg 1'0 - assign \core_calculate_stage_17_divisor_neg \core_calculate_stage_16_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_17_dividend_neg 1'0 - assign \core_calculate_stage_17_dividend_neg \core_calculate_stage_16_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_17_dive_abs_ov32 1'0 - assign \core_calculate_stage_17_dive_abs_ov32 \core_calculate_stage_16_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_17_dive_abs_ov64 1'0 - assign \core_calculate_stage_17_dive_abs_ov64 \core_calculate_stage_16_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_17_div_by_zero 1'0 - assign \core_calculate_stage_17_div_by_zero \core_calculate_stage_16_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_17_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_divisor_radicand \core_calculate_stage_16_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_17_operation 2'00 - assign \core_calculate_stage_17_operation \core_calculate_stage_16_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_17_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_quotient_root \core_calculate_stage_16_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_17_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_root_times_radicand \core_calculate_stage_16_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_17_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_compare_lhs \core_calculate_stage_16_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_17_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_17_compare_rhs \core_calculate_stage_16_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_18_muxid 2'00 - assign \core_calculate_stage_18_muxid \core_calculate_stage_17_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_18_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_18_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_18_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_18_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_18_logical_op__rc__rc 1'0 - assign \core_calculate_stage_18_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_18_logical_op__oe__oe 1'0 - assign \core_calculate_stage_18_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_18_logical_op__invert_in 1'0 - assign \core_calculate_stage_18_logical_op__zero_a 1'0 - assign \core_calculate_stage_18_logical_op__input_carry 2'00 - assign \core_calculate_stage_18_logical_op__invert_out 1'0 - assign \core_calculate_stage_18_logical_op__write_cr0 1'0 - assign \core_calculate_stage_18_logical_op__output_carry 1'0 - assign \core_calculate_stage_18_logical_op__is_32bit 1'0 - assign \core_calculate_stage_18_logical_op__is_signed 1'0 - assign \core_calculate_stage_18_logical_op__data_len 4'0000 - assign \core_calculate_stage_18_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_18_logical_op__insn \core_calculate_stage_18_logical_op__data_len \core_calculate_stage_18_logical_op__is_signed \core_calculate_stage_18_logical_op__is_32bit \core_calculate_stage_18_logical_op__output_carry \core_calculate_stage_18_logical_op__write_cr0 \core_calculate_stage_18_logical_op__invert_out \core_calculate_stage_18_logical_op__input_carry \core_calculate_stage_18_logical_op__zero_a \core_calculate_stage_18_logical_op__invert_in { \core_calculate_stage_18_logical_op__oe__oe_ok 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\logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_19_logical_op__insn$151 \core_calculate_stage_19_logical_op__data_len$150 \core_calculate_stage_19_logical_op__is_signed$149 \core_calculate_stage_19_logical_op__is_32bit$148 \core_calculate_stage_19_logical_op__output_carry$147 \core_calculate_stage_19_logical_op__write_cr0$146 \core_calculate_stage_19_logical_op__invert_out$145 \core_calculate_stage_19_logical_op__input_carry$144 \core_calculate_stage_19_logical_op__zero_a$143 \core_calculate_stage_19_logical_op__invert_in$142 { \core_calculate_stage_19_logical_op__oe__oe_ok$141 \core_calculate_stage_19_logical_op__oe__oe$140 } { \core_calculate_stage_19_logical_op__rc__rc_ok$139 \core_calculate_stage_19_logical_op__rc__rc$138 } { \core_calculate_stage_19_logical_op__imm_data__imm_ok$137 \core_calculate_stage_19_logical_op__imm_data__imm$136 } \core_calculate_stage_19_logical_op__fn_unit$135 \core_calculate_stage_19_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_19_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_19_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_19_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_19_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_19_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_19_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_19_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_19_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_19_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_19_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_19_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_19_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_19_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_19_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.p" -module \p$164 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.n" -module \n$165 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.trial0" -module \trial0$167 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.trial1" -module \trial1$168 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.pe" -module \pe$169 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core" -module \core$166 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$167 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$168 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$169 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$166 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.trial0" -module \trial0$171 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.trial1" -module \trial1$172 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.pe" -module \pe$173 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core" -module \core$170 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$171 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$172 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$173 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$170 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.trial0" -module \trial0$175 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.trial1" -module \trial1$176 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.pe" -module \pe$177 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core" -module \core$174 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$175 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$176 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$177 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute 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\enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$174 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.trial0" -module \trial0$179 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.trial1" -module \trial1$180 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1101000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.pe" -module \pe$181 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core" -module \core$178 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$179 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$180 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$181 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$164 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$165 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_20_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_20_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_20_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_20_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_20_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_20_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_20_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_20_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_20_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_20_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_20_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_20_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_20_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_20_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_20_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_20_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_20_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_20_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_20_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_20_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_20_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_20_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_20_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_20_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_20_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_20_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_20_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_20_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_20_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_20_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_20_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_20_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_20_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_20_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_20_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_20_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_20_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_20_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_20_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_20_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_20_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_20_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_20_compare_rhs$66 - cell \core_calculate_stage_20 \core_calculate_stage_20 - connect \muxid \core_calculate_stage_20_muxid - connect \logical_op__insn_type \core_calculate_stage_20_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_20_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_20_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_20_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_20_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_20_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_20_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_20_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_20_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_20_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_20_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_20_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_20_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_20_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_20_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_20_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_20_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_20_logical_op__insn - connect \ra \core_calculate_stage_20_ra - connect \rb \core_calculate_stage_20_rb - connect \xer_so \core_calculate_stage_20_xer_so - connect \divisor_neg \core_calculate_stage_20_divisor_neg - connect \dividend_neg \core_calculate_stage_20_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_20_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_20_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_20_div_by_zero - connect \divisor_radicand \core_calculate_stage_20_divisor_radicand - connect \operation \core_calculate_stage_20_operation - connect \quotient_root \core_calculate_stage_20_quotient_root - connect \root_times_radicand \core_calculate_stage_20_root_times_radicand - connect \compare_lhs \core_calculate_stage_20_compare_lhs - connect \compare_rhs \core_calculate_stage_20_compare_rhs - connect \muxid$1 \core_calculate_stage_20_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_20_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_20_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_20_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_20_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_20_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_20_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_20_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_20_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_20_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_20_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_20_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_20_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_20_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_20_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_20_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_20_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_20_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_20_ra$53 - connect \rb$21 \core_calculate_stage_20_rb$54 - connect \xer_so$22 \core_calculate_stage_20_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_20_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_20_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_20_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_20_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_20_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_20_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_20_operation$62 - connect \quotient_root$30 \core_calculate_stage_20_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_20_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_20_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_20_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_21_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_21_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_21_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_21_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_21_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_21_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_21_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_21_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_21_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_21_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_21_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_21_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_21_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_21_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_21_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_21_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_21_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_21_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_21_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_21_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_21_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_21_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_21_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_21_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_21_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_21_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_21_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_21_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_21_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_21_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_21_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_21_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_21_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_21_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_21_compare_rhs$99 - cell \core_calculate_stage_21 \core_calculate_stage_21 - connect \muxid \core_calculate_stage_21_muxid - connect \logical_op__insn_type \core_calculate_stage_21_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_21_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_21_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_21_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_21_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_21_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_21_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_21_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_21_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_21_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_21_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_21_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_21_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_21_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_21_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_21_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_21_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_21_logical_op__insn - connect \ra \core_calculate_stage_21_ra - connect \rb \core_calculate_stage_21_rb - connect \xer_so \core_calculate_stage_21_xer_so - connect \divisor_neg \core_calculate_stage_21_divisor_neg - connect \dividend_neg \core_calculate_stage_21_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_21_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_21_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_21_div_by_zero - connect \divisor_radicand \core_calculate_stage_21_divisor_radicand - connect \operation \core_calculate_stage_21_operation - connect \quotient_root \core_calculate_stage_21_quotient_root - connect \root_times_radicand \core_calculate_stage_21_root_times_radicand - connect \compare_lhs \core_calculate_stage_21_compare_lhs - connect \compare_rhs \core_calculate_stage_21_compare_rhs - connect \muxid$1 \core_calculate_stage_21_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_21_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_21_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_21_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_21_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_21_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_21_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_21_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_21_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_21_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_21_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_21_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_21_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_21_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_21_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_21_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_21_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_21_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_21_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_21_ra$86 - connect \rb$21 \core_calculate_stage_21_rb$87 - connect \xer_so$22 \core_calculate_stage_21_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_21_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_21_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_21_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_21_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_21_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_21_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_21_operation$95 - connect \quotient_root$30 \core_calculate_stage_21_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_21_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_21_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_21_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_22_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_22_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_22_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_22_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_22_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_22_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_22_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_22_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_22_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_22_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_22_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_22_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_22_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_22_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_22_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_22_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_22_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_22_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_22_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_22_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_22_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_22_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_22_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_22_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_22_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_22_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_22_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_22_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_22_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_22_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_22_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_22_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_22_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_22_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_22_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_22_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_22_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_22_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_22_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_22_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_22_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_22_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_22_compare_rhs$132 - cell \core_calculate_stage_22 \core_calculate_stage_22 - connect \muxid \core_calculate_stage_22_muxid - connect \logical_op__insn_type \core_calculate_stage_22_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_22_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_22_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_22_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_22_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_22_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_22_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_22_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_22_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_22_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_22_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_22_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_22_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_22_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_22_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_22_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_22_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_22_logical_op__insn - connect \ra \core_calculate_stage_22_ra - connect \rb \core_calculate_stage_22_rb - connect \xer_so \core_calculate_stage_22_xer_so - connect \divisor_neg \core_calculate_stage_22_divisor_neg - connect \dividend_neg \core_calculate_stage_22_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_22_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_22_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_22_div_by_zero - connect \divisor_radicand \core_calculate_stage_22_divisor_radicand - connect \operation \core_calculate_stage_22_operation - connect \quotient_root \core_calculate_stage_22_quotient_root - connect \root_times_radicand \core_calculate_stage_22_root_times_radicand - connect \compare_lhs \core_calculate_stage_22_compare_lhs - connect \compare_rhs \core_calculate_stage_22_compare_rhs - connect \muxid$1 \core_calculate_stage_22_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_22_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_22_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_22_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_22_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_22_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_22_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_22_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_22_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_22_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_22_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_22_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_22_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_22_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_22_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_22_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_22_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_22_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_22_ra$119 - connect \rb$21 \core_calculate_stage_22_rb$120 - connect \xer_so$22 \core_calculate_stage_22_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_22_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_22_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_22_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_22_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_22_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_22_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_22_operation$128 - connect \quotient_root$30 \core_calculate_stage_22_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_22_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_22_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_22_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_23_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_23_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_23_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_23_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__zero_a - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_23_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_23_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_23_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_23_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_23_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_23_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_23_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_23_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_23_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_23_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_23_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_23_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_23_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_23_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_23_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_23_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_23_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_23_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_23_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_23_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_23_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_23_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_23_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_23_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_23_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_23_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_23_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_23_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_23_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_23_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_23_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_23_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_23_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_23_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_23_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_23_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_23_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_23_compare_rhs$165 - cell \core_calculate_stage_23 \core_calculate_stage_23 - connect \muxid \core_calculate_stage_23_muxid - connect \logical_op__insn_type \core_calculate_stage_23_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_23_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_23_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_23_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_23_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_23_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_23_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_23_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_23_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_23_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_23_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_23_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_23_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_23_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_23_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_23_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_23_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_23_logical_op__insn - connect \ra \core_calculate_stage_23_ra - connect \rb \core_calculate_stage_23_rb - connect \xer_so \core_calculate_stage_23_xer_so - connect \divisor_neg \core_calculate_stage_23_divisor_neg - connect \dividend_neg \core_calculate_stage_23_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_23_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_23_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_23_div_by_zero - connect \divisor_radicand \core_calculate_stage_23_divisor_radicand - connect \operation \core_calculate_stage_23_operation - connect \quotient_root \core_calculate_stage_23_quotient_root - connect \root_times_radicand \core_calculate_stage_23_root_times_radicand - connect \compare_lhs \core_calculate_stage_23_compare_lhs - connect \compare_rhs \core_calculate_stage_23_compare_rhs - connect \muxid$1 \core_calculate_stage_23_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_23_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_23_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_23_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_23_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_23_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_23_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_23_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_23_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_23_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_23_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_23_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_23_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_23_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_23_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_23_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_23_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_23_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_23_ra$152 - connect \rb$21 \core_calculate_stage_23_rb$153 - connect \xer_so$22 \core_calculate_stage_23_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_23_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_23_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_23_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_23_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_23_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_23_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_23_operation$161 - connect \quotient_root$30 \core_calculate_stage_23_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_23_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_23_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_23_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_20_muxid 2'00 - assign \core_calculate_stage_20_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_20_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_20_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_20_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_20_logical_op__rc__rc 1'0 - assign \core_calculate_stage_20_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_20_logical_op__oe__oe 1'0 - assign \core_calculate_stage_20_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_20_logical_op__invert_in 1'0 - assign \core_calculate_stage_20_logical_op__zero_a 1'0 - assign \core_calculate_stage_20_logical_op__input_carry 2'00 - assign \core_calculate_stage_20_logical_op__invert_out 1'0 - assign \core_calculate_stage_20_logical_op__write_cr0 1'0 - assign \core_calculate_stage_20_logical_op__output_carry 1'0 - assign \core_calculate_stage_20_logical_op__is_32bit 1'0 - assign \core_calculate_stage_20_logical_op__is_signed 1'0 - assign \core_calculate_stage_20_logical_op__data_len 4'0000 - assign \core_calculate_stage_20_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_20_logical_op__insn \core_calculate_stage_20_logical_op__data_len \core_calculate_stage_20_logical_op__is_signed \core_calculate_stage_20_logical_op__is_32bit \core_calculate_stage_20_logical_op__output_carry \core_calculate_stage_20_logical_op__write_cr0 \core_calculate_stage_20_logical_op__invert_out \core_calculate_stage_20_logical_op__input_carry \core_calculate_stage_20_logical_op__zero_a \core_calculate_stage_20_logical_op__invert_in { \core_calculate_stage_20_logical_op__oe__oe_ok \core_calculate_stage_20_logical_op__oe__oe } { \core_calculate_stage_20_logical_op__rc__rc_ok \core_calculate_stage_20_logical_op__rc__rc } { \core_calculate_stage_20_logical_op__imm_data__imm_ok \core_calculate_stage_20_logical_op__imm_data__imm } \core_calculate_stage_20_logical_op__fn_unit \core_calculate_stage_20_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_20_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_20_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_20_xer_so 1'0 - assign \core_calculate_stage_20_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_20_divisor_neg 1'0 - assign \core_calculate_stage_20_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_20_dividend_neg 1'0 - assign \core_calculate_stage_20_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_20_dive_abs_ov32 1'0 - assign \core_calculate_stage_20_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_20_dive_abs_ov64 1'0 - assign \core_calculate_stage_20_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_20_div_by_zero 1'0 - assign \core_calculate_stage_20_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_20_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_20_operation 2'00 - assign \core_calculate_stage_20_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_20_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_20_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_20_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_20_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_20_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_21_muxid 2'00 - assign \core_calculate_stage_21_muxid \core_calculate_stage_20_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_21_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_21_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_21_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_21_logical_op__rc__rc 1'0 - assign \core_calculate_stage_21_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_21_logical_op__oe__oe 1'0 - assign \core_calculate_stage_21_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_21_logical_op__invert_in 1'0 - assign \core_calculate_stage_21_logical_op__zero_a 1'0 - assign \core_calculate_stage_21_logical_op__input_carry 2'00 - assign \core_calculate_stage_21_logical_op__invert_out 1'0 - assign \core_calculate_stage_21_logical_op__write_cr0 1'0 - assign \core_calculate_stage_21_logical_op__output_carry 1'0 - assign \core_calculate_stage_21_logical_op__is_32bit 1'0 - assign \core_calculate_stage_21_logical_op__is_signed 1'0 - assign \core_calculate_stage_21_logical_op__data_len 4'0000 - assign \core_calculate_stage_21_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_21_logical_op__insn \core_calculate_stage_21_logical_op__data_len \core_calculate_stage_21_logical_op__is_signed \core_calculate_stage_21_logical_op__is_32bit \core_calculate_stage_21_logical_op__output_carry \core_calculate_stage_21_logical_op__write_cr0 \core_calculate_stage_21_logical_op__invert_out \core_calculate_stage_21_logical_op__input_carry \core_calculate_stage_21_logical_op__zero_a \core_calculate_stage_21_logical_op__invert_in { \core_calculate_stage_21_logical_op__oe__oe_ok \core_calculate_stage_21_logical_op__oe__oe } { \core_calculate_stage_21_logical_op__rc__rc_ok \core_calculate_stage_21_logical_op__rc__rc } { \core_calculate_stage_21_logical_op__imm_data__imm_ok \core_calculate_stage_21_logical_op__imm_data__imm } \core_calculate_stage_21_logical_op__fn_unit \core_calculate_stage_21_logical_op__insn_type } { \core_calculate_stage_20_logical_op__insn$52 \core_calculate_stage_20_logical_op__data_len$51 \core_calculate_stage_20_logical_op__is_signed$50 \core_calculate_stage_20_logical_op__is_32bit$49 \core_calculate_stage_20_logical_op__output_carry$48 \core_calculate_stage_20_logical_op__write_cr0$47 \core_calculate_stage_20_logical_op__invert_out$46 \core_calculate_stage_20_logical_op__input_carry$45 \core_calculate_stage_20_logical_op__zero_a$44 \core_calculate_stage_20_logical_op__invert_in$43 { \core_calculate_stage_20_logical_op__oe__oe_ok$42 \core_calculate_stage_20_logical_op__oe__oe$41 } { \core_calculate_stage_20_logical_op__rc__rc_ok$40 \core_calculate_stage_20_logical_op__rc__rc$39 } { \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 \core_calculate_stage_20_logical_op__imm_data__imm$37 } \core_calculate_stage_20_logical_op__fn_unit$36 \core_calculate_stage_20_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_21_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_ra \core_calculate_stage_20_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_21_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_rb \core_calculate_stage_20_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_21_xer_so 1'0 - assign \core_calculate_stage_21_xer_so \core_calculate_stage_20_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_21_divisor_neg 1'0 - assign \core_calculate_stage_21_divisor_neg \core_calculate_stage_20_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_21_dividend_neg 1'0 - assign \core_calculate_stage_21_dividend_neg \core_calculate_stage_20_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_21_dive_abs_ov32 1'0 - assign \core_calculate_stage_21_dive_abs_ov32 \core_calculate_stage_20_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_21_dive_abs_ov64 1'0 - assign \core_calculate_stage_21_dive_abs_ov64 \core_calculate_stage_20_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_21_div_by_zero 1'0 - assign \core_calculate_stage_21_div_by_zero \core_calculate_stage_20_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_21_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_divisor_radicand \core_calculate_stage_20_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_21_operation 2'00 - assign \core_calculate_stage_21_operation \core_calculate_stage_20_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_21_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_quotient_root \core_calculate_stage_20_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_21_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_root_times_radicand \core_calculate_stage_20_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_21_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_compare_lhs \core_calculate_stage_20_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_21_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_21_compare_rhs \core_calculate_stage_20_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_22_muxid 2'00 - assign \core_calculate_stage_22_muxid \core_calculate_stage_21_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_22_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_22_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_22_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_22_logical_op__rc__rc 1'0 - assign \core_calculate_stage_22_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_22_logical_op__oe__oe 1'0 - assign \core_calculate_stage_22_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_22_logical_op__invert_in 1'0 - assign \core_calculate_stage_22_logical_op__zero_a 1'0 - assign \core_calculate_stage_22_logical_op__input_carry 2'00 - assign \core_calculate_stage_22_logical_op__invert_out 1'0 - assign \core_calculate_stage_22_logical_op__write_cr0 1'0 - assign \core_calculate_stage_22_logical_op__output_carry 1'0 - assign \core_calculate_stage_22_logical_op__is_32bit 1'0 - assign \core_calculate_stage_22_logical_op__is_signed 1'0 - assign \core_calculate_stage_22_logical_op__data_len 4'0000 - assign \core_calculate_stage_22_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_22_logical_op__insn \core_calculate_stage_22_logical_op__data_len \core_calculate_stage_22_logical_op__is_signed \core_calculate_stage_22_logical_op__is_32bit \core_calculate_stage_22_logical_op__output_carry \core_calculate_stage_22_logical_op__write_cr0 \core_calculate_stage_22_logical_op__invert_out \core_calculate_stage_22_logical_op__input_carry \core_calculate_stage_22_logical_op__zero_a \core_calculate_stage_22_logical_op__invert_in { \core_calculate_stage_22_logical_op__oe__oe_ok \core_calculate_stage_22_logical_op__oe__oe } { \core_calculate_stage_22_logical_op__rc__rc_ok \core_calculate_stage_22_logical_op__rc__rc } { \core_calculate_stage_22_logical_op__imm_data__imm_ok \core_calculate_stage_22_logical_op__imm_data__imm } \core_calculate_stage_22_logical_op__fn_unit \core_calculate_stage_22_logical_op__insn_type } { \core_calculate_stage_21_logical_op__insn$85 \core_calculate_stage_21_logical_op__data_len$84 \core_calculate_stage_21_logical_op__is_signed$83 \core_calculate_stage_21_logical_op__is_32bit$82 \core_calculate_stage_21_logical_op__output_carry$81 \core_calculate_stage_21_logical_op__write_cr0$80 \core_calculate_stage_21_logical_op__invert_out$79 \core_calculate_stage_21_logical_op__input_carry$78 \core_calculate_stage_21_logical_op__zero_a$77 \core_calculate_stage_21_logical_op__invert_in$76 { \core_calculate_stage_21_logical_op__oe__oe_ok$75 \core_calculate_stage_21_logical_op__oe__oe$74 } { \core_calculate_stage_21_logical_op__rc__rc_ok$73 \core_calculate_stage_21_logical_op__rc__rc$72 } { \core_calculate_stage_21_logical_op__imm_data__imm_ok$71 \core_calculate_stage_21_logical_op__imm_data__imm$70 } \core_calculate_stage_21_logical_op__fn_unit$69 \core_calculate_stage_21_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_22_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_ra \core_calculate_stage_21_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_22_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_rb \core_calculate_stage_21_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_22_xer_so 1'0 - assign \core_calculate_stage_22_xer_so \core_calculate_stage_21_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_22_divisor_neg 1'0 - assign \core_calculate_stage_22_divisor_neg \core_calculate_stage_21_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_22_dividend_neg 1'0 - assign \core_calculate_stage_22_dividend_neg \core_calculate_stage_21_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_22_dive_abs_ov32 1'0 - assign \core_calculate_stage_22_dive_abs_ov32 \core_calculate_stage_21_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_22_dive_abs_ov64 1'0 - assign \core_calculate_stage_22_dive_abs_ov64 \core_calculate_stage_21_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_22_div_by_zero 1'0 - assign \core_calculate_stage_22_div_by_zero \core_calculate_stage_21_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_22_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_divisor_radicand \core_calculate_stage_21_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_22_operation 2'00 - assign \core_calculate_stage_22_operation \core_calculate_stage_21_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_22_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_quotient_root \core_calculate_stage_21_quotient_root$96 - sync init - end - process $group_96 - assign \core_calculate_stage_22_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_root_times_radicand \core_calculate_stage_21_root_times_radicand$97 - sync init - end - process $group_97 - assign \core_calculate_stage_22_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_compare_lhs \core_calculate_stage_21_compare_lhs$98 - sync init - end - process $group_98 - assign \core_calculate_stage_22_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_22_compare_rhs \core_calculate_stage_21_compare_rhs$99 - sync init - end - process $group_99 - assign \core_calculate_stage_23_muxid 2'00 - assign \core_calculate_stage_23_muxid \core_calculate_stage_22_muxid$100 - sync init - end - process $group_100 - assign \core_calculate_stage_23_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_23_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_23_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_23_logical_op__rc__rc 1'0 - assign \core_calculate_stage_23_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_23_logical_op__oe__oe 1'0 - assign \core_calculate_stage_23_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_23_logical_op__invert_in 1'0 - assign \core_calculate_stage_23_logical_op__zero_a 1'0 - assign \core_calculate_stage_23_logical_op__input_carry 2'00 - assign \core_calculate_stage_23_logical_op__invert_out 1'0 - assign \core_calculate_stage_23_logical_op__write_cr0 1'0 - assign \core_calculate_stage_23_logical_op__output_carry 1'0 - assign \core_calculate_stage_23_logical_op__is_32bit 1'0 - assign \core_calculate_stage_23_logical_op__is_signed 1'0 - assign \core_calculate_stage_23_logical_op__data_len 4'0000 - assign \core_calculate_stage_23_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_23_logical_op__insn \core_calculate_stage_23_logical_op__data_len \core_calculate_stage_23_logical_op__is_signed \core_calculate_stage_23_logical_op__is_32bit \core_calculate_stage_23_logical_op__output_carry \core_calculate_stage_23_logical_op__write_cr0 \core_calculate_stage_23_logical_op__invert_out \core_calculate_stage_23_logical_op__input_carry \core_calculate_stage_23_logical_op__zero_a \core_calculate_stage_23_logical_op__invert_in { \core_calculate_stage_23_logical_op__oe__oe_ok \core_calculate_stage_23_logical_op__oe__oe } { \core_calculate_stage_23_logical_op__rc__rc_ok \core_calculate_stage_23_logical_op__rc__rc } { \core_calculate_stage_23_logical_op__imm_data__imm_ok \core_calculate_stage_23_logical_op__imm_data__imm } \core_calculate_stage_23_logical_op__fn_unit \core_calculate_stage_23_logical_op__insn_type } { \core_calculate_stage_22_logical_op__insn$118 \core_calculate_stage_22_logical_op__data_len$117 \core_calculate_stage_22_logical_op__is_signed$116 \core_calculate_stage_22_logical_op__is_32bit$115 \core_calculate_stage_22_logical_op__output_carry$114 \core_calculate_stage_22_logical_op__write_cr0$113 \core_calculate_stage_22_logical_op__invert_out$112 \core_calculate_stage_22_logical_op__input_carry$111 \core_calculate_stage_22_logical_op__zero_a$110 \core_calculate_stage_22_logical_op__invert_in$109 { \core_calculate_stage_22_logical_op__oe__oe_ok$108 \core_calculate_stage_22_logical_op__oe__oe$107 } { \core_calculate_stage_22_logical_op__rc__rc_ok$106 \core_calculate_stage_22_logical_op__rc__rc$105 } { \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 \core_calculate_stage_22_logical_op__imm_data__imm$103 } \core_calculate_stage_22_logical_op__fn_unit$102 \core_calculate_stage_22_logical_op__insn_type$101 } - sync init - end - process $group_118 - assign \core_calculate_stage_23_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_ra \core_calculate_stage_22_ra$119 - sync init - end - process $group_119 - assign \core_calculate_stage_23_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_rb \core_calculate_stage_22_rb$120 - sync init - end - process $group_120 - assign \core_calculate_stage_23_xer_so 1'0 - assign \core_calculate_stage_23_xer_so \core_calculate_stage_22_xer_so$121 - sync init - end - process $group_121 - assign \core_calculate_stage_23_divisor_neg 1'0 - assign \core_calculate_stage_23_divisor_neg \core_calculate_stage_22_divisor_neg$122 - sync init - end - process $group_122 - assign \core_calculate_stage_23_dividend_neg 1'0 - assign \core_calculate_stage_23_dividend_neg \core_calculate_stage_22_dividend_neg$123 - sync init - end - process $group_123 - assign \core_calculate_stage_23_dive_abs_ov32 1'0 - assign \core_calculate_stage_23_dive_abs_ov32 \core_calculate_stage_22_dive_abs_ov32$124 - sync init - end - process $group_124 - assign \core_calculate_stage_23_dive_abs_ov64 1'0 - assign \core_calculate_stage_23_dive_abs_ov64 \core_calculate_stage_22_dive_abs_ov64$125 - sync init - end - process $group_125 - assign \core_calculate_stage_23_div_by_zero 1'0 - assign \core_calculate_stage_23_div_by_zero \core_calculate_stage_22_div_by_zero$126 - sync init - end - process $group_126 - assign \core_calculate_stage_23_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_divisor_radicand \core_calculate_stage_22_divisor_radicand$127 - sync init - end - process $group_127 - assign \core_calculate_stage_23_operation 2'00 - assign \core_calculate_stage_23_operation \core_calculate_stage_22_operation$128 - sync init - end - process $group_128 - assign \core_calculate_stage_23_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_quotient_root \core_calculate_stage_22_quotient_root$129 - sync init - end - process $group_129 - assign \core_calculate_stage_23_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_root_times_radicand \core_calculate_stage_22_root_times_radicand$130 - sync init - end - process $group_130 - assign \core_calculate_stage_23_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_compare_lhs \core_calculate_stage_22_compare_lhs$131 - sync init - end - process $group_131 - assign \core_calculate_stage_23_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_23_compare_rhs \core_calculate_stage_22_compare_rhs$132 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$166 - process $group_132 - assign \p_valid_i$166 1'0 - assign \p_valid_i$166 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_133 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_23_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_23_logical_op__insn$151 \core_calculate_stage_23_logical_op__data_len$150 \core_calculate_stage_23_logical_op__is_signed$149 \core_calculate_stage_23_logical_op__is_32bit$148 \core_calculate_stage_23_logical_op__output_carry$147 \core_calculate_stage_23_logical_op__write_cr0$146 \core_calculate_stage_23_logical_op__invert_out$145 \core_calculate_stage_23_logical_op__input_carry$144 \core_calculate_stage_23_logical_op__zero_a$143 \core_calculate_stage_23_logical_op__invert_in$142 { \core_calculate_stage_23_logical_op__oe__oe_ok$141 \core_calculate_stage_23_logical_op__oe__oe$140 } { \core_calculate_stage_23_logical_op__rc__rc_ok$139 \core_calculate_stage_23_logical_op__rc__rc$138 } { \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 \core_calculate_stage_23_logical_op__imm_data__imm$136 } \core_calculate_stage_23_logical_op__fn_unit$135 \core_calculate_stage_23_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_23_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_23_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_23_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_23_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_23_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_23_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_23_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_23_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_23_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_23_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_23_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_23_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_23_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_23_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.p" -module \p$182 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.n" -module \n$183 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.trial0" -module \trial0$185 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.trial1" -module \trial1$186 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.pe" -module \pe$187 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core" -module \core$184 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$185 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$186 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$187 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$184 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.trial0" -module \trial0$189 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.trial1" -module \trial1$190 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.pe" -module \pe$191 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core" -module \core$188 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$189 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$190 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$191 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$188 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 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\compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core.trial0" -module \trial0$193 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core.pe" -module \pe$195 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$193 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$194 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$195 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$192 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.trial0" -module \trial0$197 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.trial1" -module \trial1$198 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.pe" -module \pe$199 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core" -module \core$196 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$197 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$198 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$199 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'100100 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27" -module \core_calculate_stage_27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$196 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$182 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$183 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_24_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_24_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_24_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_24_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_24_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_24_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_24_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_24_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_24_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_24_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_24_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_24_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_24_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_24_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_24_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_24_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_24_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_24_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_24_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_24_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_24_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_24_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_24_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_24_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_24_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_24_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_24_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_24_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_24_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_24_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_24_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_24_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_24_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_24_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_24_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_24_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_24_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_24_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_24_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_24_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_24_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_24_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_24_compare_rhs$66 - cell \core_calculate_stage_24 \core_calculate_stage_24 - connect \muxid \core_calculate_stage_24_muxid - connect \logical_op__insn_type \core_calculate_stage_24_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_24_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_24_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_24_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_24_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_24_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_24_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_24_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_24_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_24_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_24_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_24_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_24_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_24_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_24_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_24_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_24_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_24_logical_op__insn - connect \ra \core_calculate_stage_24_ra - connect \rb \core_calculate_stage_24_rb - connect \xer_so \core_calculate_stage_24_xer_so - connect \divisor_neg \core_calculate_stage_24_divisor_neg - connect \dividend_neg \core_calculate_stage_24_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_24_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_24_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_24_div_by_zero - connect \divisor_radicand \core_calculate_stage_24_divisor_radicand - connect \operation \core_calculate_stage_24_operation - connect \quotient_root \core_calculate_stage_24_quotient_root - connect \root_times_radicand \core_calculate_stage_24_root_times_radicand - connect \compare_lhs \core_calculate_stage_24_compare_lhs - connect \compare_rhs \core_calculate_stage_24_compare_rhs - connect \muxid$1 \core_calculate_stage_24_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_24_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_24_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_24_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_24_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_24_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_24_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_24_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_24_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_24_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_24_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_24_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_24_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_24_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_24_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_24_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_24_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_24_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_24_ra$53 - connect \rb$21 \core_calculate_stage_24_rb$54 - connect \xer_so$22 \core_calculate_stage_24_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_24_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_24_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_24_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_24_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_24_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_24_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_24_operation$62 - connect \quotient_root$30 \core_calculate_stage_24_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_24_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_24_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_24_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_25_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_25_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_25_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_25_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_25_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_25_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_25_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_25_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_25_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_25_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_25_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_25_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_25_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_25_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_25_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_25_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_25_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_25_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_25_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_25_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_25_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_25_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_25_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_25_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_25_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_25_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_25_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_25_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_25_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_25_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_25_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_25_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_25_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_25_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_25_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_25_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_25_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_25_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_25_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_25_compare_rhs$99 - cell \core_calculate_stage_25 \core_calculate_stage_25 - connect \muxid \core_calculate_stage_25_muxid - connect \logical_op__insn_type \core_calculate_stage_25_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_25_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_25_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_25_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_25_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_25_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_25_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_25_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_25_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_25_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_25_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_25_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_25_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_25_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_25_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_25_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_25_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_25_logical_op__insn - connect \ra \core_calculate_stage_25_ra - connect \rb \core_calculate_stage_25_rb - connect \xer_so \core_calculate_stage_25_xer_so - connect \divisor_neg \core_calculate_stage_25_divisor_neg - connect \dividend_neg \core_calculate_stage_25_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_25_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_25_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_25_div_by_zero - connect \divisor_radicand \core_calculate_stage_25_divisor_radicand - connect \operation \core_calculate_stage_25_operation - connect \quotient_root \core_calculate_stage_25_quotient_root - connect \root_times_radicand \core_calculate_stage_25_root_times_radicand - connect \compare_lhs \core_calculate_stage_25_compare_lhs - connect \compare_rhs \core_calculate_stage_25_compare_rhs - connect \muxid$1 \core_calculate_stage_25_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_25_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_25_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_25_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_25_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_25_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_25_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_25_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_25_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_25_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_25_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_25_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_25_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_25_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_25_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_25_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_25_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_25_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_25_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_25_ra$86 - connect \rb$21 \core_calculate_stage_25_rb$87 - connect \xer_so$22 \core_calculate_stage_25_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_25_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_25_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_25_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_25_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_25_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_25_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_25_operation$95 - connect \quotient_root$30 \core_calculate_stage_25_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_25_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_25_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_25_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_26_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_26_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_26_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_26_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_26_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_26_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_26_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_26_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_26_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_26_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_26_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_26_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_26_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_26_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_26_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_26_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_26_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_26_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_26_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_26_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_26_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_26_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_26_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_26_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_26_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_26_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_26_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_26_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_26_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_26_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_26_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_26_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_26_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_26_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_26_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_26_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_26_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_26_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_26_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_26_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_26_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_26_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_26_compare_rhs$132 - cell \core_calculate_stage_26 \core_calculate_stage_26 - connect \muxid \core_calculate_stage_26_muxid - connect \logical_op__insn_type \core_calculate_stage_26_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_26_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_26_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_26_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_26_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_26_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_26_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_26_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_26_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_26_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_26_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_26_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_26_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_26_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_26_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_26_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_26_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_26_logical_op__insn - connect \ra \core_calculate_stage_26_ra - connect \rb \core_calculate_stage_26_rb - connect \xer_so \core_calculate_stage_26_xer_so - connect \divisor_neg \core_calculate_stage_26_divisor_neg - connect \dividend_neg \core_calculate_stage_26_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_26_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_26_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_26_div_by_zero - connect \divisor_radicand \core_calculate_stage_26_divisor_radicand - connect \operation \core_calculate_stage_26_operation - connect \quotient_root \core_calculate_stage_26_quotient_root - connect \root_times_radicand \core_calculate_stage_26_root_times_radicand - connect \compare_lhs \core_calculate_stage_26_compare_lhs - connect \compare_rhs \core_calculate_stage_26_compare_rhs - connect \muxid$1 \core_calculate_stage_26_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_26_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_26_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_26_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_26_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_26_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_26_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_26_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_26_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_26_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_26_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_26_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_26_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_26_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_26_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_26_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_26_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_26_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_26_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_26_ra$119 - connect \rb$21 \core_calculate_stage_26_rb$120 - connect \xer_so$22 \core_calculate_stage_26_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_26_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_26_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_26_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_26_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_26_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_26_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_26_operation$128 - connect \quotient_root$30 \core_calculate_stage_26_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_26_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_26_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_26_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_27_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_27_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_27_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_27_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_27_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_27_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_27_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_27_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_27_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_27_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_27_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_27_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_27_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_27_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_27_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_27_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_27_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_27_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_27_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_27_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_27_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_27_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_27_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_27_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_27_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_27_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_27_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_27_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_27_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_27_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_27_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_27_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_27_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_27_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_27_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_27_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_27_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_27_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_27_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_27_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_27_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_27_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_27_compare_rhs$165 - cell \core_calculate_stage_27 \core_calculate_stage_27 - connect \muxid \core_calculate_stage_27_muxid - connect \logical_op__insn_type \core_calculate_stage_27_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_27_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_27_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_27_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_27_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_27_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_27_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_27_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_27_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_27_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_27_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_27_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_27_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_27_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_27_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_27_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_27_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_27_logical_op__insn - connect \ra \core_calculate_stage_27_ra - connect \rb \core_calculate_stage_27_rb - connect \xer_so \core_calculate_stage_27_xer_so - connect \divisor_neg \core_calculate_stage_27_divisor_neg - connect \dividend_neg \core_calculate_stage_27_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_27_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_27_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_27_div_by_zero - connect \divisor_radicand \core_calculate_stage_27_divisor_radicand - connect \operation \core_calculate_stage_27_operation - connect \quotient_root \core_calculate_stage_27_quotient_root - connect \root_times_radicand \core_calculate_stage_27_root_times_radicand - connect \compare_lhs \core_calculate_stage_27_compare_lhs - connect \compare_rhs \core_calculate_stage_27_compare_rhs - connect \muxid$1 \core_calculate_stage_27_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_27_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_27_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_27_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_27_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_27_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_27_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_27_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_27_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_27_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_27_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_27_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_27_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_27_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_27_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_27_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_27_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_27_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_27_ra$152 - connect \rb$21 \core_calculate_stage_27_rb$153 - connect \xer_so$22 \core_calculate_stage_27_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_27_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_27_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_27_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_27_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_27_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_27_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_27_operation$161 - connect \quotient_root$30 \core_calculate_stage_27_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_27_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_27_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_27_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_24_muxid 2'00 - assign \core_calculate_stage_24_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_24_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_24_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_24_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_24_logical_op__rc__rc 1'0 - assign \core_calculate_stage_24_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_24_logical_op__oe__oe 1'0 - assign \core_calculate_stage_24_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_24_logical_op__invert_in 1'0 - assign \core_calculate_stage_24_logical_op__zero_a 1'0 - assign \core_calculate_stage_24_logical_op__input_carry 2'00 - assign \core_calculate_stage_24_logical_op__invert_out 1'0 - assign \core_calculate_stage_24_logical_op__write_cr0 1'0 - assign \core_calculate_stage_24_logical_op__output_carry 1'0 - assign \core_calculate_stage_24_logical_op__is_32bit 1'0 - assign \core_calculate_stage_24_logical_op__is_signed 1'0 - assign \core_calculate_stage_24_logical_op__data_len 4'0000 - assign \core_calculate_stage_24_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_24_logical_op__insn \core_calculate_stage_24_logical_op__data_len \core_calculate_stage_24_logical_op__is_signed \core_calculate_stage_24_logical_op__is_32bit \core_calculate_stage_24_logical_op__output_carry \core_calculate_stage_24_logical_op__write_cr0 \core_calculate_stage_24_logical_op__invert_out \core_calculate_stage_24_logical_op__input_carry \core_calculate_stage_24_logical_op__zero_a \core_calculate_stage_24_logical_op__invert_in { \core_calculate_stage_24_logical_op__oe__oe_ok \core_calculate_stage_24_logical_op__oe__oe } { \core_calculate_stage_24_logical_op__rc__rc_ok \core_calculate_stage_24_logical_op__rc__rc } { \core_calculate_stage_24_logical_op__imm_data__imm_ok \core_calculate_stage_24_logical_op__imm_data__imm } \core_calculate_stage_24_logical_op__fn_unit \core_calculate_stage_24_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_24_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_24_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_24_xer_so 1'0 - assign \core_calculate_stage_24_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_24_divisor_neg 1'0 - assign \core_calculate_stage_24_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_24_dividend_neg 1'0 - assign \core_calculate_stage_24_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_24_dive_abs_ov32 1'0 - assign \core_calculate_stage_24_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_24_dive_abs_ov64 1'0 - assign \core_calculate_stage_24_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_24_div_by_zero 1'0 - assign \core_calculate_stage_24_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_24_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_24_operation 2'00 - assign \core_calculate_stage_24_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_24_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_24_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_24_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_24_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_24_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_25_muxid 2'00 - assign \core_calculate_stage_25_muxid \core_calculate_stage_24_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_25_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_25_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_25_logical_op__imm_data__imm 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- assign { \core_calculate_stage_25_logical_op__insn \core_calculate_stage_25_logical_op__data_len \core_calculate_stage_25_logical_op__is_signed \core_calculate_stage_25_logical_op__is_32bit \core_calculate_stage_25_logical_op__output_carry \core_calculate_stage_25_logical_op__write_cr0 \core_calculate_stage_25_logical_op__invert_out \core_calculate_stage_25_logical_op__input_carry \core_calculate_stage_25_logical_op__zero_a \core_calculate_stage_25_logical_op__invert_in { \core_calculate_stage_25_logical_op__oe__oe_ok \core_calculate_stage_25_logical_op__oe__oe } { \core_calculate_stage_25_logical_op__rc__rc_ok \core_calculate_stage_25_logical_op__rc__rc } { \core_calculate_stage_25_logical_op__imm_data__imm_ok \core_calculate_stage_25_logical_op__imm_data__imm } \core_calculate_stage_25_logical_op__fn_unit \core_calculate_stage_25_logical_op__insn_type } { \core_calculate_stage_24_logical_op__insn$52 \core_calculate_stage_24_logical_op__data_len$51 \core_calculate_stage_24_logical_op__is_signed$50 \core_calculate_stage_24_logical_op__is_32bit$49 \core_calculate_stage_24_logical_op__output_carry$48 \core_calculate_stage_24_logical_op__write_cr0$47 \core_calculate_stage_24_logical_op__invert_out$46 \core_calculate_stage_24_logical_op__input_carry$45 \core_calculate_stage_24_logical_op__zero_a$44 \core_calculate_stage_24_logical_op__invert_in$43 { \core_calculate_stage_24_logical_op__oe__oe_ok$42 \core_calculate_stage_24_logical_op__oe__oe$41 } { \core_calculate_stage_24_logical_op__rc__rc_ok$40 \core_calculate_stage_24_logical_op__rc__rc$39 } { \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 \core_calculate_stage_24_logical_op__imm_data__imm$37 } \core_calculate_stage_24_logical_op__fn_unit$36 \core_calculate_stage_24_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_25_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_25_ra \core_calculate_stage_24_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_25_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_25_rb \core_calculate_stage_24_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_25_xer_so 1'0 - assign \core_calculate_stage_25_xer_so \core_calculate_stage_24_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_25_divisor_neg 1'0 - assign \core_calculate_stage_25_divisor_neg \core_calculate_stage_24_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_25_dividend_neg 1'0 - assign \core_calculate_stage_25_dividend_neg \core_calculate_stage_24_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_25_dive_abs_ov32 1'0 - assign \core_calculate_stage_25_dive_abs_ov32 \core_calculate_stage_24_dive_abs_ov32$58 - sync init - end - process $group_58 - assign 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\core_calculate_stage_24_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_26_muxid 2'00 - assign \core_calculate_stage_26_muxid \core_calculate_stage_25_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_26_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_26_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_26_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_26_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_26_logical_op__rc__rc 1'0 - assign \core_calculate_stage_26_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_26_logical_op__oe__oe 1'0 - assign \core_calculate_stage_26_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_26_logical_op__invert_in 1'0 - assign \core_calculate_stage_26_logical_op__zero_a 1'0 - assign \core_calculate_stage_26_logical_op__input_carry 2'00 - assign \core_calculate_stage_26_logical_op__invert_out 1'0 - assign \core_calculate_stage_26_logical_op__write_cr0 1'0 - assign \core_calculate_stage_26_logical_op__output_carry 1'0 - assign \core_calculate_stage_26_logical_op__is_32bit 1'0 - assign \core_calculate_stage_26_logical_op__is_signed 1'0 - assign \core_calculate_stage_26_logical_op__data_len 4'0000 - assign \core_calculate_stage_26_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_26_logical_op__insn \core_calculate_stage_26_logical_op__data_len \core_calculate_stage_26_logical_op__is_signed \core_calculate_stage_26_logical_op__is_32bit \core_calculate_stage_26_logical_op__output_carry \core_calculate_stage_26_logical_op__write_cr0 \core_calculate_stage_26_logical_op__invert_out \core_calculate_stage_26_logical_op__input_carry \core_calculate_stage_26_logical_op__zero_a \core_calculate_stage_26_logical_op__invert_in { \core_calculate_stage_26_logical_op__oe__oe_ok \core_calculate_stage_26_logical_op__oe__oe } { \core_calculate_stage_26_logical_op__rc__rc_ok \core_calculate_stage_26_logical_op__rc__rc } { \core_calculate_stage_26_logical_op__imm_data__imm_ok \core_calculate_stage_26_logical_op__imm_data__imm } \core_calculate_stage_26_logical_op__fn_unit \core_calculate_stage_26_logical_op__insn_type } { \core_calculate_stage_25_logical_op__insn$85 \core_calculate_stage_25_logical_op__data_len$84 \core_calculate_stage_25_logical_op__is_signed$83 \core_calculate_stage_25_logical_op__is_32bit$82 \core_calculate_stage_25_logical_op__output_carry$81 \core_calculate_stage_25_logical_op__write_cr0$80 \core_calculate_stage_25_logical_op__invert_out$79 \core_calculate_stage_25_logical_op__input_carry$78 \core_calculate_stage_25_logical_op__zero_a$77 \core_calculate_stage_25_logical_op__invert_in$76 { \core_calculate_stage_25_logical_op__oe__oe_ok$75 \core_calculate_stage_25_logical_op__oe__oe$74 } { \core_calculate_stage_25_logical_op__rc__rc_ok$73 \core_calculate_stage_25_logical_op__rc__rc$72 } { \core_calculate_stage_25_logical_op__imm_data__imm_ok$71 \core_calculate_stage_25_logical_op__imm_data__imm$70 } \core_calculate_stage_25_logical_op__fn_unit$69 \core_calculate_stage_25_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_26_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_26_ra \core_calculate_stage_25_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_26_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_26_rb \core_calculate_stage_25_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_26_xer_so 1'0 - assign \core_calculate_stage_26_xer_so \core_calculate_stage_25_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_26_divisor_neg 1'0 - assign \core_calculate_stage_26_divisor_neg \core_calculate_stage_25_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_26_dividend_neg 1'0 - assign \core_calculate_stage_26_dividend_neg \core_calculate_stage_25_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_26_dive_abs_ov32 1'0 - assign \core_calculate_stage_26_dive_abs_ov32 \core_calculate_stage_25_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_26_dive_abs_ov64 1'0 - assign \core_calculate_stage_26_dive_abs_ov64 \core_calculate_stage_25_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_26_div_by_zero 1'0 - assign \core_calculate_stage_26_div_by_zero \core_calculate_stage_25_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_26_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_26_divisor_radicand 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\core_calculate_stage_27_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_27_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_27_logical_op__rc__rc 1'0 - assign \core_calculate_stage_27_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_27_logical_op__oe__oe 1'0 - assign \core_calculate_stage_27_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_27_logical_op__invert_in 1'0 - assign \core_calculate_stage_27_logical_op__zero_a 1'0 - assign \core_calculate_stage_27_logical_op__input_carry 2'00 - assign \core_calculate_stage_27_logical_op__invert_out 1'0 - assign \core_calculate_stage_27_logical_op__write_cr0 1'0 - assign \core_calculate_stage_27_logical_op__output_carry 1'0 - assign \core_calculate_stage_27_logical_op__is_32bit 1'0 - assign \core_calculate_stage_27_logical_op__is_signed 1'0 - assign \core_calculate_stage_27_logical_op__data_len 4'0000 - assign \core_calculate_stage_27_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_27_logical_op__insn \core_calculate_stage_27_logical_op__data_len \core_calculate_stage_27_logical_op__is_signed \core_calculate_stage_27_logical_op__is_32bit \core_calculate_stage_27_logical_op__output_carry \core_calculate_stage_27_logical_op__write_cr0 \core_calculate_stage_27_logical_op__invert_out \core_calculate_stage_27_logical_op__input_carry \core_calculate_stage_27_logical_op__zero_a \core_calculate_stage_27_logical_op__invert_in { \core_calculate_stage_27_logical_op__oe__oe_ok \core_calculate_stage_27_logical_op__oe__oe } { \core_calculate_stage_27_logical_op__rc__rc_ok \core_calculate_stage_27_logical_op__rc__rc } { \core_calculate_stage_27_logical_op__imm_data__imm_ok \core_calculate_stage_27_logical_op__imm_data__imm } \core_calculate_stage_27_logical_op__fn_unit \core_calculate_stage_27_logical_op__insn_type } { \core_calculate_stage_26_logical_op__insn$118 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_27_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_27_logical_op__insn$151 \core_calculate_stage_27_logical_op__data_len$150 \core_calculate_stage_27_logical_op__is_signed$149 \core_calculate_stage_27_logical_op__is_32bit$148 \core_calculate_stage_27_logical_op__output_carry$147 \core_calculate_stage_27_logical_op__write_cr0$146 \core_calculate_stage_27_logical_op__invert_out$145 \core_calculate_stage_27_logical_op__input_carry$144 \core_calculate_stage_27_logical_op__zero_a$143 \core_calculate_stage_27_logical_op__invert_in$142 { \core_calculate_stage_27_logical_op__oe__oe_ok$141 \core_calculate_stage_27_logical_op__oe__oe$140 } { \core_calculate_stage_27_logical_op__rc__rc_ok$139 \core_calculate_stage_27_logical_op__rc__rc$138 } { \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 \core_calculate_stage_27_logical_op__imm_data__imm$136 } \core_calculate_stage_27_logical_op__fn_unit$135 \core_calculate_stage_27_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_27_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_27_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_27_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_27_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_27_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_27_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_27_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_27_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_27_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_27_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_27_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_27_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_27_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_27_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.p" -module \p$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.n" -module \n$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.trial0" -module \trial0$203 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.trial1" -module \trial1$204 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.pe" -module \pe$205 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core" -module \core$202 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$203 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$204 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$205 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'100011 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28" -module \core_calculate_stage_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$202 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.trial0" -module \trial0$207 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src 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parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.trial1" -module \trial1$208 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.pe" -module \pe$209 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core" -module \core$206 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$207 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$208 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$209 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$206 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.trial0" -module \trial0$211 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.trial1" -module \trial1$212 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.pe" -module \pe$213 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core" -module \core$210 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$211 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$212 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$213 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \next_bits - connect \B 6'100001 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$210 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.trial0" -module \trial0$215 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.trial1" -module \trial1$216 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1100000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.pe" -module \pe$217 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core" -module \core$214 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$215 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$216 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$217 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$214 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7" -module \pipe_middle_7 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute 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"ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$200 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$201 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_28_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_28_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_28_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_28_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_28_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_28_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_28_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_28_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_28_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_28_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_28_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_28_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_28_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_28_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_28_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 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"OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_28_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_28_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_28_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_28_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_28_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_28_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_28_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_28_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_28_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_28_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_28_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_28_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_28_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_28_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_28_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_28_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_28_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_28_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_28_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_28_compare_rhs$66 - cell \core_calculate_stage_28 \core_calculate_stage_28 - connect \muxid \core_calculate_stage_28_muxid - connect \logical_op__insn_type \core_calculate_stage_28_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_28_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_28_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_28_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_28_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_28_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_28_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_28_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_28_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_28_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_28_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_28_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_28_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_28_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_28_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_28_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_28_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_28_logical_op__insn - connect \ra \core_calculate_stage_28_ra - connect \rb \core_calculate_stage_28_rb - connect \xer_so \core_calculate_stage_28_xer_so - connect \divisor_neg \core_calculate_stage_28_divisor_neg - connect \dividend_neg \core_calculate_stage_28_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_28_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_28_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_28_div_by_zero - connect \divisor_radicand \core_calculate_stage_28_divisor_radicand - connect \operation \core_calculate_stage_28_operation - connect \quotient_root \core_calculate_stage_28_quotient_root - connect \root_times_radicand \core_calculate_stage_28_root_times_radicand - connect \compare_lhs \core_calculate_stage_28_compare_lhs - connect \compare_rhs \core_calculate_stage_28_compare_rhs - connect \muxid$1 \core_calculate_stage_28_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_28_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_28_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_28_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_28_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_28_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_28_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_28_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_28_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_28_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_28_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_28_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_28_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_28_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_28_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_28_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_28_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_28_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_28_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_28_ra$53 - connect \rb$21 \core_calculate_stage_28_rb$54 - connect \xer_so$22 \core_calculate_stage_28_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_28_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_28_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_28_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_28_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_28_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_28_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_28_operation$62 - connect \quotient_root$30 \core_calculate_stage_28_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_28_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_28_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_28_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_29_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute 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11 \core_calculate_stage_29_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_29_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_29_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_29_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_29_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_29_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_29_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_29_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_29_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_29_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_29_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_29_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_29_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_29_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_29_compare_rhs$99 - cell \core_calculate_stage_29 \core_calculate_stage_29 - connect \muxid \core_calculate_stage_29_muxid - connect \logical_op__insn_type \core_calculate_stage_29_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_29_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_29_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_29_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_29_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_29_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_29_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_29_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_29_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_29_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_29_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_29_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_29_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_29_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_29_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_29_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_29_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_29_logical_op__insn - connect \ra \core_calculate_stage_29_ra - connect \rb \core_calculate_stage_29_rb - connect \xer_so \core_calculate_stage_29_xer_so - connect \divisor_neg \core_calculate_stage_29_divisor_neg - connect \dividend_neg \core_calculate_stage_29_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_29_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_29_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_29_div_by_zero - connect \divisor_radicand \core_calculate_stage_29_divisor_radicand - connect \operation \core_calculate_stage_29_operation - connect \quotient_root \core_calculate_stage_29_quotient_root - connect \root_times_radicand \core_calculate_stage_29_root_times_radicand - connect \compare_lhs \core_calculate_stage_29_compare_lhs - connect \compare_rhs \core_calculate_stage_29_compare_rhs - connect \muxid$1 \core_calculate_stage_29_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_29_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_29_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_29_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_29_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_29_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_29_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_29_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_29_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_29_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_29_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_29_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_29_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_29_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_29_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_29_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_29_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_29_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_29_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_29_ra$86 - connect \rb$21 \core_calculate_stage_29_rb$87 - connect \xer_so$22 \core_calculate_stage_29_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_29_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_29_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_29_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_29_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_29_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_29_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_29_operation$95 - connect \quotient_root$30 \core_calculate_stage_29_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_29_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_29_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_29_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_30_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_30_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_30_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_30_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_30_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_30_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_30_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_30_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_30_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_30_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_30_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_30_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_30_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_30_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_30_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_30_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_30_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_30_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_30_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_30_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_30_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_30_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_30_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_30_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_30_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_30_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_30_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_30_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_30_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_30_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_30_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_30_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_30_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_30_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_30_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_30_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_30_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_30_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_30_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_30_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_30_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_30_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_30_compare_rhs$132 - cell \core_calculate_stage_30 \core_calculate_stage_30 - connect \muxid \core_calculate_stage_30_muxid - connect \logical_op__insn_type \core_calculate_stage_30_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_30_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_30_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_30_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_30_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_30_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_30_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_30_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_30_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_30_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_30_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_30_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_30_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_30_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_30_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_30_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_30_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_30_logical_op__insn - connect \ra \core_calculate_stage_30_ra - connect \rb \core_calculate_stage_30_rb - connect \xer_so \core_calculate_stage_30_xer_so - connect \divisor_neg \core_calculate_stage_30_divisor_neg - connect \dividend_neg \core_calculate_stage_30_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_30_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_30_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_30_div_by_zero - connect \divisor_radicand \core_calculate_stage_30_divisor_radicand - connect \operation \core_calculate_stage_30_operation - connect \quotient_root \core_calculate_stage_30_quotient_root - connect \root_times_radicand \core_calculate_stage_30_root_times_radicand - connect \compare_lhs \core_calculate_stage_30_compare_lhs - connect \compare_rhs \core_calculate_stage_30_compare_rhs - connect \muxid$1 \core_calculate_stage_30_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_30_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_30_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_30_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_30_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_30_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_30_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_30_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_30_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_30_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_30_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_30_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_30_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_30_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_30_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_30_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_30_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_30_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_30_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_30_ra$119 - connect \rb$21 \core_calculate_stage_30_rb$120 - connect \xer_so$22 \core_calculate_stage_30_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_30_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_30_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_30_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_30_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_30_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_30_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_30_operation$128 - connect \quotient_root$30 \core_calculate_stage_30_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_30_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_30_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_30_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_31_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_31_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_31_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_31_logical_op__imm_data__imm - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_31_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_31_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_31_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_31_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_31_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_31_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_31_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_31_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_31_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_31_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_31_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_31_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_31_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_31_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_31_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_31_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_31_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_31_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_31_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_31_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_31_compare_rhs$165 - cell \core_calculate_stage_31 \core_calculate_stage_31 - connect \muxid \core_calculate_stage_31_muxid - connect \logical_op__insn_type \core_calculate_stage_31_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_31_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_31_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_31_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_31_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_31_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_31_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_31_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_31_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_31_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_31_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_31_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_31_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_31_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_31_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_31_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_31_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_31_logical_op__insn - connect \ra \core_calculate_stage_31_ra - connect \rb \core_calculate_stage_31_rb - connect \xer_so \core_calculate_stage_31_xer_so - connect \divisor_neg \core_calculate_stage_31_divisor_neg - connect \dividend_neg \core_calculate_stage_31_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_31_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_31_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_31_div_by_zero - connect \divisor_radicand \core_calculate_stage_31_divisor_radicand - connect \operation \core_calculate_stage_31_operation - connect \quotient_root \core_calculate_stage_31_quotient_root - connect \root_times_radicand \core_calculate_stage_31_root_times_radicand - connect \compare_lhs \core_calculate_stage_31_compare_lhs - connect \compare_rhs \core_calculate_stage_31_compare_rhs - connect \muxid$1 \core_calculate_stage_31_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_31_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_31_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_31_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_31_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_31_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_31_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_31_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_31_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_31_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_31_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_31_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_31_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_31_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_31_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_31_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_31_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_31_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_31_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_31_ra$152 - connect \rb$21 \core_calculate_stage_31_rb$153 - connect \xer_so$22 \core_calculate_stage_31_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_31_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_31_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_31_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_31_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_31_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_31_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_31_operation$161 - connect \quotient_root$30 \core_calculate_stage_31_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_31_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_31_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_31_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_28_muxid 2'00 - assign \core_calculate_stage_28_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_28_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_28_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_28_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_28_logical_op__rc__rc 1'0 - assign \core_calculate_stage_28_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_28_logical_op__oe__oe 1'0 - assign \core_calculate_stage_28_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_28_logical_op__invert_in 1'0 - assign \core_calculate_stage_28_logical_op__zero_a 1'0 - assign \core_calculate_stage_28_logical_op__input_carry 2'00 - assign \core_calculate_stage_28_logical_op__invert_out 1'0 - assign \core_calculate_stage_28_logical_op__write_cr0 1'0 - assign \core_calculate_stage_28_logical_op__output_carry 1'0 - assign \core_calculate_stage_28_logical_op__is_32bit 1'0 - assign \core_calculate_stage_28_logical_op__is_signed 1'0 - assign \core_calculate_stage_28_logical_op__data_len 4'0000 - assign \core_calculate_stage_28_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_28_logical_op__insn \core_calculate_stage_28_logical_op__data_len \core_calculate_stage_28_logical_op__is_signed \core_calculate_stage_28_logical_op__is_32bit \core_calculate_stage_28_logical_op__output_carry \core_calculate_stage_28_logical_op__write_cr0 \core_calculate_stage_28_logical_op__invert_out \core_calculate_stage_28_logical_op__input_carry \core_calculate_stage_28_logical_op__zero_a \core_calculate_stage_28_logical_op__invert_in { \core_calculate_stage_28_logical_op__oe__oe_ok \core_calculate_stage_28_logical_op__oe__oe } { \core_calculate_stage_28_logical_op__rc__rc_ok \core_calculate_stage_28_logical_op__rc__rc } { \core_calculate_stage_28_logical_op__imm_data__imm_ok \core_calculate_stage_28_logical_op__imm_data__imm } \core_calculate_stage_28_logical_op__fn_unit \core_calculate_stage_28_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_28_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_28_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_28_xer_so 1'0 - assign \core_calculate_stage_28_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_28_divisor_neg 1'0 - assign \core_calculate_stage_28_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_28_dividend_neg 1'0 - assign \core_calculate_stage_28_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_28_dive_abs_ov32 1'0 - assign \core_calculate_stage_28_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_28_dive_abs_ov64 1'0 - assign \core_calculate_stage_28_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_28_div_by_zero 1'0 - assign \core_calculate_stage_28_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_28_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_28_operation 2'00 - assign \core_calculate_stage_28_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_28_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_28_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_28_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_28_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_28_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_29_muxid 2'00 - assign \core_calculate_stage_29_muxid \core_calculate_stage_28_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_29_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_29_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_29_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_29_logical_op__rc__rc 1'0 - assign \core_calculate_stage_29_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_29_logical_op__oe__oe 1'0 - assign \core_calculate_stage_29_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_29_logical_op__invert_in 1'0 - assign \core_calculate_stage_29_logical_op__zero_a 1'0 - assign \core_calculate_stage_29_logical_op__input_carry 2'00 - assign \core_calculate_stage_29_logical_op__invert_out 1'0 - assign \core_calculate_stage_29_logical_op__write_cr0 1'0 - assign \core_calculate_stage_29_logical_op__output_carry 1'0 - assign \core_calculate_stage_29_logical_op__is_32bit 1'0 - assign \core_calculate_stage_29_logical_op__is_signed 1'0 - assign \core_calculate_stage_29_logical_op__data_len 4'0000 - assign \core_calculate_stage_29_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_29_logical_op__insn \core_calculate_stage_29_logical_op__data_len \core_calculate_stage_29_logical_op__is_signed \core_calculate_stage_29_logical_op__is_32bit \core_calculate_stage_29_logical_op__output_carry \core_calculate_stage_29_logical_op__write_cr0 \core_calculate_stage_29_logical_op__invert_out \core_calculate_stage_29_logical_op__input_carry \core_calculate_stage_29_logical_op__zero_a \core_calculate_stage_29_logical_op__invert_in { \core_calculate_stage_29_logical_op__oe__oe_ok \core_calculate_stage_29_logical_op__oe__oe } { \core_calculate_stage_29_logical_op__rc__rc_ok \core_calculate_stage_29_logical_op__rc__rc } { \core_calculate_stage_29_logical_op__imm_data__imm_ok \core_calculate_stage_29_logical_op__imm_data__imm } \core_calculate_stage_29_logical_op__fn_unit \core_calculate_stage_29_logical_op__insn_type } { \core_calculate_stage_28_logical_op__insn$52 \core_calculate_stage_28_logical_op__data_len$51 \core_calculate_stage_28_logical_op__is_signed$50 \core_calculate_stage_28_logical_op__is_32bit$49 \core_calculate_stage_28_logical_op__output_carry$48 \core_calculate_stage_28_logical_op__write_cr0$47 \core_calculate_stage_28_logical_op__invert_out$46 \core_calculate_stage_28_logical_op__input_carry$45 \core_calculate_stage_28_logical_op__zero_a$44 \core_calculate_stage_28_logical_op__invert_in$43 { \core_calculate_stage_28_logical_op__oe__oe_ok$42 \core_calculate_stage_28_logical_op__oe__oe$41 } { \core_calculate_stage_28_logical_op__rc__rc_ok$40 \core_calculate_stage_28_logical_op__rc__rc$39 } { \core_calculate_stage_28_logical_op__imm_data__imm_ok$38 \core_calculate_stage_28_logical_op__imm_data__imm$37 } \core_calculate_stage_28_logical_op__fn_unit$36 \core_calculate_stage_28_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_29_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_ra \core_calculate_stage_28_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_29_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_rb \core_calculate_stage_28_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_29_xer_so 1'0 - assign \core_calculate_stage_29_xer_so \core_calculate_stage_28_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_29_divisor_neg 1'0 - assign \core_calculate_stage_29_divisor_neg \core_calculate_stage_28_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_29_dividend_neg 1'0 - assign \core_calculate_stage_29_dividend_neg \core_calculate_stage_28_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_29_dive_abs_ov32 1'0 - assign \core_calculate_stage_29_dive_abs_ov32 \core_calculate_stage_28_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_29_dive_abs_ov64 1'0 - assign \core_calculate_stage_29_dive_abs_ov64 \core_calculate_stage_28_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_29_div_by_zero 1'0 - assign \core_calculate_stage_29_div_by_zero \core_calculate_stage_28_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_29_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_divisor_radicand \core_calculate_stage_28_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_29_operation 2'00 - assign \core_calculate_stage_29_operation \core_calculate_stage_28_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_29_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_quotient_root \core_calculate_stage_28_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_29_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_root_times_radicand \core_calculate_stage_28_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_29_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_compare_lhs \core_calculate_stage_28_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_29_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_29_compare_rhs \core_calculate_stage_28_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_30_muxid 2'00 - assign \core_calculate_stage_30_muxid \core_calculate_stage_29_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_30_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_30_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_30_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_30_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_30_logical_op__rc__rc 1'0 - assign \core_calculate_stage_30_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_30_logical_op__oe__oe 1'0 - assign \core_calculate_stage_30_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_30_logical_op__invert_in 1'0 - assign \core_calculate_stage_30_logical_op__zero_a 1'0 - assign \core_calculate_stage_30_logical_op__input_carry 2'00 - assign \core_calculate_stage_30_logical_op__invert_out 1'0 - assign \core_calculate_stage_30_logical_op__write_cr0 1'0 - assign \core_calculate_stage_30_logical_op__output_carry 1'0 - assign \core_calculate_stage_30_logical_op__is_32bit 1'0 - assign \core_calculate_stage_30_logical_op__is_signed 1'0 - assign \core_calculate_stage_30_logical_op__data_len 4'0000 - assign \core_calculate_stage_30_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_30_logical_op__insn \core_calculate_stage_30_logical_op__data_len \core_calculate_stage_30_logical_op__is_signed \core_calculate_stage_30_logical_op__is_32bit \core_calculate_stage_30_logical_op__output_carry \core_calculate_stage_30_logical_op__write_cr0 \core_calculate_stage_30_logical_op__invert_out \core_calculate_stage_30_logical_op__input_carry \core_calculate_stage_30_logical_op__zero_a \core_calculate_stage_30_logical_op__invert_in { \core_calculate_stage_30_logical_op__oe__oe_ok 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\logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_31_logical_op__insn$151 \core_calculate_stage_31_logical_op__data_len$150 \core_calculate_stage_31_logical_op__is_signed$149 \core_calculate_stage_31_logical_op__is_32bit$148 \core_calculate_stage_31_logical_op__output_carry$147 \core_calculate_stage_31_logical_op__write_cr0$146 \core_calculate_stage_31_logical_op__invert_out$145 \core_calculate_stage_31_logical_op__input_carry$144 \core_calculate_stage_31_logical_op__zero_a$143 \core_calculate_stage_31_logical_op__invert_in$142 { \core_calculate_stage_31_logical_op__oe__oe_ok$141 \core_calculate_stage_31_logical_op__oe__oe$140 } { \core_calculate_stage_31_logical_op__rc__rc_ok$139 \core_calculate_stage_31_logical_op__rc__rc$138 } { \core_calculate_stage_31_logical_op__imm_data__imm_ok$137 \core_calculate_stage_31_logical_op__imm_data__imm$136 } \core_calculate_stage_31_logical_op__fn_unit$135 \core_calculate_stage_31_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_31_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_31_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_31_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_31_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_31_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_31_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_31_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_31_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_31_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_31_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_31_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_31_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_31_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_31_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.p" -module \p$218 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.n" -module \n$219 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.trial0" -module \trial0$221 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.trial1" -module \trial1$222 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.pe" -module \pe$223 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core" -module \core$220 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$221 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$222 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$223 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$220 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.trial0" -module \trial0$225 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.trial1" -module \trial1$226 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.pe" -module \pe$227 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core" -module \core$224 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$225 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$226 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$227 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$224 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.trial0" -module \trial0$229 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.trial1" -module \trial1$230 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.pe" -module \pe$231 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core" -module \core$228 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$229 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$230 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$231 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute 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\enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$228 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.trial0" -module \trial0$233 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.trial1" -module \trial1$234 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.pe" -module \pe$235 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core" -module \core$232 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$233 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$234 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$235 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$218 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$219 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_32_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_32_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_32_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_32_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_32_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_32_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_32_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_32_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_32_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_32_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_32_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_32_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_32_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_32_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_32_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_32_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_32_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_32_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_32_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_32_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_32_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_32_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_32_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_32_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_32_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_32_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_32_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_32_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_32_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_32_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_32_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_32_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_32_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_32_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_32_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_32_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_32_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_32_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_32_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_32_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_32_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_32_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_32_compare_rhs$66 - cell \core_calculate_stage_32 \core_calculate_stage_32 - connect \muxid \core_calculate_stage_32_muxid - connect \logical_op__insn_type \core_calculate_stage_32_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_32_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_32_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_32_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_32_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_32_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_32_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_32_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_32_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_32_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_32_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_32_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_32_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_32_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_32_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_32_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_32_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_32_logical_op__insn - connect \ra \core_calculate_stage_32_ra - connect \rb \core_calculate_stage_32_rb - connect \xer_so \core_calculate_stage_32_xer_so - connect \divisor_neg \core_calculate_stage_32_divisor_neg - connect \dividend_neg \core_calculate_stage_32_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_32_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_32_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_32_div_by_zero - connect \divisor_radicand \core_calculate_stage_32_divisor_radicand - connect \operation \core_calculate_stage_32_operation - connect \quotient_root \core_calculate_stage_32_quotient_root - connect \root_times_radicand \core_calculate_stage_32_root_times_radicand - connect \compare_lhs \core_calculate_stage_32_compare_lhs - connect \compare_rhs \core_calculate_stage_32_compare_rhs - connect \muxid$1 \core_calculate_stage_32_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_32_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_32_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_32_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_32_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_32_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_32_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_32_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_32_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_32_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_32_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_32_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_32_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_32_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_32_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_32_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_32_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_32_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_32_ra$53 - connect \rb$21 \core_calculate_stage_32_rb$54 - connect \xer_so$22 \core_calculate_stage_32_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_32_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_32_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_32_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_32_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_32_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_32_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_32_operation$62 - connect \quotient_root$30 \core_calculate_stage_32_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_32_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_32_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_32_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_33_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_33_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_33_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_33_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_33_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_33_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_33_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_33_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_33_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_33_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_33_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_33_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_33_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_33_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_33_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_33_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_33_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_33_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_33_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_33_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_33_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_33_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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11 \core_calculate_stage_33_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_33_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_33_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_33_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_33_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_33_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_33_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_33_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_33_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_33_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_33_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_33_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_33_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_33_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_33_compare_rhs$99 - cell \core_calculate_stage_33 \core_calculate_stage_33 - connect \muxid \core_calculate_stage_33_muxid - connect \logical_op__insn_type \core_calculate_stage_33_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_33_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_33_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_33_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_33_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_33_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_33_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_33_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_33_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_33_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_33_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_33_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_33_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_33_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_33_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_33_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_33_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_33_logical_op__insn - connect \ra \core_calculate_stage_33_ra - connect \rb \core_calculate_stage_33_rb - connect \xer_so \core_calculate_stage_33_xer_so - connect \divisor_neg \core_calculate_stage_33_divisor_neg - connect \dividend_neg \core_calculate_stage_33_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_33_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_33_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_33_div_by_zero - connect \divisor_radicand \core_calculate_stage_33_divisor_radicand - connect \operation \core_calculate_stage_33_operation - connect \quotient_root \core_calculate_stage_33_quotient_root - connect \root_times_radicand \core_calculate_stage_33_root_times_radicand - connect \compare_lhs \core_calculate_stage_33_compare_lhs - connect \compare_rhs \core_calculate_stage_33_compare_rhs - connect \muxid$1 \core_calculate_stage_33_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_33_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_33_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_33_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_33_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_33_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_33_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_33_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_33_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_33_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_33_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_33_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_33_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_33_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_33_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_33_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_33_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_33_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_33_ra$86 - connect \rb$21 \core_calculate_stage_33_rb$87 - connect \xer_so$22 \core_calculate_stage_33_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_33_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_33_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_33_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_33_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_33_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_33_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_33_operation$95 - connect \quotient_root$30 \core_calculate_stage_33_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_33_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_33_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_33_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_34_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_34_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_34_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_34_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_34_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_34_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_34_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_34_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_34_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_34_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_34_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_34_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_34_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_34_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_34_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_34_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_34_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_34_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_34_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_34_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_34_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_34_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_34_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_34_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_34_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_34_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_34_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_34_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_34_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_34_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_34_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_34_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_34_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_34_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_34_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_34_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_34_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_34_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_34_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_34_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_34_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_34_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_34_compare_rhs$132 - cell \core_calculate_stage_34 \core_calculate_stage_34 - connect \muxid \core_calculate_stage_34_muxid - connect \logical_op__insn_type \core_calculate_stage_34_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_34_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_34_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_34_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_34_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_34_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_34_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_34_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_34_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_34_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_34_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_34_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_34_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_34_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_34_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_34_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_34_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_34_logical_op__insn - connect \ra \core_calculate_stage_34_ra - connect \rb \core_calculate_stage_34_rb - connect \xer_so \core_calculate_stage_34_xer_so - connect \divisor_neg \core_calculate_stage_34_divisor_neg - connect \dividend_neg \core_calculate_stage_34_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_34_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_34_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_34_div_by_zero - connect \divisor_radicand \core_calculate_stage_34_divisor_radicand - connect \operation \core_calculate_stage_34_operation - connect \quotient_root \core_calculate_stage_34_quotient_root - connect \root_times_radicand \core_calculate_stage_34_root_times_radicand - connect \compare_lhs \core_calculate_stage_34_compare_lhs - connect \compare_rhs \core_calculate_stage_34_compare_rhs - connect \muxid$1 \core_calculate_stage_34_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_34_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_34_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_34_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_34_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_34_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_34_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_34_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_34_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_34_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_34_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_34_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_34_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_34_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_34_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_34_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_34_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_34_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_34_ra$119 - connect \rb$21 \core_calculate_stage_34_rb$120 - connect \xer_so$22 \core_calculate_stage_34_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_34_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_34_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_34_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_34_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_34_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_34_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_34_operation$128 - connect \quotient_root$30 \core_calculate_stage_34_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_34_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_34_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_34_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_35_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_35_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_35_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_35_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__zero_a - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_35_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_35_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_35_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_35_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_35_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_35_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_35_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_35_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_35_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_35_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_35_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_35_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_35_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_35_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_35_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_35_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_35_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_35_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_35_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_35_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_35_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_35_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_35_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_35_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_35_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_35_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_35_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_35_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_35_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_35_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_35_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_35_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_35_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_35_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_35_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_35_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_35_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_35_compare_rhs$165 - cell \core_calculate_stage_35 \core_calculate_stage_35 - connect \muxid \core_calculate_stage_35_muxid - connect \logical_op__insn_type \core_calculate_stage_35_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_35_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_35_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_35_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_35_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_35_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_35_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_35_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_35_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_35_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_35_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_35_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_35_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_35_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_35_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_35_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_35_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_35_logical_op__insn - connect \ra \core_calculate_stage_35_ra - connect \rb \core_calculate_stage_35_rb - connect \xer_so \core_calculate_stage_35_xer_so - connect \divisor_neg \core_calculate_stage_35_divisor_neg - connect \dividend_neg \core_calculate_stage_35_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_35_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_35_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_35_div_by_zero - connect \divisor_radicand \core_calculate_stage_35_divisor_radicand - connect \operation \core_calculate_stage_35_operation - connect \quotient_root \core_calculate_stage_35_quotient_root - connect \root_times_radicand \core_calculate_stage_35_root_times_radicand - connect \compare_lhs \core_calculate_stage_35_compare_lhs - connect \compare_rhs \core_calculate_stage_35_compare_rhs - connect \muxid$1 \core_calculate_stage_35_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_35_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_35_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_35_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_35_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_35_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_35_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_35_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_35_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_35_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_35_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_35_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_35_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_35_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_35_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_35_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_35_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_35_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_35_ra$152 - connect \rb$21 \core_calculate_stage_35_rb$153 - connect \xer_so$22 \core_calculate_stage_35_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_35_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_35_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_35_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_35_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_35_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_35_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_35_operation$161 - connect \quotient_root$30 \core_calculate_stage_35_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_35_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_35_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_35_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_32_muxid 2'00 - assign \core_calculate_stage_32_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_32_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_32_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_32_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_32_logical_op__rc__rc 1'0 - assign \core_calculate_stage_32_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_32_logical_op__oe__oe 1'0 - assign \core_calculate_stage_32_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_32_logical_op__invert_in 1'0 - assign \core_calculate_stage_32_logical_op__zero_a 1'0 - assign \core_calculate_stage_32_logical_op__input_carry 2'00 - assign \core_calculate_stage_32_logical_op__invert_out 1'0 - assign \core_calculate_stage_32_logical_op__write_cr0 1'0 - assign \core_calculate_stage_32_logical_op__output_carry 1'0 - assign \core_calculate_stage_32_logical_op__is_32bit 1'0 - assign \core_calculate_stage_32_logical_op__is_signed 1'0 - assign \core_calculate_stage_32_logical_op__data_len 4'0000 - assign \core_calculate_stage_32_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_32_logical_op__insn \core_calculate_stage_32_logical_op__data_len \core_calculate_stage_32_logical_op__is_signed \core_calculate_stage_32_logical_op__is_32bit \core_calculate_stage_32_logical_op__output_carry \core_calculate_stage_32_logical_op__write_cr0 \core_calculate_stage_32_logical_op__invert_out \core_calculate_stage_32_logical_op__input_carry \core_calculate_stage_32_logical_op__zero_a \core_calculate_stage_32_logical_op__invert_in { \core_calculate_stage_32_logical_op__oe__oe_ok \core_calculate_stage_32_logical_op__oe__oe } { \core_calculate_stage_32_logical_op__rc__rc_ok \core_calculate_stage_32_logical_op__rc__rc } { \core_calculate_stage_32_logical_op__imm_data__imm_ok \core_calculate_stage_32_logical_op__imm_data__imm } \core_calculate_stage_32_logical_op__fn_unit \core_calculate_stage_32_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_32_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_32_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_32_xer_so 1'0 - assign \core_calculate_stage_32_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_32_divisor_neg 1'0 - assign \core_calculate_stage_32_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_32_dividend_neg 1'0 - assign \core_calculate_stage_32_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_32_dive_abs_ov32 1'0 - assign \core_calculate_stage_32_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_32_dive_abs_ov64 1'0 - assign \core_calculate_stage_32_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_32_div_by_zero 1'0 - assign \core_calculate_stage_32_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_32_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_32_operation 2'00 - assign \core_calculate_stage_32_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_32_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_32_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_32_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_32_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_32_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_33_muxid 2'00 - assign \core_calculate_stage_33_muxid \core_calculate_stage_32_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_33_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_33_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_33_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_33_logical_op__rc__rc 1'0 - assign \core_calculate_stage_33_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_33_logical_op__oe__oe 1'0 - assign \core_calculate_stage_33_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_33_logical_op__invert_in 1'0 - assign \core_calculate_stage_33_logical_op__zero_a 1'0 - assign \core_calculate_stage_33_logical_op__input_carry 2'00 - assign \core_calculate_stage_33_logical_op__invert_out 1'0 - assign \core_calculate_stage_33_logical_op__write_cr0 1'0 - assign \core_calculate_stage_33_logical_op__output_carry 1'0 - assign \core_calculate_stage_33_logical_op__is_32bit 1'0 - assign \core_calculate_stage_33_logical_op__is_signed 1'0 - assign \core_calculate_stage_33_logical_op__data_len 4'0000 - assign \core_calculate_stage_33_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_33_logical_op__insn \core_calculate_stage_33_logical_op__data_len \core_calculate_stage_33_logical_op__is_signed \core_calculate_stage_33_logical_op__is_32bit \core_calculate_stage_33_logical_op__output_carry \core_calculate_stage_33_logical_op__write_cr0 \core_calculate_stage_33_logical_op__invert_out \core_calculate_stage_33_logical_op__input_carry \core_calculate_stage_33_logical_op__zero_a \core_calculate_stage_33_logical_op__invert_in { \core_calculate_stage_33_logical_op__oe__oe_ok \core_calculate_stage_33_logical_op__oe__oe } { \core_calculate_stage_33_logical_op__rc__rc_ok \core_calculate_stage_33_logical_op__rc__rc } { \core_calculate_stage_33_logical_op__imm_data__imm_ok \core_calculate_stage_33_logical_op__imm_data__imm } \core_calculate_stage_33_logical_op__fn_unit \core_calculate_stage_33_logical_op__insn_type } { \core_calculate_stage_32_logical_op__insn$52 \core_calculate_stage_32_logical_op__data_len$51 \core_calculate_stage_32_logical_op__is_signed$50 \core_calculate_stage_32_logical_op__is_32bit$49 \core_calculate_stage_32_logical_op__output_carry$48 \core_calculate_stage_32_logical_op__write_cr0$47 \core_calculate_stage_32_logical_op__invert_out$46 \core_calculate_stage_32_logical_op__input_carry$45 \core_calculate_stage_32_logical_op__zero_a$44 \core_calculate_stage_32_logical_op__invert_in$43 { \core_calculate_stage_32_logical_op__oe__oe_ok$42 \core_calculate_stage_32_logical_op__oe__oe$41 } { \core_calculate_stage_32_logical_op__rc__rc_ok$40 \core_calculate_stage_32_logical_op__rc__rc$39 } { \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 \core_calculate_stage_32_logical_op__imm_data__imm$37 } \core_calculate_stage_32_logical_op__fn_unit$36 \core_calculate_stage_32_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_33_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_ra \core_calculate_stage_32_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_33_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_rb \core_calculate_stage_32_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_33_xer_so 1'0 - assign \core_calculate_stage_33_xer_so \core_calculate_stage_32_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_33_divisor_neg 1'0 - assign \core_calculate_stage_33_divisor_neg \core_calculate_stage_32_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_33_dividend_neg 1'0 - assign \core_calculate_stage_33_dividend_neg \core_calculate_stage_32_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_33_dive_abs_ov32 1'0 - assign \core_calculate_stage_33_dive_abs_ov32 \core_calculate_stage_32_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_33_dive_abs_ov64 1'0 - assign \core_calculate_stage_33_dive_abs_ov64 \core_calculate_stage_32_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_33_div_by_zero 1'0 - assign \core_calculate_stage_33_div_by_zero \core_calculate_stage_32_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_33_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_divisor_radicand \core_calculate_stage_32_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_33_operation 2'00 - assign \core_calculate_stage_33_operation \core_calculate_stage_32_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_33_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_quotient_root \core_calculate_stage_32_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_33_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_root_times_radicand \core_calculate_stage_32_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_33_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_compare_lhs \core_calculate_stage_32_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_33_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_33_compare_rhs \core_calculate_stage_32_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_34_muxid 2'00 - assign \core_calculate_stage_34_muxid \core_calculate_stage_33_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_34_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_34_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_34_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_34_logical_op__rc__rc 1'0 - assign \core_calculate_stage_34_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_34_logical_op__oe__oe 1'0 - assign \core_calculate_stage_34_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_34_logical_op__invert_in 1'0 - assign \core_calculate_stage_34_logical_op__zero_a 1'0 - assign \core_calculate_stage_34_logical_op__input_carry 2'00 - assign \core_calculate_stage_34_logical_op__invert_out 1'0 - assign \core_calculate_stage_34_logical_op__write_cr0 1'0 - assign \core_calculate_stage_34_logical_op__output_carry 1'0 - assign \core_calculate_stage_34_logical_op__is_32bit 1'0 - assign \core_calculate_stage_34_logical_op__is_signed 1'0 - assign \core_calculate_stage_34_logical_op__data_len 4'0000 - assign \core_calculate_stage_34_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_34_logical_op__insn \core_calculate_stage_34_logical_op__data_len \core_calculate_stage_34_logical_op__is_signed \core_calculate_stage_34_logical_op__is_32bit \core_calculate_stage_34_logical_op__output_carry \core_calculate_stage_34_logical_op__write_cr0 \core_calculate_stage_34_logical_op__invert_out \core_calculate_stage_34_logical_op__input_carry \core_calculate_stage_34_logical_op__zero_a \core_calculate_stage_34_logical_op__invert_in { \core_calculate_stage_34_logical_op__oe__oe_ok \core_calculate_stage_34_logical_op__oe__oe } { \core_calculate_stage_34_logical_op__rc__rc_ok \core_calculate_stage_34_logical_op__rc__rc } { \core_calculate_stage_34_logical_op__imm_data__imm_ok \core_calculate_stage_34_logical_op__imm_data__imm } \core_calculate_stage_34_logical_op__fn_unit \core_calculate_stage_34_logical_op__insn_type } { \core_calculate_stage_33_logical_op__insn$85 \core_calculate_stage_33_logical_op__data_len$84 \core_calculate_stage_33_logical_op__is_signed$83 \core_calculate_stage_33_logical_op__is_32bit$82 \core_calculate_stage_33_logical_op__output_carry$81 \core_calculate_stage_33_logical_op__write_cr0$80 \core_calculate_stage_33_logical_op__invert_out$79 \core_calculate_stage_33_logical_op__input_carry$78 \core_calculate_stage_33_logical_op__zero_a$77 \core_calculate_stage_33_logical_op__invert_in$76 { \core_calculate_stage_33_logical_op__oe__oe_ok$75 \core_calculate_stage_33_logical_op__oe__oe$74 } { \core_calculate_stage_33_logical_op__rc__rc_ok$73 \core_calculate_stage_33_logical_op__rc__rc$72 } { \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 \core_calculate_stage_33_logical_op__imm_data__imm$70 } \core_calculate_stage_33_logical_op__fn_unit$69 \core_calculate_stage_33_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_34_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_ra \core_calculate_stage_33_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_34_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_rb \core_calculate_stage_33_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_34_xer_so 1'0 - assign \core_calculate_stage_34_xer_so \core_calculate_stage_33_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_34_divisor_neg 1'0 - assign \core_calculate_stage_34_divisor_neg \core_calculate_stage_33_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_34_dividend_neg 1'0 - assign \core_calculate_stage_34_dividend_neg \core_calculate_stage_33_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_34_dive_abs_ov32 1'0 - assign \core_calculate_stage_34_dive_abs_ov32 \core_calculate_stage_33_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_34_dive_abs_ov64 1'0 - assign \core_calculate_stage_34_dive_abs_ov64 \core_calculate_stage_33_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_34_div_by_zero 1'0 - assign \core_calculate_stage_34_div_by_zero \core_calculate_stage_33_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_34_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_divisor_radicand \core_calculate_stage_33_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_34_operation 2'00 - assign \core_calculate_stage_34_operation \core_calculate_stage_33_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_34_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_quotient_root \core_calculate_stage_33_quotient_root$96 - sync init - end - process $group_96 - assign \core_calculate_stage_34_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_root_times_radicand \core_calculate_stage_33_root_times_radicand$97 - sync init - end - process $group_97 - assign \core_calculate_stage_34_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_compare_lhs \core_calculate_stage_33_compare_lhs$98 - sync init - end - process $group_98 - assign \core_calculate_stage_34_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_34_compare_rhs \core_calculate_stage_33_compare_rhs$99 - sync init - end - process $group_99 - assign \core_calculate_stage_35_muxid 2'00 - assign \core_calculate_stage_35_muxid \core_calculate_stage_34_muxid$100 - sync init - end - process $group_100 - assign \core_calculate_stage_35_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_35_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_35_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_35_logical_op__rc__rc 1'0 - assign \core_calculate_stage_35_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_35_logical_op__oe__oe 1'0 - assign \core_calculate_stage_35_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_35_logical_op__invert_in 1'0 - assign \core_calculate_stage_35_logical_op__zero_a 1'0 - assign \core_calculate_stage_35_logical_op__input_carry 2'00 - assign \core_calculate_stage_35_logical_op__invert_out 1'0 - assign \core_calculate_stage_35_logical_op__write_cr0 1'0 - assign \core_calculate_stage_35_logical_op__output_carry 1'0 - assign \core_calculate_stage_35_logical_op__is_32bit 1'0 - assign \core_calculate_stage_35_logical_op__is_signed 1'0 - assign \core_calculate_stage_35_logical_op__data_len 4'0000 - assign \core_calculate_stage_35_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_35_logical_op__insn \core_calculate_stage_35_logical_op__data_len \core_calculate_stage_35_logical_op__is_signed \core_calculate_stage_35_logical_op__is_32bit \core_calculate_stage_35_logical_op__output_carry \core_calculate_stage_35_logical_op__write_cr0 \core_calculate_stage_35_logical_op__invert_out \core_calculate_stage_35_logical_op__input_carry \core_calculate_stage_35_logical_op__zero_a \core_calculate_stage_35_logical_op__invert_in { \core_calculate_stage_35_logical_op__oe__oe_ok \core_calculate_stage_35_logical_op__oe__oe } { \core_calculate_stage_35_logical_op__rc__rc_ok \core_calculate_stage_35_logical_op__rc__rc } { \core_calculate_stage_35_logical_op__imm_data__imm_ok \core_calculate_stage_35_logical_op__imm_data__imm } \core_calculate_stage_35_logical_op__fn_unit \core_calculate_stage_35_logical_op__insn_type } { \core_calculate_stage_34_logical_op__insn$118 \core_calculate_stage_34_logical_op__data_len$117 \core_calculate_stage_34_logical_op__is_signed$116 \core_calculate_stage_34_logical_op__is_32bit$115 \core_calculate_stage_34_logical_op__output_carry$114 \core_calculate_stage_34_logical_op__write_cr0$113 \core_calculate_stage_34_logical_op__invert_out$112 \core_calculate_stage_34_logical_op__input_carry$111 \core_calculate_stage_34_logical_op__zero_a$110 \core_calculate_stage_34_logical_op__invert_in$109 { \core_calculate_stage_34_logical_op__oe__oe_ok$108 \core_calculate_stage_34_logical_op__oe__oe$107 } { \core_calculate_stage_34_logical_op__rc__rc_ok$106 \core_calculate_stage_34_logical_op__rc__rc$105 } { \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 \core_calculate_stage_34_logical_op__imm_data__imm$103 } \core_calculate_stage_34_logical_op__fn_unit$102 \core_calculate_stage_34_logical_op__insn_type$101 } - sync init - end - process $group_118 - assign \core_calculate_stage_35_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_ra \core_calculate_stage_34_ra$119 - sync init - end - process $group_119 - assign \core_calculate_stage_35_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_rb \core_calculate_stage_34_rb$120 - sync init - end - process $group_120 - assign \core_calculate_stage_35_xer_so 1'0 - assign \core_calculate_stage_35_xer_so \core_calculate_stage_34_xer_so$121 - sync init - end - process $group_121 - assign \core_calculate_stage_35_divisor_neg 1'0 - assign \core_calculate_stage_35_divisor_neg \core_calculate_stage_34_divisor_neg$122 - sync init - end - process $group_122 - assign \core_calculate_stage_35_dividend_neg 1'0 - assign \core_calculate_stage_35_dividend_neg \core_calculate_stage_34_dividend_neg$123 - sync init - end - process $group_123 - assign \core_calculate_stage_35_dive_abs_ov32 1'0 - assign \core_calculate_stage_35_dive_abs_ov32 \core_calculate_stage_34_dive_abs_ov32$124 - sync init - end - process $group_124 - assign \core_calculate_stage_35_dive_abs_ov64 1'0 - assign \core_calculate_stage_35_dive_abs_ov64 \core_calculate_stage_34_dive_abs_ov64$125 - sync init - end - process $group_125 - assign \core_calculate_stage_35_div_by_zero 1'0 - assign \core_calculate_stage_35_div_by_zero \core_calculate_stage_34_div_by_zero$126 - sync init - end - process $group_126 - assign \core_calculate_stage_35_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_divisor_radicand \core_calculate_stage_34_divisor_radicand$127 - sync init - end - process $group_127 - assign \core_calculate_stage_35_operation 2'00 - assign \core_calculate_stage_35_operation \core_calculate_stage_34_operation$128 - sync init - end - process $group_128 - assign \core_calculate_stage_35_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_quotient_root \core_calculate_stage_34_quotient_root$129 - sync init - end - process $group_129 - assign \core_calculate_stage_35_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_root_times_radicand \core_calculate_stage_34_root_times_radicand$130 - sync init - end - process $group_130 - assign \core_calculate_stage_35_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_compare_lhs \core_calculate_stage_34_compare_lhs$131 - sync init - end - process $group_131 - assign \core_calculate_stage_35_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_35_compare_rhs \core_calculate_stage_34_compare_rhs$132 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$166 - process $group_132 - assign \p_valid_i$166 1'0 - assign \p_valid_i$166 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_133 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_35_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_35_logical_op__insn$151 \core_calculate_stage_35_logical_op__data_len$150 \core_calculate_stage_35_logical_op__is_signed$149 \core_calculate_stage_35_logical_op__is_32bit$148 \core_calculate_stage_35_logical_op__output_carry$147 \core_calculate_stage_35_logical_op__write_cr0$146 \core_calculate_stage_35_logical_op__invert_out$145 \core_calculate_stage_35_logical_op__input_carry$144 \core_calculate_stage_35_logical_op__zero_a$143 \core_calculate_stage_35_logical_op__invert_in$142 { \core_calculate_stage_35_logical_op__oe__oe_ok$141 \core_calculate_stage_35_logical_op__oe__oe$140 } { \core_calculate_stage_35_logical_op__rc__rc_ok$139 \core_calculate_stage_35_logical_op__rc__rc$138 } { \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 \core_calculate_stage_35_logical_op__imm_data__imm$136 } \core_calculate_stage_35_logical_op__fn_unit$135 \core_calculate_stage_35_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_35_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_35_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_35_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_35_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_35_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_35_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_35_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_35_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_35_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_35_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_35_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_35_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_35_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_35_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.p" -module \p$236 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.n" -module \n$237 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.trial0" -module \trial0$239 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.trial1" -module \trial1$240 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.pe" -module \pe$241 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core" -module \core$238 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$239 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$240 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$241 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$238 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.trial0" -module \trial0$243 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.trial1" -module \trial1$244 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.pe" -module \pe$245 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core" -module \core$242 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$243 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$244 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$245 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 32 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A \next_bits - connect \B 5'11010 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$242 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { 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\core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.trial0" -module \trial0$247 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.trial1" -module \trial1$248 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.pe" -module \pe$249 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$247 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$248 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$249 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$246 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.trial0" -module \trial0$251 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.trial1" -module \trial1$252 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1011000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.pe" -module \pe$253 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core" -module \core$250 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$251 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$252 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$253 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 32 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A \next_bits - connect \B 5'11000 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39" -module \core_calculate_stage_39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$250 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$236 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$237 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_36_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_36_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_36_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_36_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_36_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_36_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_36_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_36_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_36_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_36_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_36_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_36_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_36_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_36_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_36_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_36_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_36_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_36_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_36_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_36_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_36_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_36_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_36_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_36_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_36_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_36_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_36_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_36_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_36_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_36_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_36_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_36_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_36_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_36_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_36_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_36_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_36_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_36_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_36_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_36_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_36_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_36_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_36_compare_rhs$66 - cell \core_calculate_stage_36 \core_calculate_stage_36 - connect \muxid \core_calculate_stage_36_muxid - connect \logical_op__insn_type \core_calculate_stage_36_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_36_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_36_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_36_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_36_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_36_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_36_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_36_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_36_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_36_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_36_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_36_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_36_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_36_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_36_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_36_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_36_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_36_logical_op__insn - connect \ra \core_calculate_stage_36_ra - connect \rb \core_calculate_stage_36_rb - connect \xer_so \core_calculate_stage_36_xer_so - connect \divisor_neg \core_calculate_stage_36_divisor_neg - connect \dividend_neg \core_calculate_stage_36_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_36_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_36_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_36_div_by_zero - connect \divisor_radicand \core_calculate_stage_36_divisor_radicand - connect \operation \core_calculate_stage_36_operation - connect \quotient_root \core_calculate_stage_36_quotient_root - connect \root_times_radicand \core_calculate_stage_36_root_times_radicand - connect \compare_lhs \core_calculate_stage_36_compare_lhs - connect \compare_rhs \core_calculate_stage_36_compare_rhs - connect \muxid$1 \core_calculate_stage_36_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_36_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_36_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_36_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_36_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_36_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_36_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_36_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_36_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_36_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_36_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_36_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_36_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_36_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_36_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_36_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_36_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_36_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_36_ra$53 - connect \rb$21 \core_calculate_stage_36_rb$54 - connect \xer_so$22 \core_calculate_stage_36_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_36_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_36_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_36_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_36_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_36_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_36_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_36_operation$62 - connect \quotient_root$30 \core_calculate_stage_36_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_36_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_36_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_36_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_37_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_37_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_37_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_37_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_37_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_37_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_37_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_37_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_37_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_37_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_37_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_37_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_37_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_37_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_37_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_37_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_37_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_37_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_37_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_37_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_37_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_37_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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11 \core_calculate_stage_37_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_37_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_37_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_37_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_37_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_37_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_37_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_37_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_37_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_37_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_37_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_37_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_37_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_37_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_37_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_37_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_37_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_37_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_37_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_37_compare_rhs$99 - cell \core_calculate_stage_37 \core_calculate_stage_37 - connect \muxid \core_calculate_stage_37_muxid - connect \logical_op__insn_type \core_calculate_stage_37_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_37_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_37_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_37_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_37_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_37_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_37_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_37_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_37_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_37_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_37_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_37_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_37_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_37_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_37_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_37_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_37_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_37_logical_op__insn - connect \ra \core_calculate_stage_37_ra - connect \rb \core_calculate_stage_37_rb - connect \xer_so \core_calculate_stage_37_xer_so - connect \divisor_neg \core_calculate_stage_37_divisor_neg - connect \dividend_neg \core_calculate_stage_37_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_37_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_37_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_37_div_by_zero - connect \divisor_radicand \core_calculate_stage_37_divisor_radicand - connect \operation \core_calculate_stage_37_operation - connect \quotient_root \core_calculate_stage_37_quotient_root - connect \root_times_radicand \core_calculate_stage_37_root_times_radicand - connect \compare_lhs \core_calculate_stage_37_compare_lhs - connect \compare_rhs \core_calculate_stage_37_compare_rhs - connect \muxid$1 \core_calculate_stage_37_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_37_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_37_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_37_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_37_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_37_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_37_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_37_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_37_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_37_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_37_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_37_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_37_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_37_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_37_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_37_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_37_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_37_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_37_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_37_ra$86 - connect \rb$21 \core_calculate_stage_37_rb$87 - connect \xer_so$22 \core_calculate_stage_37_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_37_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_37_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_37_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_37_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_37_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_37_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_37_operation$95 - connect \quotient_root$30 \core_calculate_stage_37_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_37_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_37_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_37_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_38_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_38_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_38_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_38_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_38_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_38_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_38_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_38_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_38_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_38_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_38_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_38_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_38_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_38_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_38_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_38_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_38_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_38_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_38_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_38_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_38_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_38_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_38_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_38_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_38_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_38_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_38_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_38_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_38_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_38_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_38_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_38_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_38_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_38_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_38_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_38_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_38_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_38_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_38_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_38_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_38_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_38_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_38_compare_rhs$132 - cell \core_calculate_stage_38 \core_calculate_stage_38 - connect \muxid \core_calculate_stage_38_muxid - connect \logical_op__insn_type \core_calculate_stage_38_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_38_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_38_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_38_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_38_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_38_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_38_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_38_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_38_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_38_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_38_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_38_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_38_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_38_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_38_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_38_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_38_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_38_logical_op__insn - connect \ra \core_calculate_stage_38_ra - connect \rb \core_calculate_stage_38_rb - connect \xer_so \core_calculate_stage_38_xer_so - connect \divisor_neg \core_calculate_stage_38_divisor_neg - connect \dividend_neg \core_calculate_stage_38_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_38_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_38_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_38_div_by_zero - connect \divisor_radicand \core_calculate_stage_38_divisor_radicand - connect \operation \core_calculate_stage_38_operation - connect \quotient_root \core_calculate_stage_38_quotient_root - connect \root_times_radicand \core_calculate_stage_38_root_times_radicand - connect \compare_lhs \core_calculate_stage_38_compare_lhs - connect \compare_rhs \core_calculate_stage_38_compare_rhs - connect \muxid$1 \core_calculate_stage_38_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_38_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_38_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_38_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_38_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_38_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_38_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_38_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_38_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_38_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_38_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_38_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_38_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_38_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_38_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_38_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_38_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_38_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_38_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_38_ra$119 - connect \rb$21 \core_calculate_stage_38_rb$120 - connect \xer_so$22 \core_calculate_stage_38_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_38_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_38_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_38_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_38_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_38_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_38_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_38_operation$128 - connect \quotient_root$30 \core_calculate_stage_38_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_38_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_38_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_38_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_39_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_39_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_39_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_39_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_39_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_39_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_39_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_39_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_39_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_39_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_39_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_39_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_39_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_39_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_39_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_39_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_39_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_39_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_39_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_39_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_39_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_39_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_39_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_39_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_39_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_39_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_39_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_39_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_39_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_39_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_39_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_39_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_39_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_39_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_39_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_39_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_39_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_39_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_39_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_39_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_39_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_39_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_39_compare_rhs$165 - cell \core_calculate_stage_39 \core_calculate_stage_39 - connect \muxid \core_calculate_stage_39_muxid - connect \logical_op__insn_type \core_calculate_stage_39_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_39_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_39_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_39_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_39_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_39_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_39_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_39_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_39_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_39_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_39_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_39_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_39_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_39_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_39_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_39_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_39_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_39_logical_op__insn - connect \ra \core_calculate_stage_39_ra - connect \rb \core_calculate_stage_39_rb - connect \xer_so \core_calculate_stage_39_xer_so - connect \divisor_neg \core_calculate_stage_39_divisor_neg - connect \dividend_neg \core_calculate_stage_39_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_39_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_39_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_39_div_by_zero - connect \divisor_radicand \core_calculate_stage_39_divisor_radicand - connect \operation \core_calculate_stage_39_operation - connect \quotient_root \core_calculate_stage_39_quotient_root - connect \root_times_radicand \core_calculate_stage_39_root_times_radicand - connect \compare_lhs \core_calculate_stage_39_compare_lhs - connect \compare_rhs \core_calculate_stage_39_compare_rhs - connect \muxid$1 \core_calculate_stage_39_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_39_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_39_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_39_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_39_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_39_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_39_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_39_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_39_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_39_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_39_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_39_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_39_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_39_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_39_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_39_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_39_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_39_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_39_ra$152 - connect \rb$21 \core_calculate_stage_39_rb$153 - connect \xer_so$22 \core_calculate_stage_39_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_39_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_39_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_39_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_39_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_39_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_39_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_39_operation$161 - connect \quotient_root$30 \core_calculate_stage_39_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_39_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_39_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_39_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_36_muxid 2'00 - assign \core_calculate_stage_36_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_36_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_36_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_36_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_36_logical_op__rc__rc 1'0 - assign \core_calculate_stage_36_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_36_logical_op__oe__oe 1'0 - assign \core_calculate_stage_36_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_36_logical_op__invert_in 1'0 - assign \core_calculate_stage_36_logical_op__zero_a 1'0 - assign \core_calculate_stage_36_logical_op__input_carry 2'00 - assign \core_calculate_stage_36_logical_op__invert_out 1'0 - assign \core_calculate_stage_36_logical_op__write_cr0 1'0 - assign \core_calculate_stage_36_logical_op__output_carry 1'0 - assign \core_calculate_stage_36_logical_op__is_32bit 1'0 - assign \core_calculate_stage_36_logical_op__is_signed 1'0 - assign \core_calculate_stage_36_logical_op__data_len 4'0000 - assign \core_calculate_stage_36_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_36_logical_op__insn \core_calculate_stage_36_logical_op__data_len \core_calculate_stage_36_logical_op__is_signed \core_calculate_stage_36_logical_op__is_32bit \core_calculate_stage_36_logical_op__output_carry \core_calculate_stage_36_logical_op__write_cr0 \core_calculate_stage_36_logical_op__invert_out \core_calculate_stage_36_logical_op__input_carry \core_calculate_stage_36_logical_op__zero_a \core_calculate_stage_36_logical_op__invert_in { \core_calculate_stage_36_logical_op__oe__oe_ok \core_calculate_stage_36_logical_op__oe__oe } { \core_calculate_stage_36_logical_op__rc__rc_ok \core_calculate_stage_36_logical_op__rc__rc } { \core_calculate_stage_36_logical_op__imm_data__imm_ok \core_calculate_stage_36_logical_op__imm_data__imm } \core_calculate_stage_36_logical_op__fn_unit \core_calculate_stage_36_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_36_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_36_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_36_xer_so 1'0 - assign \core_calculate_stage_36_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_36_divisor_neg 1'0 - assign \core_calculate_stage_36_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_36_dividend_neg 1'0 - assign \core_calculate_stage_36_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_36_dive_abs_ov32 1'0 - assign \core_calculate_stage_36_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_36_dive_abs_ov64 1'0 - assign \core_calculate_stage_36_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_36_div_by_zero 1'0 - assign \core_calculate_stage_36_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_36_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_36_operation 2'00 - assign \core_calculate_stage_36_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_36_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_36_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_36_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_36_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_36_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_37_muxid 2'00 - assign \core_calculate_stage_37_muxid \core_calculate_stage_36_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_37_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_37_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_37_logical_op__imm_data__imm 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\core_calculate_stage_36_logical_op__is_signed$50 \core_calculate_stage_36_logical_op__is_32bit$49 \core_calculate_stage_36_logical_op__output_carry$48 \core_calculate_stage_36_logical_op__write_cr0$47 \core_calculate_stage_36_logical_op__invert_out$46 \core_calculate_stage_36_logical_op__input_carry$45 \core_calculate_stage_36_logical_op__zero_a$44 \core_calculate_stage_36_logical_op__invert_in$43 { \core_calculate_stage_36_logical_op__oe__oe_ok$42 \core_calculate_stage_36_logical_op__oe__oe$41 } { \core_calculate_stage_36_logical_op__rc__rc_ok$40 \core_calculate_stage_36_logical_op__rc__rc$39 } { \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 \core_calculate_stage_36_logical_op__imm_data__imm$37 } \core_calculate_stage_36_logical_op__fn_unit$36 \core_calculate_stage_36_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_37_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_37_ra 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\core_calculate_stage_36_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_38_muxid 2'00 - assign \core_calculate_stage_38_muxid \core_calculate_stage_37_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_38_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_38_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_38_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_38_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_38_logical_op__rc__rc 1'0 - assign \core_calculate_stage_38_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_38_logical_op__oe__oe 1'0 - assign \core_calculate_stage_38_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_38_logical_op__invert_in 1'0 - assign \core_calculate_stage_38_logical_op__zero_a 1'0 - assign \core_calculate_stage_38_logical_op__input_carry 2'00 - assign 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\core_calculate_stage_38_logical_op__oe__oe } { \core_calculate_stage_38_logical_op__rc__rc_ok \core_calculate_stage_38_logical_op__rc__rc } { \core_calculate_stage_38_logical_op__imm_data__imm_ok \core_calculate_stage_38_logical_op__imm_data__imm } \core_calculate_stage_38_logical_op__fn_unit \core_calculate_stage_38_logical_op__insn_type } { \core_calculate_stage_37_logical_op__insn$85 \core_calculate_stage_37_logical_op__data_len$84 \core_calculate_stage_37_logical_op__is_signed$83 \core_calculate_stage_37_logical_op__is_32bit$82 \core_calculate_stage_37_logical_op__output_carry$81 \core_calculate_stage_37_logical_op__write_cr0$80 \core_calculate_stage_37_logical_op__invert_out$79 \core_calculate_stage_37_logical_op__input_carry$78 \core_calculate_stage_37_logical_op__zero_a$77 \core_calculate_stage_37_logical_op__invert_in$76 { \core_calculate_stage_37_logical_op__oe__oe_ok$75 \core_calculate_stage_37_logical_op__oe__oe$74 } { \core_calculate_stage_37_logical_op__rc__rc_ok$73 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\enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_39_logical_op__insn$151 \core_calculate_stage_39_logical_op__data_len$150 \core_calculate_stage_39_logical_op__is_signed$149 \core_calculate_stage_39_logical_op__is_32bit$148 \core_calculate_stage_39_logical_op__output_carry$147 \core_calculate_stage_39_logical_op__write_cr0$146 \core_calculate_stage_39_logical_op__invert_out$145 \core_calculate_stage_39_logical_op__input_carry$144 \core_calculate_stage_39_logical_op__zero_a$143 \core_calculate_stage_39_logical_op__invert_in$142 { \core_calculate_stage_39_logical_op__oe__oe_ok$141 \core_calculate_stage_39_logical_op__oe__oe$140 } { \core_calculate_stage_39_logical_op__rc__rc_ok$139 \core_calculate_stage_39_logical_op__rc__rc$138 } { \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 \core_calculate_stage_39_logical_op__imm_data__imm$136 } \core_calculate_stage_39_logical_op__fn_unit$135 \core_calculate_stage_39_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_39_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_39_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_39_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_39_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_39_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_39_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_39_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_39_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_39_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_39_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_39_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_39_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_39_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_39_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.p" -module \p$254 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.n" -module \n$255 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.trial0" -module \trial0$257 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.trial1" -module \trial1$258 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.pe" -module \pe$259 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core" -module \core$256 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$257 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$258 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$259 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40" -module \core_calculate_stage_40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$256 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.trial0" -module \trial0$261 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src 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1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.trial1" -module \trial1$262 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.pe" -module \pe$263 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core" -module \core$260 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$261 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$262 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$263 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$260 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.trial0" -module \trial0$265 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.trial1" -module \trial1$266 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.pe" -module \pe$267 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core" -module \core$264 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$265 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$266 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$267 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 32 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 32 - connect \A \next_bits - connect \B 5'10101 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$264 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.trial0" -module \trial0$269 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.trial1" -module \trial1$270 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.pe" -module \pe$271 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core" -module \core$268 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$269 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$270 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$271 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$268 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10" -module \pipe_middle_10 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute 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"ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$254 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$255 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_40_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_40_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_40_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_40_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_40_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_40_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_40_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_40_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_40_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_40_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_40_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_40_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_40_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_40_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_40_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 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"OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_40_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_40_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_40_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_40_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_40_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_40_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_40_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_40_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_40_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_40_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_40_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_40_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_40_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_40_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_40_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_40_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_40_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_40_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_40_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_40_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_40_compare_rhs$66 - cell \core_calculate_stage_40 \core_calculate_stage_40 - connect \muxid \core_calculate_stage_40_muxid - connect \logical_op__insn_type \core_calculate_stage_40_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_40_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_40_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_40_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_40_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_40_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_40_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_40_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_40_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_40_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_40_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_40_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_40_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_40_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_40_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_40_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_40_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_40_logical_op__insn - connect \ra \core_calculate_stage_40_ra - connect \rb \core_calculate_stage_40_rb - connect \xer_so \core_calculate_stage_40_xer_so - connect \divisor_neg \core_calculate_stage_40_divisor_neg - connect \dividend_neg \core_calculate_stage_40_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_40_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_40_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_40_div_by_zero - connect \divisor_radicand \core_calculate_stage_40_divisor_radicand - connect \operation \core_calculate_stage_40_operation - connect \quotient_root \core_calculate_stage_40_quotient_root - connect \root_times_radicand \core_calculate_stage_40_root_times_radicand - connect \compare_lhs \core_calculate_stage_40_compare_lhs - connect \compare_rhs \core_calculate_stage_40_compare_rhs - connect \muxid$1 \core_calculate_stage_40_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_40_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_40_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_40_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_40_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_40_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_40_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_40_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_40_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_40_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_40_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_40_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_40_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_40_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_40_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_40_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_40_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_40_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_40_ra$53 - connect \rb$21 \core_calculate_stage_40_rb$54 - connect \xer_so$22 \core_calculate_stage_40_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_40_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_40_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_40_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_40_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_40_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_40_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_40_operation$62 - connect \quotient_root$30 \core_calculate_stage_40_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_40_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_40_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_40_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_41_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_41_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_41_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_41_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_41_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_41_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_41_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_41_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_41_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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11 \core_calculate_stage_41_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_41_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_41_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_41_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_41_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_41_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_41_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_41_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_41_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_41_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_41_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_41_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_41_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_41_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_41_compare_rhs$99 - cell \core_calculate_stage_41 \core_calculate_stage_41 - connect \muxid \core_calculate_stage_41_muxid - connect \logical_op__insn_type \core_calculate_stage_41_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_41_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_41_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_41_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_41_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_41_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_41_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_41_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_41_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_41_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_41_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_41_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_41_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_41_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_41_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_41_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_41_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_41_logical_op__insn - connect \ra \core_calculate_stage_41_ra - connect \rb \core_calculate_stage_41_rb - connect \xer_so \core_calculate_stage_41_xer_so - connect \divisor_neg \core_calculate_stage_41_divisor_neg - connect \dividend_neg \core_calculate_stage_41_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_41_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_41_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_41_div_by_zero - connect \divisor_radicand \core_calculate_stage_41_divisor_radicand - connect \operation \core_calculate_stage_41_operation - connect \quotient_root \core_calculate_stage_41_quotient_root - connect \root_times_radicand \core_calculate_stage_41_root_times_radicand - connect \compare_lhs \core_calculate_stage_41_compare_lhs - connect \compare_rhs \core_calculate_stage_41_compare_rhs - connect \muxid$1 \core_calculate_stage_41_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_41_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_41_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_41_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_41_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_41_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_41_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_41_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_41_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_41_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_41_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_41_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_41_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_41_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_41_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_41_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_41_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_41_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_41_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_41_ra$86 - connect \rb$21 \core_calculate_stage_41_rb$87 - connect \xer_so$22 \core_calculate_stage_41_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_41_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_41_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_41_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_41_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_41_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_41_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_41_operation$95 - connect \quotient_root$30 \core_calculate_stage_41_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_41_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_41_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_41_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_42_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_42_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_42_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_42_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_42_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_42_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_42_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_42_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_42_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_42_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_42_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_42_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_42_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_42_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_42_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_42_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_42_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_42_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_42_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_42_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_42_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_42_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_42_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_42_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_42_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_42_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_42_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_42_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_42_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_42_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_42_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_42_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_42_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_42_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_42_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_42_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_42_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_42_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_42_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_42_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_42_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_42_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_42_compare_rhs$132 - cell \core_calculate_stage_42 \core_calculate_stage_42 - connect \muxid \core_calculate_stage_42_muxid - connect \logical_op__insn_type \core_calculate_stage_42_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_42_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_42_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_42_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_42_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_42_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_42_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_42_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_42_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_42_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_42_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_42_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_42_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_42_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_42_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_42_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_42_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_42_logical_op__insn - connect \ra \core_calculate_stage_42_ra - connect \rb \core_calculate_stage_42_rb - connect \xer_so \core_calculate_stage_42_xer_so - connect \divisor_neg \core_calculate_stage_42_divisor_neg - connect \dividend_neg \core_calculate_stage_42_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_42_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_42_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_42_div_by_zero - connect \divisor_radicand \core_calculate_stage_42_divisor_radicand - connect \operation \core_calculate_stage_42_operation - connect \quotient_root \core_calculate_stage_42_quotient_root - connect \root_times_radicand \core_calculate_stage_42_root_times_radicand - connect \compare_lhs \core_calculate_stage_42_compare_lhs - connect \compare_rhs \core_calculate_stage_42_compare_rhs - connect \muxid$1 \core_calculate_stage_42_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_42_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_42_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_42_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_42_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_42_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_42_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_42_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_42_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_42_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_42_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_42_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_42_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_42_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_42_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_42_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_42_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_42_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_42_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_42_ra$119 - connect \rb$21 \core_calculate_stage_42_rb$120 - connect \xer_so$22 \core_calculate_stage_42_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_42_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_42_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_42_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_42_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_42_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_42_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_42_operation$128 - connect \quotient_root$30 \core_calculate_stage_42_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_42_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_42_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_42_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_43_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_43_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_43_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_43_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__zero_a - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_43_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_43_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_43_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_43_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_43_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_43_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_43_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_43_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_43_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_43_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_43_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_43_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_43_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_43_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_43_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_43_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_43_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_43_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_43_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_43_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_43_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_43_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_43_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_43_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_43_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_43_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_43_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_43_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_43_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_43_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_43_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_43_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_43_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_43_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_43_compare_rhs$165 - cell \core_calculate_stage_43 \core_calculate_stage_43 - connect \muxid \core_calculate_stage_43_muxid - connect \logical_op__insn_type \core_calculate_stage_43_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_43_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_43_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_43_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_43_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_43_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_43_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_43_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_43_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_43_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_43_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_43_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_43_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_43_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_43_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_43_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_43_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_43_logical_op__insn - connect \ra \core_calculate_stage_43_ra - connect \rb \core_calculate_stage_43_rb - connect \xer_so \core_calculate_stage_43_xer_so - connect \divisor_neg \core_calculate_stage_43_divisor_neg - connect \dividend_neg \core_calculate_stage_43_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_43_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_43_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_43_div_by_zero - connect \divisor_radicand \core_calculate_stage_43_divisor_radicand - connect \operation \core_calculate_stage_43_operation - connect \quotient_root \core_calculate_stage_43_quotient_root - connect \root_times_radicand \core_calculate_stage_43_root_times_radicand - connect \compare_lhs \core_calculate_stage_43_compare_lhs - connect \compare_rhs \core_calculate_stage_43_compare_rhs - connect \muxid$1 \core_calculate_stage_43_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_43_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_43_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_43_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_43_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_43_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_43_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_43_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_43_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_43_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_43_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_43_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_43_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_43_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_43_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_43_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_43_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_43_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_43_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_43_ra$152 - connect \rb$21 \core_calculate_stage_43_rb$153 - connect \xer_so$22 \core_calculate_stage_43_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_43_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_43_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_43_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_43_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_43_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_43_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_43_operation$161 - connect \quotient_root$30 \core_calculate_stage_43_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_43_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_43_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_43_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_40_muxid 2'00 - assign \core_calculate_stage_40_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_40_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_40_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_40_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_40_logical_op__rc__rc 1'0 - assign \core_calculate_stage_40_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_40_logical_op__oe__oe 1'0 - assign \core_calculate_stage_40_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_40_logical_op__invert_in 1'0 - assign \core_calculate_stage_40_logical_op__zero_a 1'0 - assign \core_calculate_stage_40_logical_op__input_carry 2'00 - assign \core_calculate_stage_40_logical_op__invert_out 1'0 - assign \core_calculate_stage_40_logical_op__write_cr0 1'0 - assign \core_calculate_stage_40_logical_op__output_carry 1'0 - assign \core_calculate_stage_40_logical_op__is_32bit 1'0 - assign \core_calculate_stage_40_logical_op__is_signed 1'0 - assign \core_calculate_stage_40_logical_op__data_len 4'0000 - assign \core_calculate_stage_40_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_40_logical_op__insn \core_calculate_stage_40_logical_op__data_len \core_calculate_stage_40_logical_op__is_signed \core_calculate_stage_40_logical_op__is_32bit \core_calculate_stage_40_logical_op__output_carry \core_calculate_stage_40_logical_op__write_cr0 \core_calculate_stage_40_logical_op__invert_out \core_calculate_stage_40_logical_op__input_carry \core_calculate_stage_40_logical_op__zero_a \core_calculate_stage_40_logical_op__invert_in { \core_calculate_stage_40_logical_op__oe__oe_ok \core_calculate_stage_40_logical_op__oe__oe } { \core_calculate_stage_40_logical_op__rc__rc_ok \core_calculate_stage_40_logical_op__rc__rc } { \core_calculate_stage_40_logical_op__imm_data__imm_ok \core_calculate_stage_40_logical_op__imm_data__imm } \core_calculate_stage_40_logical_op__fn_unit \core_calculate_stage_40_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_40_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_40_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_40_xer_so 1'0 - assign \core_calculate_stage_40_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_40_divisor_neg 1'0 - assign \core_calculate_stage_40_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_40_dividend_neg 1'0 - assign \core_calculate_stage_40_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_40_dive_abs_ov32 1'0 - assign \core_calculate_stage_40_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_40_dive_abs_ov64 1'0 - assign \core_calculate_stage_40_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_40_div_by_zero 1'0 - assign \core_calculate_stage_40_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_40_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_40_operation 2'00 - assign \core_calculate_stage_40_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_40_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_40_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_40_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_40_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_40_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_41_muxid 2'00 - assign \core_calculate_stage_41_muxid \core_calculate_stage_40_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_41_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_41_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_41_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_41_logical_op__rc__rc 1'0 - assign \core_calculate_stage_41_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_41_logical_op__oe__oe 1'0 - assign \core_calculate_stage_41_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_41_logical_op__invert_in 1'0 - assign \core_calculate_stage_41_logical_op__zero_a 1'0 - assign \core_calculate_stage_41_logical_op__input_carry 2'00 - assign \core_calculate_stage_41_logical_op__invert_out 1'0 - assign \core_calculate_stage_41_logical_op__write_cr0 1'0 - assign \core_calculate_stage_41_logical_op__output_carry 1'0 - assign \core_calculate_stage_41_logical_op__is_32bit 1'0 - assign \core_calculate_stage_41_logical_op__is_signed 1'0 - assign \core_calculate_stage_41_logical_op__data_len 4'0000 - assign \core_calculate_stage_41_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_41_logical_op__insn \core_calculate_stage_41_logical_op__data_len \core_calculate_stage_41_logical_op__is_signed \core_calculate_stage_41_logical_op__is_32bit \core_calculate_stage_41_logical_op__output_carry \core_calculate_stage_41_logical_op__write_cr0 \core_calculate_stage_41_logical_op__invert_out \core_calculate_stage_41_logical_op__input_carry \core_calculate_stage_41_logical_op__zero_a \core_calculate_stage_41_logical_op__invert_in { \core_calculate_stage_41_logical_op__oe__oe_ok \core_calculate_stage_41_logical_op__oe__oe } { \core_calculate_stage_41_logical_op__rc__rc_ok \core_calculate_stage_41_logical_op__rc__rc } { \core_calculate_stage_41_logical_op__imm_data__imm_ok \core_calculate_stage_41_logical_op__imm_data__imm } \core_calculate_stage_41_logical_op__fn_unit \core_calculate_stage_41_logical_op__insn_type } { \core_calculate_stage_40_logical_op__insn$52 \core_calculate_stage_40_logical_op__data_len$51 \core_calculate_stage_40_logical_op__is_signed$50 \core_calculate_stage_40_logical_op__is_32bit$49 \core_calculate_stage_40_logical_op__output_carry$48 \core_calculate_stage_40_logical_op__write_cr0$47 \core_calculate_stage_40_logical_op__invert_out$46 \core_calculate_stage_40_logical_op__input_carry$45 \core_calculate_stage_40_logical_op__zero_a$44 \core_calculate_stage_40_logical_op__invert_in$43 { \core_calculate_stage_40_logical_op__oe__oe_ok$42 \core_calculate_stage_40_logical_op__oe__oe$41 } { \core_calculate_stage_40_logical_op__rc__rc_ok$40 \core_calculate_stage_40_logical_op__rc__rc$39 } { \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 \core_calculate_stage_40_logical_op__imm_data__imm$37 } \core_calculate_stage_40_logical_op__fn_unit$36 \core_calculate_stage_40_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_41_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_ra \core_calculate_stage_40_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_41_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_rb \core_calculate_stage_40_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_41_xer_so 1'0 - assign \core_calculate_stage_41_xer_so \core_calculate_stage_40_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_41_divisor_neg 1'0 - assign \core_calculate_stage_41_divisor_neg \core_calculate_stage_40_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_41_dividend_neg 1'0 - assign \core_calculate_stage_41_dividend_neg \core_calculate_stage_40_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_41_dive_abs_ov32 1'0 - assign \core_calculate_stage_41_dive_abs_ov32 \core_calculate_stage_40_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_41_dive_abs_ov64 1'0 - assign \core_calculate_stage_41_dive_abs_ov64 \core_calculate_stage_40_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_41_div_by_zero 1'0 - assign \core_calculate_stage_41_div_by_zero \core_calculate_stage_40_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_41_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_divisor_radicand \core_calculate_stage_40_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_41_operation 2'00 - assign \core_calculate_stage_41_operation \core_calculate_stage_40_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_41_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_quotient_root \core_calculate_stage_40_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_41_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_root_times_radicand \core_calculate_stage_40_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_41_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_compare_lhs \core_calculate_stage_40_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_41_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_41_compare_rhs \core_calculate_stage_40_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_42_muxid 2'00 - assign \core_calculate_stage_42_muxid \core_calculate_stage_41_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_42_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_42_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_42_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_42_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_42_logical_op__rc__rc 1'0 - assign \core_calculate_stage_42_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_42_logical_op__oe__oe 1'0 - assign \core_calculate_stage_42_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_42_logical_op__invert_in 1'0 - assign \core_calculate_stage_42_logical_op__zero_a 1'0 - assign \core_calculate_stage_42_logical_op__input_carry 2'00 - assign \core_calculate_stage_42_logical_op__invert_out 1'0 - assign \core_calculate_stage_42_logical_op__write_cr0 1'0 - assign \core_calculate_stage_42_logical_op__output_carry 1'0 - assign \core_calculate_stage_42_logical_op__is_32bit 1'0 - assign \core_calculate_stage_42_logical_op__is_signed 1'0 - assign \core_calculate_stage_42_logical_op__data_len 4'0000 - assign \core_calculate_stage_42_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_42_logical_op__insn \core_calculate_stage_42_logical_op__data_len \core_calculate_stage_42_logical_op__is_signed \core_calculate_stage_42_logical_op__is_32bit \core_calculate_stage_42_logical_op__output_carry \core_calculate_stage_42_logical_op__write_cr0 \core_calculate_stage_42_logical_op__invert_out \core_calculate_stage_42_logical_op__input_carry \core_calculate_stage_42_logical_op__zero_a \core_calculate_stage_42_logical_op__invert_in { \core_calculate_stage_42_logical_op__oe__oe_ok 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_43_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute 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\logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_43_logical_op__insn$151 \core_calculate_stage_43_logical_op__data_len$150 \core_calculate_stage_43_logical_op__is_signed$149 \core_calculate_stage_43_logical_op__is_32bit$148 \core_calculate_stage_43_logical_op__output_carry$147 \core_calculate_stage_43_logical_op__write_cr0$146 \core_calculate_stage_43_logical_op__invert_out$145 \core_calculate_stage_43_logical_op__input_carry$144 \core_calculate_stage_43_logical_op__zero_a$143 \core_calculate_stage_43_logical_op__invert_in$142 { \core_calculate_stage_43_logical_op__oe__oe_ok$141 \core_calculate_stage_43_logical_op__oe__oe$140 } { \core_calculate_stage_43_logical_op__rc__rc_ok$139 \core_calculate_stage_43_logical_op__rc__rc$138 } { \core_calculate_stage_43_logical_op__imm_data__imm_ok$137 \core_calculate_stage_43_logical_op__imm_data__imm$136 } \core_calculate_stage_43_logical_op__fn_unit$135 \core_calculate_stage_43_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_43_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_43_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_43_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_43_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_43_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_43_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_43_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_43_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_43_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_43_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_43_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_43_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_43_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_43_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.p" -module \p$272 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.n" -module \n$273 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.trial0" -module \trial0$275 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.trial1" -module \trial1$276 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.pe" -module \pe$277 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core" -module \core$274 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$275 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$276 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$277 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$274 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.trial0" -module \trial0$279 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.trial1" -module \trial1$280 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.pe" -module \pe$281 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core" -module \core$278 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$279 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$280 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$281 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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\src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$278 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.trial0" -module \trial0$283 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.trial1" -module \trial1$284 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.pe" -module \pe$285 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core" -module \core$282 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$283 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$284 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$285 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute 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\enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$282 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.trial0" -module \trial0$287 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.trial1" -module \trial1$288 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1010000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.pe" -module \pe$289 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core" -module \core$286 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$287 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$288 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$289 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$272 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$273 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_44_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_44_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_44_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_44_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_44_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_44_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_44_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_44_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_44_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_44_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_44_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_44_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_44_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_44_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_44_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_44_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_44_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_44_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_44_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_44_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_44_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_44_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_44_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_44_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_44_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_44_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_44_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_44_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_44_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_44_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_44_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_44_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_44_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_44_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_44_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_44_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_44_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_44_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_44_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_44_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_44_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_44_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_44_compare_rhs$66 - cell \core_calculate_stage_44 \core_calculate_stage_44 - connect \muxid \core_calculate_stage_44_muxid - connect \logical_op__insn_type \core_calculate_stage_44_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_44_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_44_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_44_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_44_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_44_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_44_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_44_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_44_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_44_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_44_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_44_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_44_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_44_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_44_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_44_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_44_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_44_logical_op__insn - connect \ra \core_calculate_stage_44_ra - connect \rb \core_calculate_stage_44_rb - connect \xer_so \core_calculate_stage_44_xer_so - connect \divisor_neg \core_calculate_stage_44_divisor_neg - connect \dividend_neg \core_calculate_stage_44_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_44_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_44_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_44_div_by_zero - connect \divisor_radicand \core_calculate_stage_44_divisor_radicand - connect \operation \core_calculate_stage_44_operation - connect \quotient_root \core_calculate_stage_44_quotient_root - connect \root_times_radicand \core_calculate_stage_44_root_times_radicand - connect \compare_lhs \core_calculate_stage_44_compare_lhs - connect \compare_rhs \core_calculate_stage_44_compare_rhs - connect \muxid$1 \core_calculate_stage_44_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_44_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_44_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_44_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_44_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_44_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_44_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_44_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_44_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_44_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_44_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_44_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_44_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_44_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_44_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_44_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_44_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_44_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_44_ra$53 - connect \rb$21 \core_calculate_stage_44_rb$54 - connect \xer_so$22 \core_calculate_stage_44_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_44_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_44_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_44_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_44_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_44_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_44_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_44_operation$62 - connect \quotient_root$30 \core_calculate_stage_44_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_44_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_44_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_44_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_45_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_45_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_45_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_45_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_45_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_45_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_45_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_45_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_45_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_45_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_45_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_45_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_45_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_45_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_45_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_45_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_45_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_45_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_45_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_45_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_45_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_45_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_45_logical_op__insn_type$68 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_45_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_45_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_45_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_45_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_45_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_45_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_45_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_45_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_45_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_45_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_45_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_45_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_45_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_45_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_45_compare_rhs$99 - cell \core_calculate_stage_45 \core_calculate_stage_45 - connect \muxid \core_calculate_stage_45_muxid - connect \logical_op__insn_type \core_calculate_stage_45_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_45_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_45_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_45_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_45_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_45_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_45_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_45_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_45_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_45_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_45_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_45_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_45_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_45_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_45_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_45_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_45_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_45_logical_op__insn - connect \ra \core_calculate_stage_45_ra - connect \rb \core_calculate_stage_45_rb - connect \xer_so \core_calculate_stage_45_xer_so - connect \divisor_neg \core_calculate_stage_45_divisor_neg - connect \dividend_neg \core_calculate_stage_45_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_45_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_45_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_45_div_by_zero - connect \divisor_radicand \core_calculate_stage_45_divisor_radicand - connect \operation \core_calculate_stage_45_operation - connect \quotient_root \core_calculate_stage_45_quotient_root - connect \root_times_radicand \core_calculate_stage_45_root_times_radicand - connect \compare_lhs \core_calculate_stage_45_compare_lhs - connect \compare_rhs \core_calculate_stage_45_compare_rhs - connect \muxid$1 \core_calculate_stage_45_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_45_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_45_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_45_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_45_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_45_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_45_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_45_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_45_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_45_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_45_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_45_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_45_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_45_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_45_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_45_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_45_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_45_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_45_ra$86 - connect \rb$21 \core_calculate_stage_45_rb$87 - connect \xer_so$22 \core_calculate_stage_45_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_45_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_45_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_45_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_45_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_45_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_45_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_45_operation$95 - connect \quotient_root$30 \core_calculate_stage_45_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_45_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_45_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_45_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_46_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_46_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_46_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_46_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_46_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_46_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_46_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_46_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_46_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_46_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_46_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_46_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_46_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_46_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_46_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_46_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_46_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_46_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_46_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_46_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_46_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_46_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_46_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_46_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_46_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_46_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_46_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_46_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_46_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_46_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_46_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_46_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_46_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_46_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_46_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_46_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_46_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_46_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_46_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_46_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_46_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_46_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_46_compare_rhs$132 - cell \core_calculate_stage_46 \core_calculate_stage_46 - connect \muxid \core_calculate_stage_46_muxid - connect \logical_op__insn_type \core_calculate_stage_46_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_46_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_46_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_46_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_46_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_46_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_46_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_46_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_46_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_46_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_46_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_46_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_46_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_46_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_46_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_46_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_46_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_46_logical_op__insn - connect \ra \core_calculate_stage_46_ra - connect \rb \core_calculate_stage_46_rb - connect \xer_so \core_calculate_stage_46_xer_so - connect \divisor_neg \core_calculate_stage_46_divisor_neg - connect \dividend_neg \core_calculate_stage_46_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_46_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_46_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_46_div_by_zero - connect \divisor_radicand \core_calculate_stage_46_divisor_radicand - connect \operation \core_calculate_stage_46_operation - connect \quotient_root \core_calculate_stage_46_quotient_root - connect \root_times_radicand \core_calculate_stage_46_root_times_radicand - connect \compare_lhs \core_calculate_stage_46_compare_lhs - connect \compare_rhs \core_calculate_stage_46_compare_rhs - connect \muxid$1 \core_calculate_stage_46_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_46_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_46_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_46_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_46_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_46_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_46_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_46_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_46_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_46_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_46_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_46_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_46_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_46_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_46_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_46_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_46_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_46_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_46_ra$119 - connect \rb$21 \core_calculate_stage_46_rb$120 - connect \xer_so$22 \core_calculate_stage_46_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_46_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_46_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_46_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_46_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_46_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_46_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_46_operation$128 - connect \quotient_root$30 \core_calculate_stage_46_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_46_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_46_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_46_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_47_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_47_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_47_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_47_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__zero_a - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_47_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_47_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_47_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_47_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_47_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_47_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_47_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_47_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_47_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_47_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_47_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_47_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_47_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_47_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_47_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_47_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_47_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_47_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_47_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_47_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_47_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_47_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_47_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_47_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_47_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_47_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_47_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_47_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_47_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_47_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_47_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_47_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_47_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_47_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_47_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_47_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_47_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_47_compare_rhs$165 - cell \core_calculate_stage_47 \core_calculate_stage_47 - connect \muxid \core_calculate_stage_47_muxid - connect \logical_op__insn_type \core_calculate_stage_47_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_47_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_47_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_47_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_47_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_47_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_47_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_47_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_47_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_47_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_47_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_47_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_47_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_47_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_47_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_47_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_47_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_47_logical_op__insn - connect \ra \core_calculate_stage_47_ra - connect \rb \core_calculate_stage_47_rb - connect \xer_so \core_calculate_stage_47_xer_so - connect \divisor_neg \core_calculate_stage_47_divisor_neg - connect \dividend_neg \core_calculate_stage_47_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_47_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_47_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_47_div_by_zero - connect \divisor_radicand \core_calculate_stage_47_divisor_radicand - connect \operation \core_calculate_stage_47_operation - connect \quotient_root \core_calculate_stage_47_quotient_root - connect \root_times_radicand \core_calculate_stage_47_root_times_radicand - connect \compare_lhs \core_calculate_stage_47_compare_lhs - connect \compare_rhs \core_calculate_stage_47_compare_rhs - connect \muxid$1 \core_calculate_stage_47_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_47_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_47_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_47_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_47_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_47_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_47_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_47_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_47_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_47_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_47_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_47_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_47_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_47_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_47_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_47_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_47_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_47_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_47_ra$152 - connect \rb$21 \core_calculate_stage_47_rb$153 - connect \xer_so$22 \core_calculate_stage_47_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_47_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_47_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_47_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_47_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_47_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_47_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_47_operation$161 - connect \quotient_root$30 \core_calculate_stage_47_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_47_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_47_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_47_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_44_muxid 2'00 - assign \core_calculate_stage_44_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_44_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_44_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_44_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_44_logical_op__rc__rc 1'0 - assign \core_calculate_stage_44_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_44_logical_op__oe__oe 1'0 - assign \core_calculate_stage_44_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_44_logical_op__invert_in 1'0 - assign \core_calculate_stage_44_logical_op__zero_a 1'0 - assign \core_calculate_stage_44_logical_op__input_carry 2'00 - assign \core_calculate_stage_44_logical_op__invert_out 1'0 - assign \core_calculate_stage_44_logical_op__write_cr0 1'0 - assign \core_calculate_stage_44_logical_op__output_carry 1'0 - assign \core_calculate_stage_44_logical_op__is_32bit 1'0 - assign \core_calculate_stage_44_logical_op__is_signed 1'0 - assign \core_calculate_stage_44_logical_op__data_len 4'0000 - assign \core_calculate_stage_44_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_44_logical_op__insn \core_calculate_stage_44_logical_op__data_len \core_calculate_stage_44_logical_op__is_signed \core_calculate_stage_44_logical_op__is_32bit \core_calculate_stage_44_logical_op__output_carry \core_calculate_stage_44_logical_op__write_cr0 \core_calculate_stage_44_logical_op__invert_out \core_calculate_stage_44_logical_op__input_carry \core_calculate_stage_44_logical_op__zero_a \core_calculate_stage_44_logical_op__invert_in { \core_calculate_stage_44_logical_op__oe__oe_ok \core_calculate_stage_44_logical_op__oe__oe } { \core_calculate_stage_44_logical_op__rc__rc_ok \core_calculate_stage_44_logical_op__rc__rc } { \core_calculate_stage_44_logical_op__imm_data__imm_ok \core_calculate_stage_44_logical_op__imm_data__imm } \core_calculate_stage_44_logical_op__fn_unit \core_calculate_stage_44_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_44_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_44_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_44_xer_so 1'0 - assign \core_calculate_stage_44_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_44_divisor_neg 1'0 - assign \core_calculate_stage_44_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_44_dividend_neg 1'0 - assign \core_calculate_stage_44_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_44_dive_abs_ov32 1'0 - assign \core_calculate_stage_44_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_44_dive_abs_ov64 1'0 - assign \core_calculate_stage_44_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_44_div_by_zero 1'0 - assign \core_calculate_stage_44_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_44_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_44_operation 2'00 - assign \core_calculate_stage_44_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_44_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_44_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_44_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_44_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_44_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_45_muxid 2'00 - assign \core_calculate_stage_45_muxid \core_calculate_stage_44_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_45_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_45_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_45_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_45_logical_op__rc__rc 1'0 - assign \core_calculate_stage_45_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_45_logical_op__oe__oe 1'0 - assign \core_calculate_stage_45_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_45_logical_op__invert_in 1'0 - assign \core_calculate_stage_45_logical_op__zero_a 1'0 - assign \core_calculate_stage_45_logical_op__input_carry 2'00 - assign \core_calculate_stage_45_logical_op__invert_out 1'0 - assign \core_calculate_stage_45_logical_op__write_cr0 1'0 - assign \core_calculate_stage_45_logical_op__output_carry 1'0 - assign \core_calculate_stage_45_logical_op__is_32bit 1'0 - assign \core_calculate_stage_45_logical_op__is_signed 1'0 - assign \core_calculate_stage_45_logical_op__data_len 4'0000 - assign \core_calculate_stage_45_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_45_logical_op__insn \core_calculate_stage_45_logical_op__data_len \core_calculate_stage_45_logical_op__is_signed \core_calculate_stage_45_logical_op__is_32bit \core_calculate_stage_45_logical_op__output_carry \core_calculate_stage_45_logical_op__write_cr0 \core_calculate_stage_45_logical_op__invert_out \core_calculate_stage_45_logical_op__input_carry \core_calculate_stage_45_logical_op__zero_a \core_calculate_stage_45_logical_op__invert_in { \core_calculate_stage_45_logical_op__oe__oe_ok \core_calculate_stage_45_logical_op__oe__oe } { \core_calculate_stage_45_logical_op__rc__rc_ok \core_calculate_stage_45_logical_op__rc__rc } { \core_calculate_stage_45_logical_op__imm_data__imm_ok \core_calculate_stage_45_logical_op__imm_data__imm } \core_calculate_stage_45_logical_op__fn_unit \core_calculate_stage_45_logical_op__insn_type } { \core_calculate_stage_44_logical_op__insn$52 \core_calculate_stage_44_logical_op__data_len$51 \core_calculate_stage_44_logical_op__is_signed$50 \core_calculate_stage_44_logical_op__is_32bit$49 \core_calculate_stage_44_logical_op__output_carry$48 \core_calculate_stage_44_logical_op__write_cr0$47 \core_calculate_stage_44_logical_op__invert_out$46 \core_calculate_stage_44_logical_op__input_carry$45 \core_calculate_stage_44_logical_op__zero_a$44 \core_calculate_stage_44_logical_op__invert_in$43 { \core_calculate_stage_44_logical_op__oe__oe_ok$42 \core_calculate_stage_44_logical_op__oe__oe$41 } { \core_calculate_stage_44_logical_op__rc__rc_ok$40 \core_calculate_stage_44_logical_op__rc__rc$39 } { \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 \core_calculate_stage_44_logical_op__imm_data__imm$37 } \core_calculate_stage_44_logical_op__fn_unit$36 \core_calculate_stage_44_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_45_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_ra \core_calculate_stage_44_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_45_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_rb \core_calculate_stage_44_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_45_xer_so 1'0 - assign \core_calculate_stage_45_xer_so \core_calculate_stage_44_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_45_divisor_neg 1'0 - assign \core_calculate_stage_45_divisor_neg \core_calculate_stage_44_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_45_dividend_neg 1'0 - assign \core_calculate_stage_45_dividend_neg \core_calculate_stage_44_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_45_dive_abs_ov32 1'0 - assign \core_calculate_stage_45_dive_abs_ov32 \core_calculate_stage_44_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_45_dive_abs_ov64 1'0 - assign \core_calculate_stage_45_dive_abs_ov64 \core_calculate_stage_44_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_45_div_by_zero 1'0 - assign \core_calculate_stage_45_div_by_zero \core_calculate_stage_44_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_45_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_divisor_radicand \core_calculate_stage_44_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_45_operation 2'00 - assign \core_calculate_stage_45_operation \core_calculate_stage_44_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_45_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_quotient_root \core_calculate_stage_44_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_45_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_root_times_radicand \core_calculate_stage_44_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_45_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_compare_lhs \core_calculate_stage_44_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_45_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_45_compare_rhs \core_calculate_stage_44_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_46_muxid 2'00 - assign \core_calculate_stage_46_muxid \core_calculate_stage_45_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_46_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_46_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_46_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_46_logical_op__rc__rc 1'0 - assign \core_calculate_stage_46_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_46_logical_op__oe__oe 1'0 - assign \core_calculate_stage_46_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_46_logical_op__invert_in 1'0 - assign \core_calculate_stage_46_logical_op__zero_a 1'0 - assign \core_calculate_stage_46_logical_op__input_carry 2'00 - assign \core_calculate_stage_46_logical_op__invert_out 1'0 - assign \core_calculate_stage_46_logical_op__write_cr0 1'0 - assign \core_calculate_stage_46_logical_op__output_carry 1'0 - assign \core_calculate_stage_46_logical_op__is_32bit 1'0 - assign \core_calculate_stage_46_logical_op__is_signed 1'0 - assign \core_calculate_stage_46_logical_op__data_len 4'0000 - assign \core_calculate_stage_46_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_46_logical_op__insn \core_calculate_stage_46_logical_op__data_len \core_calculate_stage_46_logical_op__is_signed \core_calculate_stage_46_logical_op__is_32bit \core_calculate_stage_46_logical_op__output_carry \core_calculate_stage_46_logical_op__write_cr0 \core_calculate_stage_46_logical_op__invert_out \core_calculate_stage_46_logical_op__input_carry \core_calculate_stage_46_logical_op__zero_a \core_calculate_stage_46_logical_op__invert_in { \core_calculate_stage_46_logical_op__oe__oe_ok \core_calculate_stage_46_logical_op__oe__oe } { \core_calculate_stage_46_logical_op__rc__rc_ok \core_calculate_stage_46_logical_op__rc__rc } { \core_calculate_stage_46_logical_op__imm_data__imm_ok \core_calculate_stage_46_logical_op__imm_data__imm } \core_calculate_stage_46_logical_op__fn_unit \core_calculate_stage_46_logical_op__insn_type } { \core_calculate_stage_45_logical_op__insn$85 \core_calculate_stage_45_logical_op__data_len$84 \core_calculate_stage_45_logical_op__is_signed$83 \core_calculate_stage_45_logical_op__is_32bit$82 \core_calculate_stage_45_logical_op__output_carry$81 \core_calculate_stage_45_logical_op__write_cr0$80 \core_calculate_stage_45_logical_op__invert_out$79 \core_calculate_stage_45_logical_op__input_carry$78 \core_calculate_stage_45_logical_op__zero_a$77 \core_calculate_stage_45_logical_op__invert_in$76 { \core_calculate_stage_45_logical_op__oe__oe_ok$75 \core_calculate_stage_45_logical_op__oe__oe$74 } { \core_calculate_stage_45_logical_op__rc__rc_ok$73 \core_calculate_stage_45_logical_op__rc__rc$72 } { \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 \core_calculate_stage_45_logical_op__imm_data__imm$70 } \core_calculate_stage_45_logical_op__fn_unit$69 \core_calculate_stage_45_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_46_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_ra \core_calculate_stage_45_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_46_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_rb \core_calculate_stage_45_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_46_xer_so 1'0 - assign \core_calculate_stage_46_xer_so \core_calculate_stage_45_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_46_divisor_neg 1'0 - assign \core_calculate_stage_46_divisor_neg \core_calculate_stage_45_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_46_dividend_neg 1'0 - assign \core_calculate_stage_46_dividend_neg \core_calculate_stage_45_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_46_dive_abs_ov32 1'0 - assign \core_calculate_stage_46_dive_abs_ov32 \core_calculate_stage_45_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_46_dive_abs_ov64 1'0 - assign \core_calculate_stage_46_dive_abs_ov64 \core_calculate_stage_45_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_46_div_by_zero 1'0 - assign \core_calculate_stage_46_div_by_zero \core_calculate_stage_45_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_46_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_divisor_radicand \core_calculate_stage_45_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_46_operation 2'00 - assign \core_calculate_stage_46_operation \core_calculate_stage_45_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_46_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_quotient_root \core_calculate_stage_45_quotient_root$96 - sync init - end - process $group_96 - assign \core_calculate_stage_46_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_root_times_radicand \core_calculate_stage_45_root_times_radicand$97 - sync init - end - process $group_97 - assign \core_calculate_stage_46_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_compare_lhs \core_calculate_stage_45_compare_lhs$98 - sync init - end - process $group_98 - assign \core_calculate_stage_46_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_46_compare_rhs \core_calculate_stage_45_compare_rhs$99 - sync init - end - process $group_99 - assign \core_calculate_stage_47_muxid 2'00 - assign \core_calculate_stage_47_muxid \core_calculate_stage_46_muxid$100 - sync init - end - process $group_100 - assign \core_calculate_stage_47_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_47_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_47_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_47_logical_op__rc__rc 1'0 - assign \core_calculate_stage_47_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_47_logical_op__oe__oe 1'0 - assign \core_calculate_stage_47_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_47_logical_op__invert_in 1'0 - assign \core_calculate_stage_47_logical_op__zero_a 1'0 - assign \core_calculate_stage_47_logical_op__input_carry 2'00 - assign \core_calculate_stage_47_logical_op__invert_out 1'0 - assign \core_calculate_stage_47_logical_op__write_cr0 1'0 - assign \core_calculate_stage_47_logical_op__output_carry 1'0 - assign \core_calculate_stage_47_logical_op__is_32bit 1'0 - assign \core_calculate_stage_47_logical_op__is_signed 1'0 - assign \core_calculate_stage_47_logical_op__data_len 4'0000 - assign \core_calculate_stage_47_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_47_logical_op__insn \core_calculate_stage_47_logical_op__data_len \core_calculate_stage_47_logical_op__is_signed \core_calculate_stage_47_logical_op__is_32bit \core_calculate_stage_47_logical_op__output_carry \core_calculate_stage_47_logical_op__write_cr0 \core_calculate_stage_47_logical_op__invert_out \core_calculate_stage_47_logical_op__input_carry \core_calculate_stage_47_logical_op__zero_a \core_calculate_stage_47_logical_op__invert_in { \core_calculate_stage_47_logical_op__oe__oe_ok \core_calculate_stage_47_logical_op__oe__oe } { \core_calculate_stage_47_logical_op__rc__rc_ok \core_calculate_stage_47_logical_op__rc__rc } { \core_calculate_stage_47_logical_op__imm_data__imm_ok \core_calculate_stage_47_logical_op__imm_data__imm } \core_calculate_stage_47_logical_op__fn_unit \core_calculate_stage_47_logical_op__insn_type } { \core_calculate_stage_46_logical_op__insn$118 \core_calculate_stage_46_logical_op__data_len$117 \core_calculate_stage_46_logical_op__is_signed$116 \core_calculate_stage_46_logical_op__is_32bit$115 \core_calculate_stage_46_logical_op__output_carry$114 \core_calculate_stage_46_logical_op__write_cr0$113 \core_calculate_stage_46_logical_op__invert_out$112 \core_calculate_stage_46_logical_op__input_carry$111 \core_calculate_stage_46_logical_op__zero_a$110 \core_calculate_stage_46_logical_op__invert_in$109 { \core_calculate_stage_46_logical_op__oe__oe_ok$108 \core_calculate_stage_46_logical_op__oe__oe$107 } { \core_calculate_stage_46_logical_op__rc__rc_ok$106 \core_calculate_stage_46_logical_op__rc__rc$105 } { \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 \core_calculate_stage_46_logical_op__imm_data__imm$103 } \core_calculate_stage_46_logical_op__fn_unit$102 \core_calculate_stage_46_logical_op__insn_type$101 } - sync init - end - process $group_118 - assign \core_calculate_stage_47_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_ra \core_calculate_stage_46_ra$119 - sync init - end - process $group_119 - assign \core_calculate_stage_47_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_rb \core_calculate_stage_46_rb$120 - sync init - end - process $group_120 - assign \core_calculate_stage_47_xer_so 1'0 - assign \core_calculate_stage_47_xer_so \core_calculate_stage_46_xer_so$121 - sync init - end - process $group_121 - assign \core_calculate_stage_47_divisor_neg 1'0 - assign \core_calculate_stage_47_divisor_neg \core_calculate_stage_46_divisor_neg$122 - sync init - end - process $group_122 - assign \core_calculate_stage_47_dividend_neg 1'0 - assign \core_calculate_stage_47_dividend_neg \core_calculate_stage_46_dividend_neg$123 - sync init - end - process $group_123 - assign \core_calculate_stage_47_dive_abs_ov32 1'0 - assign \core_calculate_stage_47_dive_abs_ov32 \core_calculate_stage_46_dive_abs_ov32$124 - sync init - end - process $group_124 - assign \core_calculate_stage_47_dive_abs_ov64 1'0 - assign \core_calculate_stage_47_dive_abs_ov64 \core_calculate_stage_46_dive_abs_ov64$125 - sync init - end - process $group_125 - assign \core_calculate_stage_47_div_by_zero 1'0 - assign \core_calculate_stage_47_div_by_zero \core_calculate_stage_46_div_by_zero$126 - sync init - end - process $group_126 - assign \core_calculate_stage_47_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_divisor_radicand \core_calculate_stage_46_divisor_radicand$127 - sync init - end - process $group_127 - assign \core_calculate_stage_47_operation 2'00 - assign \core_calculate_stage_47_operation \core_calculate_stage_46_operation$128 - sync init - end - process $group_128 - assign \core_calculate_stage_47_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_quotient_root \core_calculate_stage_46_quotient_root$129 - sync init - end - process $group_129 - assign \core_calculate_stage_47_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_root_times_radicand \core_calculate_stage_46_root_times_radicand$130 - sync init - end - process $group_130 - assign \core_calculate_stage_47_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_compare_lhs \core_calculate_stage_46_compare_lhs$131 - sync init - end - process $group_131 - assign \core_calculate_stage_47_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_47_compare_rhs \core_calculate_stage_46_compare_rhs$132 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$166 - process $group_132 - assign \p_valid_i$166 1'0 - assign \p_valid_i$166 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_133 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_47_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_47_logical_op__insn$151 \core_calculate_stage_47_logical_op__data_len$150 \core_calculate_stage_47_logical_op__is_signed$149 \core_calculate_stage_47_logical_op__is_32bit$148 \core_calculate_stage_47_logical_op__output_carry$147 \core_calculate_stage_47_logical_op__write_cr0$146 \core_calculate_stage_47_logical_op__invert_out$145 \core_calculate_stage_47_logical_op__input_carry$144 \core_calculate_stage_47_logical_op__zero_a$143 \core_calculate_stage_47_logical_op__invert_in$142 { \core_calculate_stage_47_logical_op__oe__oe_ok$141 \core_calculate_stage_47_logical_op__oe__oe$140 } { \core_calculate_stage_47_logical_op__rc__rc_ok$139 \core_calculate_stage_47_logical_op__rc__rc$138 } { \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 \core_calculate_stage_47_logical_op__imm_data__imm$136 } \core_calculate_stage_47_logical_op__fn_unit$135 \core_calculate_stage_47_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_47_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_47_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_47_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_47_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_47_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_47_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_47_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_47_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_47_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_47_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_47_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_47_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_47_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_47_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.p" -module \p$290 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.n" -module \n$291 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.trial0" -module \trial0$293 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.trial1" -module \trial1$294 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.pe" -module \pe$295 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core" -module \core$292 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$293 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$294 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$295 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$292 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.trial0" -module \trial0$297 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.trial1" -module \trial1$298 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.pe" -module \pe$299 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core" -module \core$296 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$297 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$298 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$299 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 16 $30 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$296 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 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\core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.trial0" -module \trial0$301 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.trial1" -module \trial1$302 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.pe" -module \pe$303 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$301 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$302 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$303 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$300 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.trial0" -module \trial0$305 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.trial1" -module \trial1$306 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.pe" -module \pe$307 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core" -module \core$304 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$305 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$306 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$307 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 16 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A \next_bits - connect \B 4'1100 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51" -module \core_calculate_stage_51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$304 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$290 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$291 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_48_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_48_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_48_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_48_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_48_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_48_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_48_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_48_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_48_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_48_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_48_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_48_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_48_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_48_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_48_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_48_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_48_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_48_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_48_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_48_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_48_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_48_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_48_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_48_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_48_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_48_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_48_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_48_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_48_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_48_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_48_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_48_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_48_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_48_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_48_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_48_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_48_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_48_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_48_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_48_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_48_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_48_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_48_compare_rhs$66 - cell \core_calculate_stage_48 \core_calculate_stage_48 - connect \muxid \core_calculate_stage_48_muxid - connect \logical_op__insn_type \core_calculate_stage_48_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_48_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_48_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_48_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_48_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_48_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_48_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_48_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_48_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_48_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_48_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_48_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_48_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_48_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_48_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_48_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_48_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_48_logical_op__insn - connect \ra \core_calculate_stage_48_ra - connect \rb \core_calculate_stage_48_rb - connect \xer_so \core_calculate_stage_48_xer_so - connect \divisor_neg \core_calculate_stage_48_divisor_neg - connect \dividend_neg \core_calculate_stage_48_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_48_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_48_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_48_div_by_zero - connect \divisor_radicand \core_calculate_stage_48_divisor_radicand - connect \operation \core_calculate_stage_48_operation - connect \quotient_root \core_calculate_stage_48_quotient_root - connect \root_times_radicand \core_calculate_stage_48_root_times_radicand - connect \compare_lhs \core_calculate_stage_48_compare_lhs - connect \compare_rhs \core_calculate_stage_48_compare_rhs - connect \muxid$1 \core_calculate_stage_48_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_48_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_48_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_48_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_48_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_48_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_48_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_48_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_48_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_48_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_48_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_48_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_48_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_48_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_48_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_48_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_48_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_48_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_48_ra$53 - connect \rb$21 \core_calculate_stage_48_rb$54 - connect \xer_so$22 \core_calculate_stage_48_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_48_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_48_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_48_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_48_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_48_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_48_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_48_operation$62 - connect \quotient_root$30 \core_calculate_stage_48_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_48_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_48_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_48_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_49_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_49_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_49_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_49_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_49_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_49_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_49_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_49_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_49_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_49_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_49_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_49_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_49_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_49_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_49_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_49_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_49_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_49_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_49_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_49_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_49_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_49_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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11 \core_calculate_stage_49_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_49_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_49_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_49_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_49_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_49_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_49_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_49_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_49_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_49_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_49_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_49_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_49_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_49_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_49_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_49_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_49_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_49_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_49_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_49_compare_rhs$99 - cell \core_calculate_stage_49 \core_calculate_stage_49 - connect \muxid \core_calculate_stage_49_muxid - connect \logical_op__insn_type \core_calculate_stage_49_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_49_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_49_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_49_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_49_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_49_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_49_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_49_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_49_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_49_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_49_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_49_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_49_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_49_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_49_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_49_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_49_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_49_logical_op__insn - connect \ra \core_calculate_stage_49_ra - connect \rb \core_calculate_stage_49_rb - connect \xer_so \core_calculate_stage_49_xer_so - connect \divisor_neg \core_calculate_stage_49_divisor_neg - connect \dividend_neg \core_calculate_stage_49_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_49_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_49_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_49_div_by_zero - connect \divisor_radicand \core_calculate_stage_49_divisor_radicand - connect \operation \core_calculate_stage_49_operation - connect \quotient_root \core_calculate_stage_49_quotient_root - connect \root_times_radicand \core_calculate_stage_49_root_times_radicand - connect \compare_lhs \core_calculate_stage_49_compare_lhs - connect \compare_rhs \core_calculate_stage_49_compare_rhs - connect \muxid$1 \core_calculate_stage_49_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_49_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_49_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_49_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_49_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_49_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_49_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_49_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_49_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_49_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_49_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_49_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_49_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_49_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_49_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_49_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_49_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_49_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_49_ra$86 - connect \rb$21 \core_calculate_stage_49_rb$87 - connect \xer_so$22 \core_calculate_stage_49_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_49_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_49_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_49_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_49_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_49_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_49_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_49_operation$95 - connect \quotient_root$30 \core_calculate_stage_49_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_49_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_49_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_49_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_50_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_50_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_50_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_50_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_50_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_50_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_50_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_50_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_50_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_50_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_50_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_50_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_50_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_50_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_50_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_50_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_50_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_50_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_50_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_50_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_50_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_50_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_50_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_50_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_50_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_50_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_50_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_50_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_50_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_50_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_50_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_50_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_50_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_50_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_50_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_50_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_50_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_50_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_50_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_50_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_50_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_50_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_50_compare_rhs$132 - cell \core_calculate_stage_50 \core_calculate_stage_50 - connect \muxid \core_calculate_stage_50_muxid - connect \logical_op__insn_type \core_calculate_stage_50_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_50_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_50_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_50_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_50_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_50_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_50_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_50_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_50_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_50_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_50_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_50_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_50_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_50_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_50_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_50_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_50_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_50_logical_op__insn - connect \ra \core_calculate_stage_50_ra - connect \rb \core_calculate_stage_50_rb - connect \xer_so \core_calculate_stage_50_xer_so - connect \divisor_neg \core_calculate_stage_50_divisor_neg - connect \dividend_neg \core_calculate_stage_50_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_50_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_50_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_50_div_by_zero - connect \divisor_radicand \core_calculate_stage_50_divisor_radicand - connect \operation \core_calculate_stage_50_operation - connect \quotient_root \core_calculate_stage_50_quotient_root - connect \root_times_radicand \core_calculate_stage_50_root_times_radicand - connect \compare_lhs \core_calculate_stage_50_compare_lhs - connect \compare_rhs \core_calculate_stage_50_compare_rhs - connect \muxid$1 \core_calculate_stage_50_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_50_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_50_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_50_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_50_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_50_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_50_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_50_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_50_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_50_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_50_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_50_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_50_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_50_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_50_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_50_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_50_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_50_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_50_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_50_ra$119 - connect \rb$21 \core_calculate_stage_50_rb$120 - connect \xer_so$22 \core_calculate_stage_50_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_50_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_50_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_50_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_50_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_50_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_50_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_50_operation$128 - connect \quotient_root$30 \core_calculate_stage_50_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_50_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_50_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_50_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_51_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_51_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_51_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_51_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_51_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_51_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_51_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_51_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_51_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_51_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_51_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_51_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_51_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_51_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_51_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_51_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_51_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_51_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_51_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_51_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_51_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_51_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_51_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_51_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_51_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_51_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_51_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_51_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_51_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_51_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_51_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_51_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_51_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_51_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_51_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_51_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_51_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_51_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_51_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_51_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_51_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_51_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_51_compare_rhs$165 - cell \core_calculate_stage_51 \core_calculate_stage_51 - connect \muxid \core_calculate_stage_51_muxid - connect \logical_op__insn_type \core_calculate_stage_51_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_51_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_51_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_51_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_51_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_51_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_51_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_51_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_51_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_51_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_51_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_51_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_51_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_51_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_51_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_51_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_51_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_51_logical_op__insn - connect \ra \core_calculate_stage_51_ra - connect \rb \core_calculate_stage_51_rb - connect \xer_so \core_calculate_stage_51_xer_so - connect \divisor_neg \core_calculate_stage_51_divisor_neg - connect \dividend_neg \core_calculate_stage_51_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_51_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_51_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_51_div_by_zero - connect \divisor_radicand \core_calculate_stage_51_divisor_radicand - connect \operation \core_calculate_stage_51_operation - connect \quotient_root \core_calculate_stage_51_quotient_root - connect \root_times_radicand \core_calculate_stage_51_root_times_radicand - connect \compare_lhs \core_calculate_stage_51_compare_lhs - connect \compare_rhs \core_calculate_stage_51_compare_rhs - connect \muxid$1 \core_calculate_stage_51_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_51_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_51_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_51_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_51_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_51_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_51_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_51_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_51_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_51_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_51_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_51_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_51_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_51_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_51_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_51_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_51_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_51_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_51_ra$152 - connect \rb$21 \core_calculate_stage_51_rb$153 - connect \xer_so$22 \core_calculate_stage_51_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_51_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_51_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_51_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_51_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_51_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_51_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_51_operation$161 - connect \quotient_root$30 \core_calculate_stage_51_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_51_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_51_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_51_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_48_muxid 2'00 - assign \core_calculate_stage_48_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_48_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_48_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_48_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_48_logical_op__rc__rc 1'0 - assign \core_calculate_stage_48_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_48_logical_op__oe__oe 1'0 - assign \core_calculate_stage_48_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_48_logical_op__invert_in 1'0 - assign \core_calculate_stage_48_logical_op__zero_a 1'0 - assign \core_calculate_stage_48_logical_op__input_carry 2'00 - assign \core_calculate_stage_48_logical_op__invert_out 1'0 - assign \core_calculate_stage_48_logical_op__write_cr0 1'0 - assign \core_calculate_stage_48_logical_op__output_carry 1'0 - assign \core_calculate_stage_48_logical_op__is_32bit 1'0 - assign \core_calculate_stage_48_logical_op__is_signed 1'0 - assign \core_calculate_stage_48_logical_op__data_len 4'0000 - assign \core_calculate_stage_48_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_48_logical_op__insn \core_calculate_stage_48_logical_op__data_len \core_calculate_stage_48_logical_op__is_signed \core_calculate_stage_48_logical_op__is_32bit \core_calculate_stage_48_logical_op__output_carry \core_calculate_stage_48_logical_op__write_cr0 \core_calculate_stage_48_logical_op__invert_out \core_calculate_stage_48_logical_op__input_carry \core_calculate_stage_48_logical_op__zero_a \core_calculate_stage_48_logical_op__invert_in { \core_calculate_stage_48_logical_op__oe__oe_ok \core_calculate_stage_48_logical_op__oe__oe } { \core_calculate_stage_48_logical_op__rc__rc_ok \core_calculate_stage_48_logical_op__rc__rc } { \core_calculate_stage_48_logical_op__imm_data__imm_ok \core_calculate_stage_48_logical_op__imm_data__imm } \core_calculate_stage_48_logical_op__fn_unit \core_calculate_stage_48_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_48_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_48_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_48_xer_so 1'0 - assign \core_calculate_stage_48_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_48_divisor_neg 1'0 - assign \core_calculate_stage_48_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_48_dividend_neg 1'0 - assign \core_calculate_stage_48_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_48_dive_abs_ov32 1'0 - assign \core_calculate_stage_48_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_48_dive_abs_ov64 1'0 - assign \core_calculate_stage_48_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_48_div_by_zero 1'0 - assign \core_calculate_stage_48_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_48_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_48_operation 2'00 - assign \core_calculate_stage_48_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_48_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_48_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_48_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_48_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_48_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_49_muxid 2'00 - assign \core_calculate_stage_49_muxid \core_calculate_stage_48_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_49_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_49_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_49_logical_op__imm_data__imm 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- assign { \core_calculate_stage_49_logical_op__insn \core_calculate_stage_49_logical_op__data_len \core_calculate_stage_49_logical_op__is_signed \core_calculate_stage_49_logical_op__is_32bit \core_calculate_stage_49_logical_op__output_carry \core_calculate_stage_49_logical_op__write_cr0 \core_calculate_stage_49_logical_op__invert_out \core_calculate_stage_49_logical_op__input_carry \core_calculate_stage_49_logical_op__zero_a \core_calculate_stage_49_logical_op__invert_in { \core_calculate_stage_49_logical_op__oe__oe_ok \core_calculate_stage_49_logical_op__oe__oe } { \core_calculate_stage_49_logical_op__rc__rc_ok \core_calculate_stage_49_logical_op__rc__rc } { \core_calculate_stage_49_logical_op__imm_data__imm_ok \core_calculate_stage_49_logical_op__imm_data__imm } \core_calculate_stage_49_logical_op__fn_unit \core_calculate_stage_49_logical_op__insn_type } { \core_calculate_stage_48_logical_op__insn$52 \core_calculate_stage_48_logical_op__data_len$51 \core_calculate_stage_48_logical_op__is_signed$50 \core_calculate_stage_48_logical_op__is_32bit$49 \core_calculate_stage_48_logical_op__output_carry$48 \core_calculate_stage_48_logical_op__write_cr0$47 \core_calculate_stage_48_logical_op__invert_out$46 \core_calculate_stage_48_logical_op__input_carry$45 \core_calculate_stage_48_logical_op__zero_a$44 \core_calculate_stage_48_logical_op__invert_in$43 { \core_calculate_stage_48_logical_op__oe__oe_ok$42 \core_calculate_stage_48_logical_op__oe__oe$41 } { \core_calculate_stage_48_logical_op__rc__rc_ok$40 \core_calculate_stage_48_logical_op__rc__rc$39 } { \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 \core_calculate_stage_48_logical_op__imm_data__imm$37 } \core_calculate_stage_48_logical_op__fn_unit$36 \core_calculate_stage_48_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_49_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_49_ra \core_calculate_stage_48_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_49_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_49_rb \core_calculate_stage_48_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_49_xer_so 1'0 - assign \core_calculate_stage_49_xer_so \core_calculate_stage_48_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_49_divisor_neg 1'0 - assign \core_calculate_stage_49_divisor_neg \core_calculate_stage_48_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_49_dividend_neg 1'0 - assign \core_calculate_stage_49_dividend_neg \core_calculate_stage_48_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_49_dive_abs_ov32 1'0 - assign \core_calculate_stage_49_dive_abs_ov32 \core_calculate_stage_48_dive_abs_ov32$58 - sync init - end - process $group_58 - assign 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$group_63 - assign \core_calculate_stage_49_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_49_root_times_radicand \core_calculate_stage_48_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_49_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_49_compare_lhs \core_calculate_stage_48_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_49_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_49_compare_rhs \core_calculate_stage_48_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_50_muxid 2'00 - assign \core_calculate_stage_50_muxid \core_calculate_stage_49_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_50_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_50_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_50_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_50_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_50_logical_op__rc__rc 1'0 - assign \core_calculate_stage_50_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_50_logical_op__oe__oe 1'0 - assign \core_calculate_stage_50_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_50_logical_op__invert_in 1'0 - assign \core_calculate_stage_50_logical_op__zero_a 1'0 - assign \core_calculate_stage_50_logical_op__input_carry 2'00 - assign \core_calculate_stage_50_logical_op__invert_out 1'0 - assign \core_calculate_stage_50_logical_op__write_cr0 1'0 - assign \core_calculate_stage_50_logical_op__output_carry 1'0 - assign \core_calculate_stage_50_logical_op__is_32bit 1'0 - assign \core_calculate_stage_50_logical_op__is_signed 1'0 - assign \core_calculate_stage_50_logical_op__data_len 4'0000 - assign \core_calculate_stage_50_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_50_logical_op__insn \core_calculate_stage_50_logical_op__data_len \core_calculate_stage_50_logical_op__is_signed \core_calculate_stage_50_logical_op__is_32bit \core_calculate_stage_50_logical_op__output_carry \core_calculate_stage_50_logical_op__write_cr0 \core_calculate_stage_50_logical_op__invert_out \core_calculate_stage_50_logical_op__input_carry \core_calculate_stage_50_logical_op__zero_a \core_calculate_stage_50_logical_op__invert_in { \core_calculate_stage_50_logical_op__oe__oe_ok \core_calculate_stage_50_logical_op__oe__oe } { \core_calculate_stage_50_logical_op__rc__rc_ok \core_calculate_stage_50_logical_op__rc__rc } { \core_calculate_stage_50_logical_op__imm_data__imm_ok \core_calculate_stage_50_logical_op__imm_data__imm } \core_calculate_stage_50_logical_op__fn_unit \core_calculate_stage_50_logical_op__insn_type } { \core_calculate_stage_49_logical_op__insn$85 \core_calculate_stage_49_logical_op__data_len$84 \core_calculate_stage_49_logical_op__is_signed$83 \core_calculate_stage_49_logical_op__is_32bit$82 \core_calculate_stage_49_logical_op__output_carry$81 \core_calculate_stage_49_logical_op__write_cr0$80 \core_calculate_stage_49_logical_op__invert_out$79 \core_calculate_stage_49_logical_op__input_carry$78 \core_calculate_stage_49_logical_op__zero_a$77 \core_calculate_stage_49_logical_op__invert_in$76 { \core_calculate_stage_49_logical_op__oe__oe_ok$75 \core_calculate_stage_49_logical_op__oe__oe$74 } { \core_calculate_stage_49_logical_op__rc__rc_ok$73 \core_calculate_stage_49_logical_op__rc__rc$72 } { \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 \core_calculate_stage_49_logical_op__imm_data__imm$70 } \core_calculate_stage_49_logical_op__fn_unit$69 \core_calculate_stage_49_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_50_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_50_ra \core_calculate_stage_49_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_50_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_50_rb \core_calculate_stage_49_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_50_xer_so 1'0 - assign \core_calculate_stage_50_xer_so \core_calculate_stage_49_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_50_divisor_neg 1'0 - assign \core_calculate_stage_50_divisor_neg \core_calculate_stage_49_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_50_dividend_neg 1'0 - assign \core_calculate_stage_50_dividend_neg \core_calculate_stage_49_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_50_dive_abs_ov32 1'0 - assign \core_calculate_stage_50_dive_abs_ov32 \core_calculate_stage_49_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_50_dive_abs_ov64 1'0 - assign \core_calculate_stage_50_dive_abs_ov64 \core_calculate_stage_49_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_50_div_by_zero 1'0 - assign \core_calculate_stage_50_div_by_zero \core_calculate_stage_49_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_50_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_50_divisor_radicand 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\core_calculate_stage_51_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_51_logical_op__insn \core_calculate_stage_51_logical_op__data_len \core_calculate_stage_51_logical_op__is_signed \core_calculate_stage_51_logical_op__is_32bit \core_calculate_stage_51_logical_op__output_carry \core_calculate_stage_51_logical_op__write_cr0 \core_calculate_stage_51_logical_op__invert_out \core_calculate_stage_51_logical_op__input_carry \core_calculate_stage_51_logical_op__zero_a \core_calculate_stage_51_logical_op__invert_in { \core_calculate_stage_51_logical_op__oe__oe_ok \core_calculate_stage_51_logical_op__oe__oe } { \core_calculate_stage_51_logical_op__rc__rc_ok \core_calculate_stage_51_logical_op__rc__rc } { \core_calculate_stage_51_logical_op__imm_data__imm_ok \core_calculate_stage_51_logical_op__imm_data__imm } \core_calculate_stage_51_logical_op__fn_unit \core_calculate_stage_51_logical_op__insn_type } { \core_calculate_stage_50_logical_op__insn$118 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\enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_51_logical_op__insn$151 \core_calculate_stage_51_logical_op__data_len$150 \core_calculate_stage_51_logical_op__is_signed$149 \core_calculate_stage_51_logical_op__is_32bit$148 \core_calculate_stage_51_logical_op__output_carry$147 \core_calculate_stage_51_logical_op__write_cr0$146 \core_calculate_stage_51_logical_op__invert_out$145 \core_calculate_stage_51_logical_op__input_carry$144 \core_calculate_stage_51_logical_op__zero_a$143 \core_calculate_stage_51_logical_op__invert_in$142 { \core_calculate_stage_51_logical_op__oe__oe_ok$141 \core_calculate_stage_51_logical_op__oe__oe$140 } { \core_calculate_stage_51_logical_op__rc__rc_ok$139 \core_calculate_stage_51_logical_op__rc__rc$138 } { \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 \core_calculate_stage_51_logical_op__imm_data__imm$136 } \core_calculate_stage_51_logical_op__fn_unit$135 \core_calculate_stage_51_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_51_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_51_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_51_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_51_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_51_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_51_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_51_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_51_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_51_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_51_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_51_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_51_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_51_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_51_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.p" -module \p$308 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.n" -module \n$309 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.trial0" -module \trial0$311 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.trial1" -module \trial1$312 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.pe" -module \pe$313 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core" -module \core$310 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$311 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$312 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$313 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 16 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A \next_bits - connect \B 4'1011 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52" -module \core_calculate_stage_52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$310 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.trial0" -module \trial0$315 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src 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1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.trial1" -module \trial1$316 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.pe" -module \pe$317 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core" -module \core$314 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$315 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$316 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$317 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 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\A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$314 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.trial0" -module \trial0$319 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.trial1" -module \trial1$320 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.pe" -module \pe$321 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core" -module \core$318 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$319 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$320 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$321 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 16 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A \next_bits - connect \B 4'1001 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$318 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.trial0" -module \trial0$323 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.trial1" -module \trial1$324 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1001000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.pe" -module \pe$325 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core" -module \core$322 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$323 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$324 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$325 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$322 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13" -module \pipe_middle_13 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute 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"ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$308 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$309 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_52_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_52_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_52_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_52_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_52_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_52_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_52_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_52_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_52_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_52_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_52_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_52_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_52_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_52_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_52_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_52_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_52_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_52_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_52_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_52_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_52_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_52_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_52_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_52_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_52_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_52_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_52_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_52_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_52_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_52_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_52_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_52_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_52_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_52_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_52_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_52_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_52_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_52_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_52_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_52_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_52_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_52_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_52_compare_rhs$66 - cell \core_calculate_stage_52 \core_calculate_stage_52 - connect \muxid \core_calculate_stage_52_muxid - connect \logical_op__insn_type \core_calculate_stage_52_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_52_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_52_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_52_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_52_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_52_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_52_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_52_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_52_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_52_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_52_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_52_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_52_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_52_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_52_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_52_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_52_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_52_logical_op__insn - connect \ra \core_calculate_stage_52_ra - connect \rb \core_calculate_stage_52_rb - connect \xer_so \core_calculate_stage_52_xer_so - connect \divisor_neg \core_calculate_stage_52_divisor_neg - connect \dividend_neg \core_calculate_stage_52_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_52_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_52_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_52_div_by_zero - connect \divisor_radicand \core_calculate_stage_52_divisor_radicand - connect \operation \core_calculate_stage_52_operation - connect \quotient_root \core_calculate_stage_52_quotient_root - connect \root_times_radicand \core_calculate_stage_52_root_times_radicand - connect \compare_lhs \core_calculate_stage_52_compare_lhs - connect \compare_rhs \core_calculate_stage_52_compare_rhs - connect \muxid$1 \core_calculate_stage_52_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_52_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_52_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_52_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_52_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_52_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_52_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_52_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_52_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_52_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_52_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_52_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_52_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_52_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_52_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_52_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_52_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_52_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_52_ra$53 - connect \rb$21 \core_calculate_stage_52_rb$54 - connect \xer_so$22 \core_calculate_stage_52_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_52_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_52_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_52_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_52_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_52_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_52_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_52_operation$62 - connect \quotient_root$30 \core_calculate_stage_52_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_52_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_52_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_52_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_53_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_53_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_53_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_53_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_53_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_53_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_53_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_53_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_53_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_53_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_53_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_53_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_53_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_53_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_53_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_53_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_53_logical_op__insn_type$68 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_53_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_53_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_53_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_53_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_53_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_53_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_53_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_53_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_53_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_53_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_53_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_53_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_53_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_53_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_53_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_53_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_53_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_53_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_53_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_53_compare_rhs$99 - cell \core_calculate_stage_53 \core_calculate_stage_53 - connect \muxid \core_calculate_stage_53_muxid - connect \logical_op__insn_type \core_calculate_stage_53_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_53_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_53_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_53_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_53_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_53_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_53_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_53_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_53_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_53_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_53_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_53_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_53_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_53_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_53_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_53_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_53_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_53_logical_op__insn - connect \ra \core_calculate_stage_53_ra - connect \rb \core_calculate_stage_53_rb - connect \xer_so \core_calculate_stage_53_xer_so - connect \divisor_neg \core_calculate_stage_53_divisor_neg - connect \dividend_neg \core_calculate_stage_53_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_53_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_53_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_53_div_by_zero - connect \divisor_radicand \core_calculate_stage_53_divisor_radicand - connect \operation \core_calculate_stage_53_operation - connect \quotient_root \core_calculate_stage_53_quotient_root - connect \root_times_radicand \core_calculate_stage_53_root_times_radicand - connect \compare_lhs \core_calculate_stage_53_compare_lhs - connect \compare_rhs \core_calculate_stage_53_compare_rhs - connect \muxid$1 \core_calculate_stage_53_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_53_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_53_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_53_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_53_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_53_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_53_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_53_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_53_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_53_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_53_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_53_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_53_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_53_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_53_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_53_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_53_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_53_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_53_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_53_ra$86 - connect \rb$21 \core_calculate_stage_53_rb$87 - connect \xer_so$22 \core_calculate_stage_53_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_53_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_53_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_53_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_53_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_53_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_53_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_53_operation$95 - connect \quotient_root$30 \core_calculate_stage_53_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_53_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_53_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_53_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_54_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_54_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_54_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_54_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_54_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_54_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_54_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_54_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_54_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_54_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_54_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_54_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_54_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_54_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_54_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_54_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_54_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_54_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_54_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_54_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_54_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_54_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_54_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_54_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_54_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_54_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_54_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_54_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_54_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_54_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_54_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_54_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_54_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_54_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_54_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_54_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_54_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_54_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_54_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_54_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_54_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_54_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_54_compare_rhs$132 - cell \core_calculate_stage_54 \core_calculate_stage_54 - connect \muxid \core_calculate_stage_54_muxid - connect \logical_op__insn_type \core_calculate_stage_54_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_54_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_54_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_54_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_54_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_54_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_54_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_54_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_54_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_54_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_54_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_54_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_54_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_54_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_54_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_54_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_54_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_54_logical_op__insn - connect \ra \core_calculate_stage_54_ra - connect \rb \core_calculate_stage_54_rb - connect \xer_so \core_calculate_stage_54_xer_so - connect \divisor_neg \core_calculate_stage_54_divisor_neg - connect \dividend_neg \core_calculate_stage_54_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_54_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_54_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_54_div_by_zero - connect \divisor_radicand \core_calculate_stage_54_divisor_radicand - connect \operation \core_calculate_stage_54_operation - connect \quotient_root \core_calculate_stage_54_quotient_root - connect \root_times_radicand \core_calculate_stage_54_root_times_radicand - connect \compare_lhs \core_calculate_stage_54_compare_lhs - connect \compare_rhs \core_calculate_stage_54_compare_rhs - connect \muxid$1 \core_calculate_stage_54_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_54_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_54_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_54_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_54_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_54_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_54_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_54_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_54_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_54_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_54_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_54_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_54_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_54_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_54_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_54_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_54_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_54_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_54_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_54_ra$119 - connect \rb$21 \core_calculate_stage_54_rb$120 - connect \xer_so$22 \core_calculate_stage_54_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_54_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_54_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_54_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_54_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_54_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_54_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_54_operation$128 - connect \quotient_root$30 \core_calculate_stage_54_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_54_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_54_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_54_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_55_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_55_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_55_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_55_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__zero_a - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_55_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_55_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_55_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_55_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_55_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_55_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_55_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_55_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_55_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_55_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_55_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_55_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_55_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_55_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_55_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_55_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_55_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_55_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_55_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_55_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_55_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_55_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_55_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_55_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_55_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_55_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_55_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_55_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_55_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_55_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_55_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_55_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_55_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_55_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_55_compare_rhs$165 - cell \core_calculate_stage_55 \core_calculate_stage_55 - connect \muxid \core_calculate_stage_55_muxid - connect \logical_op__insn_type \core_calculate_stage_55_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_55_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_55_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_55_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_55_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_55_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_55_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_55_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_55_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_55_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_55_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_55_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_55_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_55_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_55_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_55_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_55_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_55_logical_op__insn - connect \ra \core_calculate_stage_55_ra - connect \rb \core_calculate_stage_55_rb - connect \xer_so \core_calculate_stage_55_xer_so - connect \divisor_neg \core_calculate_stage_55_divisor_neg - connect \dividend_neg \core_calculate_stage_55_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_55_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_55_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_55_div_by_zero - connect \divisor_radicand \core_calculate_stage_55_divisor_radicand - connect \operation \core_calculate_stage_55_operation - connect \quotient_root \core_calculate_stage_55_quotient_root - connect \root_times_radicand \core_calculate_stage_55_root_times_radicand - connect \compare_lhs \core_calculate_stage_55_compare_lhs - connect \compare_rhs \core_calculate_stage_55_compare_rhs - connect \muxid$1 \core_calculate_stage_55_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_55_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_55_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_55_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_55_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_55_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_55_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_55_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_55_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_55_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_55_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_55_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_55_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_55_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_55_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_55_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_55_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_55_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_55_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_55_ra$152 - connect \rb$21 \core_calculate_stage_55_rb$153 - connect \xer_so$22 \core_calculate_stage_55_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_55_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_55_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_55_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_55_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_55_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_55_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_55_operation$161 - connect \quotient_root$30 \core_calculate_stage_55_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_55_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_55_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_55_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_52_muxid 2'00 - assign \core_calculate_stage_52_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_52_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_52_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_52_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_52_logical_op__rc__rc 1'0 - assign \core_calculate_stage_52_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_52_logical_op__oe__oe 1'0 - assign \core_calculate_stage_52_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_52_logical_op__invert_in 1'0 - assign \core_calculate_stage_52_logical_op__zero_a 1'0 - assign \core_calculate_stage_52_logical_op__input_carry 2'00 - assign \core_calculate_stage_52_logical_op__invert_out 1'0 - assign \core_calculate_stage_52_logical_op__write_cr0 1'0 - assign \core_calculate_stage_52_logical_op__output_carry 1'0 - assign \core_calculate_stage_52_logical_op__is_32bit 1'0 - assign \core_calculate_stage_52_logical_op__is_signed 1'0 - assign \core_calculate_stage_52_logical_op__data_len 4'0000 - assign \core_calculate_stage_52_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_52_logical_op__insn \core_calculate_stage_52_logical_op__data_len \core_calculate_stage_52_logical_op__is_signed \core_calculate_stage_52_logical_op__is_32bit \core_calculate_stage_52_logical_op__output_carry \core_calculate_stage_52_logical_op__write_cr0 \core_calculate_stage_52_logical_op__invert_out \core_calculate_stage_52_logical_op__input_carry \core_calculate_stage_52_logical_op__zero_a \core_calculate_stage_52_logical_op__invert_in { \core_calculate_stage_52_logical_op__oe__oe_ok \core_calculate_stage_52_logical_op__oe__oe } { \core_calculate_stage_52_logical_op__rc__rc_ok \core_calculate_stage_52_logical_op__rc__rc } { \core_calculate_stage_52_logical_op__imm_data__imm_ok \core_calculate_stage_52_logical_op__imm_data__imm } \core_calculate_stage_52_logical_op__fn_unit \core_calculate_stage_52_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_52_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_52_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_52_xer_so 1'0 - assign \core_calculate_stage_52_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_52_divisor_neg 1'0 - assign \core_calculate_stage_52_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_52_dividend_neg 1'0 - assign \core_calculate_stage_52_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_52_dive_abs_ov32 1'0 - assign \core_calculate_stage_52_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_52_dive_abs_ov64 1'0 - assign \core_calculate_stage_52_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_52_div_by_zero 1'0 - assign \core_calculate_stage_52_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_52_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_52_operation 2'00 - assign \core_calculate_stage_52_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_52_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_52_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_52_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_52_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_52_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_53_muxid 2'00 - assign \core_calculate_stage_53_muxid \core_calculate_stage_52_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_53_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_53_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_53_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_53_logical_op__rc__rc 1'0 - assign \core_calculate_stage_53_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_53_logical_op__oe__oe 1'0 - assign \core_calculate_stage_53_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_53_logical_op__invert_in 1'0 - assign \core_calculate_stage_53_logical_op__zero_a 1'0 - assign \core_calculate_stage_53_logical_op__input_carry 2'00 - assign \core_calculate_stage_53_logical_op__invert_out 1'0 - assign \core_calculate_stage_53_logical_op__write_cr0 1'0 - assign \core_calculate_stage_53_logical_op__output_carry 1'0 - assign \core_calculate_stage_53_logical_op__is_32bit 1'0 - assign \core_calculate_stage_53_logical_op__is_signed 1'0 - assign \core_calculate_stage_53_logical_op__data_len 4'0000 - assign \core_calculate_stage_53_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_53_logical_op__insn \core_calculate_stage_53_logical_op__data_len \core_calculate_stage_53_logical_op__is_signed \core_calculate_stage_53_logical_op__is_32bit \core_calculate_stage_53_logical_op__output_carry \core_calculate_stage_53_logical_op__write_cr0 \core_calculate_stage_53_logical_op__invert_out \core_calculate_stage_53_logical_op__input_carry \core_calculate_stage_53_logical_op__zero_a \core_calculate_stage_53_logical_op__invert_in { \core_calculate_stage_53_logical_op__oe__oe_ok \core_calculate_stage_53_logical_op__oe__oe } { \core_calculate_stage_53_logical_op__rc__rc_ok \core_calculate_stage_53_logical_op__rc__rc } { \core_calculate_stage_53_logical_op__imm_data__imm_ok \core_calculate_stage_53_logical_op__imm_data__imm } \core_calculate_stage_53_logical_op__fn_unit \core_calculate_stage_53_logical_op__insn_type } { \core_calculate_stage_52_logical_op__insn$52 \core_calculate_stage_52_logical_op__data_len$51 \core_calculate_stage_52_logical_op__is_signed$50 \core_calculate_stage_52_logical_op__is_32bit$49 \core_calculate_stage_52_logical_op__output_carry$48 \core_calculate_stage_52_logical_op__write_cr0$47 \core_calculate_stage_52_logical_op__invert_out$46 \core_calculate_stage_52_logical_op__input_carry$45 \core_calculate_stage_52_logical_op__zero_a$44 \core_calculate_stage_52_logical_op__invert_in$43 { \core_calculate_stage_52_logical_op__oe__oe_ok$42 \core_calculate_stage_52_logical_op__oe__oe$41 } { \core_calculate_stage_52_logical_op__rc__rc_ok$40 \core_calculate_stage_52_logical_op__rc__rc$39 } { \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 \core_calculate_stage_52_logical_op__imm_data__imm$37 } \core_calculate_stage_52_logical_op__fn_unit$36 \core_calculate_stage_52_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_53_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_ra \core_calculate_stage_52_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_53_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_rb \core_calculate_stage_52_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_53_xer_so 1'0 - assign \core_calculate_stage_53_xer_so \core_calculate_stage_52_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_53_divisor_neg 1'0 - assign \core_calculate_stage_53_divisor_neg \core_calculate_stage_52_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_53_dividend_neg 1'0 - assign \core_calculate_stage_53_dividend_neg \core_calculate_stage_52_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_53_dive_abs_ov32 1'0 - assign \core_calculate_stage_53_dive_abs_ov32 \core_calculate_stage_52_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_53_dive_abs_ov64 1'0 - assign \core_calculate_stage_53_dive_abs_ov64 \core_calculate_stage_52_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_53_div_by_zero 1'0 - assign \core_calculate_stage_53_div_by_zero \core_calculate_stage_52_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_53_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_divisor_radicand \core_calculate_stage_52_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_53_operation 2'00 - assign \core_calculate_stage_53_operation \core_calculate_stage_52_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_53_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_quotient_root \core_calculate_stage_52_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_53_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_root_times_radicand \core_calculate_stage_52_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_53_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_compare_lhs \core_calculate_stage_52_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_53_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_53_compare_rhs \core_calculate_stage_52_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_54_muxid 2'00 - assign \core_calculate_stage_54_muxid \core_calculate_stage_53_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_54_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_54_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_54_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_54_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_54_logical_op__rc__rc 1'0 - assign \core_calculate_stage_54_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_54_logical_op__oe__oe 1'0 - assign \core_calculate_stage_54_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_54_logical_op__invert_in 1'0 - assign \core_calculate_stage_54_logical_op__zero_a 1'0 - assign \core_calculate_stage_54_logical_op__input_carry 2'00 - assign \core_calculate_stage_54_logical_op__invert_out 1'0 - assign \core_calculate_stage_54_logical_op__write_cr0 1'0 - assign \core_calculate_stage_54_logical_op__output_carry 1'0 - assign \core_calculate_stage_54_logical_op__is_32bit 1'0 - assign \core_calculate_stage_54_logical_op__is_signed 1'0 - assign \core_calculate_stage_54_logical_op__data_len 4'0000 - assign \core_calculate_stage_54_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_54_logical_op__insn \core_calculate_stage_54_logical_op__data_len \core_calculate_stage_54_logical_op__is_signed \core_calculate_stage_54_logical_op__is_32bit \core_calculate_stage_54_logical_op__output_carry \core_calculate_stage_54_logical_op__write_cr0 \core_calculate_stage_54_logical_op__invert_out \core_calculate_stage_54_logical_op__input_carry \core_calculate_stage_54_logical_op__zero_a \core_calculate_stage_54_logical_op__invert_in { \core_calculate_stage_54_logical_op__oe__oe_ok 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\logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_55_logical_op__insn$151 \core_calculate_stage_55_logical_op__data_len$150 \core_calculate_stage_55_logical_op__is_signed$149 \core_calculate_stage_55_logical_op__is_32bit$148 \core_calculate_stage_55_logical_op__output_carry$147 \core_calculate_stage_55_logical_op__write_cr0$146 \core_calculate_stage_55_logical_op__invert_out$145 \core_calculate_stage_55_logical_op__input_carry$144 \core_calculate_stage_55_logical_op__zero_a$143 \core_calculate_stage_55_logical_op__invert_in$142 { \core_calculate_stage_55_logical_op__oe__oe_ok$141 \core_calculate_stage_55_logical_op__oe__oe$140 } { \core_calculate_stage_55_logical_op__rc__rc_ok$139 \core_calculate_stage_55_logical_op__rc__rc$138 } { \core_calculate_stage_55_logical_op__imm_data__imm_ok$137 \core_calculate_stage_55_logical_op__imm_data__imm$136 } \core_calculate_stage_55_logical_op__fn_unit$135 \core_calculate_stage_55_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_55_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_55_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_55_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_55_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_55_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_55_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_55_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_55_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_55_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_55_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_55_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_55_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_55_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_55_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.p" -module \p$326 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.n" -module \n$327 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.trial0" -module \trial0$329 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.trial1" -module \trial1$330 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000111 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.pe" -module \pe$331 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core" -module \core$328 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$329 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$330 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$331 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$328 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.trial0" -module \trial0$333 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.trial1" -module \trial1$334 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000110 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.pe" -module \pe$335 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core" -module \core$332 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$333 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$334 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$335 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$332 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.trial0" -module \trial0$337 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.trial1" -module \trial1$338 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000101 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.pe" -module \pe$339 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core" -module \core$336 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$337 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$338 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$339 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute 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attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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\enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$336 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.trial0" -module \trial0$341 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.trial1" -module \trial1$342 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000100 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.pe" -module \pe$343 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core" -module \core$340 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$341 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$342 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$343 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 58 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 59 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$326 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$327 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_56_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_56_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_56_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_56_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_56_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_56_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_56_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_56_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_56_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_56_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_56_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_56_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_56_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_56_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_56_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_56_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_56_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_56_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_56_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_56_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_56_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_56_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_56_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_56_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_56_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_56_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_56_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_56_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_56_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_56_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_56_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_56_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_56_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_56_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_56_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_56_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_56_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_56_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_56_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_56_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_56_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_56_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_56_compare_rhs$66 - cell \core_calculate_stage_56 \core_calculate_stage_56 - connect \muxid \core_calculate_stage_56_muxid - connect \logical_op__insn_type \core_calculate_stage_56_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_56_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_56_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_56_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_56_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_56_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_56_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_56_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_56_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_56_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_56_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_56_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_56_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_56_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_56_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_56_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_56_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_56_logical_op__insn - connect \ra \core_calculate_stage_56_ra - connect \rb \core_calculate_stage_56_rb - connect \xer_so \core_calculate_stage_56_xer_so - connect \divisor_neg \core_calculate_stage_56_divisor_neg - connect \dividend_neg \core_calculate_stage_56_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_56_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_56_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_56_div_by_zero - connect \divisor_radicand \core_calculate_stage_56_divisor_radicand - connect \operation \core_calculate_stage_56_operation - connect \quotient_root \core_calculate_stage_56_quotient_root - connect \root_times_radicand \core_calculate_stage_56_root_times_radicand - connect \compare_lhs \core_calculate_stage_56_compare_lhs - connect \compare_rhs \core_calculate_stage_56_compare_rhs - connect \muxid$1 \core_calculate_stage_56_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_56_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_56_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_56_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_56_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_56_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_56_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_56_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_56_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_56_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_56_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_56_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_56_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_56_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_56_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_56_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_56_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_56_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_56_ra$53 - connect \rb$21 \core_calculate_stage_56_rb$54 - connect \xer_so$22 \core_calculate_stage_56_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_56_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_56_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_56_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_56_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_56_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_56_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_56_operation$62 - connect \quotient_root$30 \core_calculate_stage_56_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_56_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_56_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_56_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_57_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_57_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_57_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_57_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_57_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_57_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_57_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_57_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_57_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_57_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_57_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_57_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_57_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_57_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_57_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_57_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_57_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_57_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_57_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_57_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_57_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_57_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_57_logical_op__insn_type$68 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_57_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_57_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_57_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_57_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_57_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_57_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_57_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_57_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_57_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_57_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_57_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_57_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_57_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_57_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_57_compare_rhs$99 - cell \core_calculate_stage_57 \core_calculate_stage_57 - connect \muxid \core_calculate_stage_57_muxid - connect \logical_op__insn_type \core_calculate_stage_57_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_57_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_57_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_57_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_57_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_57_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_57_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_57_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_57_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_57_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_57_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_57_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_57_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_57_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_57_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_57_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_57_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_57_logical_op__insn - connect \ra \core_calculate_stage_57_ra - connect \rb \core_calculate_stage_57_rb - connect \xer_so \core_calculate_stage_57_xer_so - connect \divisor_neg \core_calculate_stage_57_divisor_neg - connect \dividend_neg \core_calculate_stage_57_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_57_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_57_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_57_div_by_zero - connect \divisor_radicand \core_calculate_stage_57_divisor_radicand - connect \operation \core_calculate_stage_57_operation - connect \quotient_root \core_calculate_stage_57_quotient_root - connect \root_times_radicand \core_calculate_stage_57_root_times_radicand - connect \compare_lhs \core_calculate_stage_57_compare_lhs - connect \compare_rhs \core_calculate_stage_57_compare_rhs - connect \muxid$1 \core_calculate_stage_57_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_57_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_57_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_57_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_57_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_57_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_57_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_57_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_57_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_57_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_57_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_57_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_57_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_57_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_57_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_57_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_57_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_57_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_57_ra$86 - connect \rb$21 \core_calculate_stage_57_rb$87 - connect \xer_so$22 \core_calculate_stage_57_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_57_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_57_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_57_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_57_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_57_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_57_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_57_operation$95 - connect \quotient_root$30 \core_calculate_stage_57_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_57_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_57_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_57_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_58_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_58_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_58_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_58_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_58_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_58_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_58_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_58_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_58_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_58_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_58_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_58_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_58_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_58_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_58_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_58_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_58_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_58_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_58_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_58_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_58_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_58_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_58_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_58_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_58_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_58_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_58_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_58_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_58_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_58_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_58_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_58_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_58_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_58_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_58_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_58_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_58_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_58_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_58_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_58_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_58_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_58_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_58_compare_rhs$132 - cell \core_calculate_stage_58 \core_calculate_stage_58 - connect \muxid \core_calculate_stage_58_muxid - connect \logical_op__insn_type \core_calculate_stage_58_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_58_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_58_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_58_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_58_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_58_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_58_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_58_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_58_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_58_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_58_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_58_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_58_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_58_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_58_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_58_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_58_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_58_logical_op__insn - connect \ra \core_calculate_stage_58_ra - connect \rb \core_calculate_stage_58_rb - connect \xer_so \core_calculate_stage_58_xer_so - connect \divisor_neg \core_calculate_stage_58_divisor_neg - connect \dividend_neg \core_calculate_stage_58_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_58_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_58_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_58_div_by_zero - connect \divisor_radicand \core_calculate_stage_58_divisor_radicand - connect \operation \core_calculate_stage_58_operation - connect \quotient_root \core_calculate_stage_58_quotient_root - connect \root_times_radicand \core_calculate_stage_58_root_times_radicand - connect \compare_lhs \core_calculate_stage_58_compare_lhs - connect \compare_rhs \core_calculate_stage_58_compare_rhs - connect \muxid$1 \core_calculate_stage_58_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_58_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_58_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_58_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_58_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_58_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_58_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_58_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_58_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_58_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_58_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_58_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_58_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_58_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_58_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_58_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_58_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_58_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_58_ra$119 - connect \rb$21 \core_calculate_stage_58_rb$120 - connect \xer_so$22 \core_calculate_stage_58_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_58_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_58_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_58_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_58_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_58_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_58_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_58_operation$128 - connect \quotient_root$30 \core_calculate_stage_58_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_58_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_58_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_58_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_59_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_59_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_59_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_59_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_59_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_59_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_59_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_59_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_59_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_59_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_59_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_59_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_59_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_59_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_59_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_59_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_59_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_59_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_59_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_59_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_59_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_59_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_59_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_59_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_59_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_59_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_59_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_59_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_59_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_59_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_59_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_59_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_59_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_59_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_59_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_59_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_59_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_59_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_59_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_59_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_59_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_59_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_59_compare_rhs$165 - cell \core_calculate_stage_59 \core_calculate_stage_59 - connect \muxid \core_calculate_stage_59_muxid - connect \logical_op__insn_type \core_calculate_stage_59_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_59_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_59_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_59_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_59_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_59_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_59_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_59_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_59_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_59_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_59_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_59_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_59_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_59_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_59_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_59_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_59_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_59_logical_op__insn - connect \ra \core_calculate_stage_59_ra - connect \rb \core_calculate_stage_59_rb - connect \xer_so \core_calculate_stage_59_xer_so - connect \divisor_neg \core_calculate_stage_59_divisor_neg - connect \dividend_neg \core_calculate_stage_59_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_59_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_59_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_59_div_by_zero - connect \divisor_radicand \core_calculate_stage_59_divisor_radicand - connect \operation \core_calculate_stage_59_operation - connect \quotient_root \core_calculate_stage_59_quotient_root - connect \root_times_radicand \core_calculate_stage_59_root_times_radicand - connect \compare_lhs \core_calculate_stage_59_compare_lhs - connect \compare_rhs \core_calculate_stage_59_compare_rhs - connect \muxid$1 \core_calculate_stage_59_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_59_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_59_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_59_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_59_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_59_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_59_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_59_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_59_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_59_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_59_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_59_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_59_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_59_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_59_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_59_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_59_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_59_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_59_ra$152 - connect \rb$21 \core_calculate_stage_59_rb$153 - connect \xer_so$22 \core_calculate_stage_59_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_59_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_59_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_59_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_59_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_59_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_59_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_59_operation$161 - connect \quotient_root$30 \core_calculate_stage_59_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_59_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_59_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_59_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_56_muxid 2'00 - assign \core_calculate_stage_56_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_56_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_56_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_56_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_56_logical_op__rc__rc 1'0 - assign \core_calculate_stage_56_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_56_logical_op__oe__oe 1'0 - assign \core_calculate_stage_56_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_56_logical_op__invert_in 1'0 - assign \core_calculate_stage_56_logical_op__zero_a 1'0 - assign \core_calculate_stage_56_logical_op__input_carry 2'00 - assign \core_calculate_stage_56_logical_op__invert_out 1'0 - assign \core_calculate_stage_56_logical_op__write_cr0 1'0 - assign \core_calculate_stage_56_logical_op__output_carry 1'0 - assign \core_calculate_stage_56_logical_op__is_32bit 1'0 - assign \core_calculate_stage_56_logical_op__is_signed 1'0 - assign \core_calculate_stage_56_logical_op__data_len 4'0000 - assign \core_calculate_stage_56_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_56_logical_op__insn \core_calculate_stage_56_logical_op__data_len \core_calculate_stage_56_logical_op__is_signed \core_calculate_stage_56_logical_op__is_32bit \core_calculate_stage_56_logical_op__output_carry \core_calculate_stage_56_logical_op__write_cr0 \core_calculate_stage_56_logical_op__invert_out \core_calculate_stage_56_logical_op__input_carry \core_calculate_stage_56_logical_op__zero_a \core_calculate_stage_56_logical_op__invert_in { \core_calculate_stage_56_logical_op__oe__oe_ok \core_calculate_stage_56_logical_op__oe__oe } { \core_calculate_stage_56_logical_op__rc__rc_ok \core_calculate_stage_56_logical_op__rc__rc } { \core_calculate_stage_56_logical_op__imm_data__imm_ok \core_calculate_stage_56_logical_op__imm_data__imm } \core_calculate_stage_56_logical_op__fn_unit \core_calculate_stage_56_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_56_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_56_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_56_xer_so 1'0 - assign \core_calculate_stage_56_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_56_divisor_neg 1'0 - assign \core_calculate_stage_56_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_56_dividend_neg 1'0 - assign \core_calculate_stage_56_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_56_dive_abs_ov32 1'0 - assign \core_calculate_stage_56_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_56_dive_abs_ov64 1'0 - assign \core_calculate_stage_56_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_56_div_by_zero 1'0 - assign \core_calculate_stage_56_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_56_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_56_operation 2'00 - assign \core_calculate_stage_56_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_56_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_56_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_56_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_56_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_56_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_57_muxid 2'00 - assign \core_calculate_stage_57_muxid \core_calculate_stage_56_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_57_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_57_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_57_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_57_logical_op__rc__rc 1'0 - assign \core_calculate_stage_57_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_57_logical_op__oe__oe 1'0 - assign \core_calculate_stage_57_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_57_logical_op__invert_in 1'0 - assign \core_calculate_stage_57_logical_op__zero_a 1'0 - assign \core_calculate_stage_57_logical_op__input_carry 2'00 - assign \core_calculate_stage_57_logical_op__invert_out 1'0 - assign \core_calculate_stage_57_logical_op__write_cr0 1'0 - assign \core_calculate_stage_57_logical_op__output_carry 1'0 - assign \core_calculate_stage_57_logical_op__is_32bit 1'0 - assign \core_calculate_stage_57_logical_op__is_signed 1'0 - assign \core_calculate_stage_57_logical_op__data_len 4'0000 - assign \core_calculate_stage_57_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_57_logical_op__insn \core_calculate_stage_57_logical_op__data_len \core_calculate_stage_57_logical_op__is_signed \core_calculate_stage_57_logical_op__is_32bit \core_calculate_stage_57_logical_op__output_carry \core_calculate_stage_57_logical_op__write_cr0 \core_calculate_stage_57_logical_op__invert_out \core_calculate_stage_57_logical_op__input_carry \core_calculate_stage_57_logical_op__zero_a \core_calculate_stage_57_logical_op__invert_in { \core_calculate_stage_57_logical_op__oe__oe_ok \core_calculate_stage_57_logical_op__oe__oe } { \core_calculate_stage_57_logical_op__rc__rc_ok \core_calculate_stage_57_logical_op__rc__rc } { \core_calculate_stage_57_logical_op__imm_data__imm_ok \core_calculate_stage_57_logical_op__imm_data__imm } \core_calculate_stage_57_logical_op__fn_unit \core_calculate_stage_57_logical_op__insn_type } { \core_calculate_stage_56_logical_op__insn$52 \core_calculate_stage_56_logical_op__data_len$51 \core_calculate_stage_56_logical_op__is_signed$50 \core_calculate_stage_56_logical_op__is_32bit$49 \core_calculate_stage_56_logical_op__output_carry$48 \core_calculate_stage_56_logical_op__write_cr0$47 \core_calculate_stage_56_logical_op__invert_out$46 \core_calculate_stage_56_logical_op__input_carry$45 \core_calculate_stage_56_logical_op__zero_a$44 \core_calculate_stage_56_logical_op__invert_in$43 { \core_calculate_stage_56_logical_op__oe__oe_ok$42 \core_calculate_stage_56_logical_op__oe__oe$41 } { \core_calculate_stage_56_logical_op__rc__rc_ok$40 \core_calculate_stage_56_logical_op__rc__rc$39 } { \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 \core_calculate_stage_56_logical_op__imm_data__imm$37 } \core_calculate_stage_56_logical_op__fn_unit$36 \core_calculate_stage_56_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_57_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_ra \core_calculate_stage_56_ra$53 - sync init - end - process $group_53 - assign \core_calculate_stage_57_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_rb \core_calculate_stage_56_rb$54 - sync init - end - process $group_54 - assign \core_calculate_stage_57_xer_so 1'0 - assign \core_calculate_stage_57_xer_so \core_calculate_stage_56_xer_so$55 - sync init - end - process $group_55 - assign \core_calculate_stage_57_divisor_neg 1'0 - assign \core_calculate_stage_57_divisor_neg \core_calculate_stage_56_divisor_neg$56 - sync init - end - process $group_56 - assign \core_calculate_stage_57_dividend_neg 1'0 - assign \core_calculate_stage_57_dividend_neg \core_calculate_stage_56_dividend_neg$57 - sync init - end - process $group_57 - assign \core_calculate_stage_57_dive_abs_ov32 1'0 - assign \core_calculate_stage_57_dive_abs_ov32 \core_calculate_stage_56_dive_abs_ov32$58 - sync init - end - process $group_58 - assign \core_calculate_stage_57_dive_abs_ov64 1'0 - assign \core_calculate_stage_57_dive_abs_ov64 \core_calculate_stage_56_dive_abs_ov64$59 - sync init - end - process $group_59 - assign \core_calculate_stage_57_div_by_zero 1'0 - assign \core_calculate_stage_57_div_by_zero \core_calculate_stage_56_div_by_zero$60 - sync init - end - process $group_60 - assign \core_calculate_stage_57_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_divisor_radicand \core_calculate_stage_56_divisor_radicand$61 - sync init - end - process $group_61 - assign \core_calculate_stage_57_operation 2'00 - assign \core_calculate_stage_57_operation \core_calculate_stage_56_operation$62 - sync init - end - process $group_62 - assign \core_calculate_stage_57_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_quotient_root \core_calculate_stage_56_quotient_root$63 - sync init - end - process $group_63 - assign \core_calculate_stage_57_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_root_times_radicand \core_calculate_stage_56_root_times_radicand$64 - sync init - end - process $group_64 - assign \core_calculate_stage_57_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_compare_lhs \core_calculate_stage_56_compare_lhs$65 - sync init - end - process $group_65 - assign \core_calculate_stage_57_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_57_compare_rhs \core_calculate_stage_56_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_58_muxid 2'00 - assign \core_calculate_stage_58_muxid \core_calculate_stage_57_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_58_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_58_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_58_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_58_logical_op__rc__rc 1'0 - assign \core_calculate_stage_58_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_58_logical_op__oe__oe 1'0 - assign \core_calculate_stage_58_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_58_logical_op__invert_in 1'0 - assign \core_calculate_stage_58_logical_op__zero_a 1'0 - assign \core_calculate_stage_58_logical_op__input_carry 2'00 - assign \core_calculate_stage_58_logical_op__invert_out 1'0 - assign \core_calculate_stage_58_logical_op__write_cr0 1'0 - assign \core_calculate_stage_58_logical_op__output_carry 1'0 - assign \core_calculate_stage_58_logical_op__is_32bit 1'0 - assign \core_calculate_stage_58_logical_op__is_signed 1'0 - assign \core_calculate_stage_58_logical_op__data_len 4'0000 - assign \core_calculate_stage_58_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_58_logical_op__insn \core_calculate_stage_58_logical_op__data_len \core_calculate_stage_58_logical_op__is_signed \core_calculate_stage_58_logical_op__is_32bit \core_calculate_stage_58_logical_op__output_carry \core_calculate_stage_58_logical_op__write_cr0 \core_calculate_stage_58_logical_op__invert_out \core_calculate_stage_58_logical_op__input_carry \core_calculate_stage_58_logical_op__zero_a \core_calculate_stage_58_logical_op__invert_in { \core_calculate_stage_58_logical_op__oe__oe_ok \core_calculate_stage_58_logical_op__oe__oe } { \core_calculate_stage_58_logical_op__rc__rc_ok \core_calculate_stage_58_logical_op__rc__rc } { \core_calculate_stage_58_logical_op__imm_data__imm_ok \core_calculate_stage_58_logical_op__imm_data__imm } \core_calculate_stage_58_logical_op__fn_unit \core_calculate_stage_58_logical_op__insn_type } { \core_calculate_stage_57_logical_op__insn$85 \core_calculate_stage_57_logical_op__data_len$84 \core_calculate_stage_57_logical_op__is_signed$83 \core_calculate_stage_57_logical_op__is_32bit$82 \core_calculate_stage_57_logical_op__output_carry$81 \core_calculate_stage_57_logical_op__write_cr0$80 \core_calculate_stage_57_logical_op__invert_out$79 \core_calculate_stage_57_logical_op__input_carry$78 \core_calculate_stage_57_logical_op__zero_a$77 \core_calculate_stage_57_logical_op__invert_in$76 { \core_calculate_stage_57_logical_op__oe__oe_ok$75 \core_calculate_stage_57_logical_op__oe__oe$74 } { \core_calculate_stage_57_logical_op__rc__rc_ok$73 \core_calculate_stage_57_logical_op__rc__rc$72 } { \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 \core_calculate_stage_57_logical_op__imm_data__imm$70 } \core_calculate_stage_57_logical_op__fn_unit$69 \core_calculate_stage_57_logical_op__insn_type$68 } - sync init - end - process $group_85 - assign \core_calculate_stage_58_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_ra \core_calculate_stage_57_ra$86 - sync init - end - process $group_86 - assign \core_calculate_stage_58_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_rb \core_calculate_stage_57_rb$87 - sync init - end - process $group_87 - assign \core_calculate_stage_58_xer_so 1'0 - assign \core_calculate_stage_58_xer_so \core_calculate_stage_57_xer_so$88 - sync init - end - process $group_88 - assign \core_calculate_stage_58_divisor_neg 1'0 - assign \core_calculate_stage_58_divisor_neg \core_calculate_stage_57_divisor_neg$89 - sync init - end - process $group_89 - assign \core_calculate_stage_58_dividend_neg 1'0 - assign \core_calculate_stage_58_dividend_neg \core_calculate_stage_57_dividend_neg$90 - sync init - end - process $group_90 - assign \core_calculate_stage_58_dive_abs_ov32 1'0 - assign \core_calculate_stage_58_dive_abs_ov32 \core_calculate_stage_57_dive_abs_ov32$91 - sync init - end - process $group_91 - assign \core_calculate_stage_58_dive_abs_ov64 1'0 - assign \core_calculate_stage_58_dive_abs_ov64 \core_calculate_stage_57_dive_abs_ov64$92 - sync init - end - process $group_92 - assign \core_calculate_stage_58_div_by_zero 1'0 - assign \core_calculate_stage_58_div_by_zero \core_calculate_stage_57_div_by_zero$93 - sync init - end - process $group_93 - assign \core_calculate_stage_58_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_divisor_radicand \core_calculate_stage_57_divisor_radicand$94 - sync init - end - process $group_94 - assign \core_calculate_stage_58_operation 2'00 - assign \core_calculate_stage_58_operation \core_calculate_stage_57_operation$95 - sync init - end - process $group_95 - assign \core_calculate_stage_58_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_quotient_root \core_calculate_stage_57_quotient_root$96 - sync init - end - process $group_96 - assign \core_calculate_stage_58_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_root_times_radicand \core_calculate_stage_57_root_times_radicand$97 - sync init - end - process $group_97 - assign \core_calculate_stage_58_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_compare_lhs \core_calculate_stage_57_compare_lhs$98 - sync init - end - process $group_98 - assign \core_calculate_stage_58_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_58_compare_rhs \core_calculate_stage_57_compare_rhs$99 - sync init - end - process $group_99 - assign \core_calculate_stage_59_muxid 2'00 - assign \core_calculate_stage_59_muxid \core_calculate_stage_58_muxid$100 - sync init - end - process $group_100 - assign \core_calculate_stage_59_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_59_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_59_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_59_logical_op__rc__rc 1'0 - assign \core_calculate_stage_59_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_59_logical_op__oe__oe 1'0 - assign \core_calculate_stage_59_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_59_logical_op__invert_in 1'0 - assign \core_calculate_stage_59_logical_op__zero_a 1'0 - assign \core_calculate_stage_59_logical_op__input_carry 2'00 - assign \core_calculate_stage_59_logical_op__invert_out 1'0 - assign \core_calculate_stage_59_logical_op__write_cr0 1'0 - assign \core_calculate_stage_59_logical_op__output_carry 1'0 - assign \core_calculate_stage_59_logical_op__is_32bit 1'0 - assign \core_calculate_stage_59_logical_op__is_signed 1'0 - assign \core_calculate_stage_59_logical_op__data_len 4'0000 - assign \core_calculate_stage_59_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_59_logical_op__insn \core_calculate_stage_59_logical_op__data_len \core_calculate_stage_59_logical_op__is_signed \core_calculate_stage_59_logical_op__is_32bit \core_calculate_stage_59_logical_op__output_carry \core_calculate_stage_59_logical_op__write_cr0 \core_calculate_stage_59_logical_op__invert_out \core_calculate_stage_59_logical_op__input_carry \core_calculate_stage_59_logical_op__zero_a \core_calculate_stage_59_logical_op__invert_in { \core_calculate_stage_59_logical_op__oe__oe_ok \core_calculate_stage_59_logical_op__oe__oe } { \core_calculate_stage_59_logical_op__rc__rc_ok \core_calculate_stage_59_logical_op__rc__rc } { \core_calculate_stage_59_logical_op__imm_data__imm_ok \core_calculate_stage_59_logical_op__imm_data__imm } \core_calculate_stage_59_logical_op__fn_unit \core_calculate_stage_59_logical_op__insn_type } { \core_calculate_stage_58_logical_op__insn$118 \core_calculate_stage_58_logical_op__data_len$117 \core_calculate_stage_58_logical_op__is_signed$116 \core_calculate_stage_58_logical_op__is_32bit$115 \core_calculate_stage_58_logical_op__output_carry$114 \core_calculate_stage_58_logical_op__write_cr0$113 \core_calculate_stage_58_logical_op__invert_out$112 \core_calculate_stage_58_logical_op__input_carry$111 \core_calculate_stage_58_logical_op__zero_a$110 \core_calculate_stage_58_logical_op__invert_in$109 { \core_calculate_stage_58_logical_op__oe__oe_ok$108 \core_calculate_stage_58_logical_op__oe__oe$107 } { \core_calculate_stage_58_logical_op__rc__rc_ok$106 \core_calculate_stage_58_logical_op__rc__rc$105 } { \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 \core_calculate_stage_58_logical_op__imm_data__imm$103 } \core_calculate_stage_58_logical_op__fn_unit$102 \core_calculate_stage_58_logical_op__insn_type$101 } - sync init - end - process $group_118 - assign \core_calculate_stage_59_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_ra \core_calculate_stage_58_ra$119 - sync init - end - process $group_119 - assign \core_calculate_stage_59_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_rb \core_calculate_stage_58_rb$120 - sync init - end - process $group_120 - assign \core_calculate_stage_59_xer_so 1'0 - assign \core_calculate_stage_59_xer_so \core_calculate_stage_58_xer_so$121 - sync init - end - process $group_121 - assign \core_calculate_stage_59_divisor_neg 1'0 - assign \core_calculate_stage_59_divisor_neg \core_calculate_stage_58_divisor_neg$122 - sync init - end - process $group_122 - assign \core_calculate_stage_59_dividend_neg 1'0 - assign \core_calculate_stage_59_dividend_neg \core_calculate_stage_58_dividend_neg$123 - sync init - end - process $group_123 - assign \core_calculate_stage_59_dive_abs_ov32 1'0 - assign \core_calculate_stage_59_dive_abs_ov32 \core_calculate_stage_58_dive_abs_ov32$124 - sync init - end - process $group_124 - assign \core_calculate_stage_59_dive_abs_ov64 1'0 - assign \core_calculate_stage_59_dive_abs_ov64 \core_calculate_stage_58_dive_abs_ov64$125 - sync init - end - process $group_125 - assign \core_calculate_stage_59_div_by_zero 1'0 - assign \core_calculate_stage_59_div_by_zero \core_calculate_stage_58_div_by_zero$126 - sync init - end - process $group_126 - assign \core_calculate_stage_59_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_divisor_radicand \core_calculate_stage_58_divisor_radicand$127 - sync init - end - process $group_127 - assign \core_calculate_stage_59_operation 2'00 - assign \core_calculate_stage_59_operation \core_calculate_stage_58_operation$128 - sync init - end - process $group_128 - assign \core_calculate_stage_59_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_quotient_root \core_calculate_stage_58_quotient_root$129 - sync init - end - process $group_129 - assign \core_calculate_stage_59_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_root_times_radicand \core_calculate_stage_58_root_times_radicand$130 - sync init - end - process $group_130 - assign \core_calculate_stage_59_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_compare_lhs \core_calculate_stage_58_compare_lhs$131 - sync init - end - process $group_131 - assign \core_calculate_stage_59_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_59_compare_rhs \core_calculate_stage_58_compare_rhs$132 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$166 - process $group_132 - assign \p_valid_i$166 1'0 - assign \p_valid_i$166 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_133 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$166 - connect \B \p_ready_o - connect \Y $167 - end - process $group_134 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $167 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$169 - process $group_135 - assign \muxid$169 2'00 - assign \muxid$169 \core_calculate_stage_59_muxid$133 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_59_logical_op__insn$151 \core_calculate_stage_59_logical_op__data_len$150 \core_calculate_stage_59_logical_op__is_signed$149 \core_calculate_stage_59_logical_op__is_32bit$148 \core_calculate_stage_59_logical_op__output_carry$147 \core_calculate_stage_59_logical_op__write_cr0$146 \core_calculate_stage_59_logical_op__invert_out$145 \core_calculate_stage_59_logical_op__input_carry$144 \core_calculate_stage_59_logical_op__zero_a$143 \core_calculate_stage_59_logical_op__invert_in$142 { \core_calculate_stage_59_logical_op__oe__oe_ok$141 \core_calculate_stage_59_logical_op__oe__oe$140 } { \core_calculate_stage_59_logical_op__rc__rc_ok$139 \core_calculate_stage_59_logical_op__rc__rc$138 } { \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 \core_calculate_stage_59_logical_op__imm_data__imm$136 } \core_calculate_stage_59_logical_op__fn_unit$135 \core_calculate_stage_59_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_59_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_59_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_59_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_59_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_59_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_59_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_59_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_59_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_59_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_59_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_59_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_59_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_59_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_59_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.p" -module \p$344 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.n" -module \n$345 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.trial0" -module \trial0$347 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.trial1" -module \trial1$348 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000011 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.pe" -module \pe$349 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core" -module \core$346 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$347 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$348 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$349 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$346 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.trial0" -module \trial0$351 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.trial1" -module \trial1$352 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000010 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.pe" -module \pe$353 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core" -module \core$350 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$351 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$352 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$353 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 4 $30 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$350 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 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\core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.trial0" -module \trial0$355 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.trial1" -module \trial1$356 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000001 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.pe" -module \pe$357 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$355 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$356 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$357 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" - wire width 2 \pass_flags - process $group_15 - assign \pass_flags 2'00 - assign \pass_flags { \pass_flag_1 \pass_flag_0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - wire width 2 $12 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \pass_flags - connect \Y $12 - end - process $group_16 - assign \pe_i 2'00 - assign \pe_i $12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" - wire width 1 \next_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src 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width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$354 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$28 \core_divisor_radicand$34 - sync init - end - process $group_34 - assign \operation$29 2'00 - assign \operation$29 \core_operation$35 - sync init - end - process $group_35 - assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$30 \core_quotient_root$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$39 - process $group_36 - assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$31 \root_times_radicand$39 - sync init - end - process $group_37 - assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$32 \core_compare_lhs$37 - sync init - end - process $group_38 - assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$33 \core_compare_rhs$38 - sync init - end - connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.trial0" -module \trial0$359 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.trial1" -module \trial1$360 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 input 1 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 input 2 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 output 3 \trial_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" - wire width 65 \dr_times_trial_bits - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - wire width 65 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" - cell $mul $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \divisor_radicand - connect \B 1'1 - connect \Y $3 - end - process $group_0 - assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \dr_times_trial_bits $3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 1'1 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $7 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 192 $8 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $sshl $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 192 - connect \A \dr_times_trial_bits - connect \B 7'1000000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - wire width 193 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" - cell $add $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_rhs - connect \B $8 - connect \Y $10 - end - connect $7 $10 - process $group_1 - assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" - case 1'1 - assign \trial_compare_rhs $7 [191:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.pe" -module \pe$361 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 1 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 2 \o - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [1] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i [0] } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core" -module \core$358 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 0 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 1 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 2 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 3 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 4 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 5 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 6 \divisor_radicand$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 7 \operation$2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 8 \quotient_root$3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 9 \compare_lhs$4 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 10 \compare_rhs$5 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial0_trial_compare_rhs - cell \trial0$359 \trial0 - connect \divisor_radicand \trial0_divisor_radicand - connect \compare_rhs \trial0_compare_rhs - connect \operation \trial0_operation - connect \trial_compare_rhs \trial0_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" - wire width 64 \trial1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" - wire width 192 \trial1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" - wire width 2 \trial1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" - wire width 192 \trial1_trial_compare_rhs - cell \trial1$360 \trial1 - connect \divisor_radicand \trial1_divisor_radicand - connect \compare_rhs \trial1_compare_rhs - connect \operation \trial1_operation - connect \trial_compare_rhs \trial1_trial_compare_rhs - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 2 \pe_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pe_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pe_o - cell \pe$361 \pe - connect \i \pe_i - connect \n \pe_n - connect \o \pe_o - end - process $group_0 - assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$1 \divisor_radicand - sync init - end - process $group_1 - assign \operation$2 2'00 - assign \operation$2 \operation - sync init - end - process $group_2 - assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$4 \compare_lhs - sync init - end - process $group_3 - assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$6 - process $group_4 - assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$6 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$7 - process $group_5 - assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$7 \root_times_radicand - sync init - end - process $group_6 - assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial0_compare_rhs \compare_rhs - sync init - end - process $group_7 - assign \trial0_operation 2'00 - assign \trial0_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_0 - wire width 1 $verilog_initial_trigger - process $group_8 - assign \pass_flag_0 1'0 - assign \pass_flag_0 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_9 - assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_divisor_radicand \divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" - wire width 64 \quotient_root$8 - process $group_10 - assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$8 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" - wire width 128 \root_times_radicand$9 - process $group_11 - assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$9 \root_times_radicand - sync init - end - process $group_12 - assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \trial1_compare_rhs \compare_rhs - sync init - end - process $group_13 - assign \trial1_operation 2'00 - assign \trial1_operation \operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" - wire width 1 \pass_flag_1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" - cell $ge $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 1 - connect \A \compare_lhs - connect \B \trial1_trial_compare_rhs - connect \Y $10 - end - process $group_14 - assign \pass_flag_1 1'0 - assign \pass_flag_1 $10 - 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"/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - cell $not $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pe_n - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - wire width 2 $17 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" - cell $sub $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \pe_o - connect \B 1'1 - connect \Y $17 - end - connect $16 $17 - process $group_17 - assign \next_bits 1'0 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" - case 1'1 - assign \next_bits $16 [0] - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" - case - assign \next_bits 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'0 - connect \Y $19 - end - process $group_18 - assign \nbe 1'0 - assign \nbe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" - wire width 1 \nbe$21 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \next_bits - connect \B 1'1 - connect \Y $22 - end - process $group_19 - assign \nbe$21 1'0 - assign \nbe$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $24 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } - connect \B \trial0_trial_compare_rhs - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - wire width 192 $26 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } - connect \B \trial1_trial_compare_rhs - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 192 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $24 - connect \B $26 - connect \Y $28 - end - process $group_20 - assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$5 $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 2 $30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $sshl $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \next_bits - connect \B 1'0 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 64 - connect \A \quotient_root - connect \B $30 - connect \Y $32 - end - process $group_21 - assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$3 $32 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63" -module \core_calculate_stage_63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 30 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 31 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 32 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 33 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 34 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 35 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 36 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 44 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 50 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 51 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 52 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 53 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 54 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 55 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 56 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 57 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 58 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 59 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 60 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 61 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 62 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 63 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 64 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 65 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_divisor_radicand$34 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_operation$35 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_quotient_root$36 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_compare_lhs$37 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_compare_rhs$38 - cell \core$358 \core - connect \divisor_radicand \core_divisor_radicand - connect \operation \core_operation - connect \quotient_root \core_quotient_root - connect \root_times_radicand \core_root_times_radicand - connect \compare_lhs \core_compare_lhs - connect \compare_rhs \core_compare_rhs - connect \divisor_radicand$1 \core_divisor_radicand$34 - connect \operation$2 \core_operation$35 - connect \quotient_root$3 \core_quotient_root$36 - connect \compare_lhs$4 \core_compare_lhs$37 - connect \compare_rhs$5 \core_compare_rhs$38 - end - process $group_0 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_1 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra - sync init - end - process $group_20 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb - sync init - end - process $group_21 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_22 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg - sync init - end - process $group_23 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg - sync init - end - process $group_24 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32 - sync init - end - process $group_25 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64 - sync init - end - process $group_26 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero - sync init - end - process $group_27 - assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_operation 2'00 - assign \core_operation \operation - sync init - end - process $group_29 - assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_compare_rhs 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 60 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 61 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 62 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 63 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 64 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 65 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$27$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 output 66 \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$28$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 output 67 \operation$29 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$29$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 output 68 \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$30$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 output 69 \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$31$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 output 70 \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$32$next - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 output 71 \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$33$next - cell \p$344 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$345 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_60_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_60_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_60_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_60_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_60_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_60_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_60_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_60_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_60_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_60_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_60_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_60_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_60_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_60_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_60_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_60_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_60_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_60_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_60_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_60_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_60_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_60_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_60_logical_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_60_logical_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_60_logical_op__imm_data__imm$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__rc__rc_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__oe__oe_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__invert_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__zero_a$44 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_60_logical_op__input_carry$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__invert_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__write_cr0$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__output_carry$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__is_32bit$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_60_logical_op__is_signed$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_60_logical_op__data_len$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_60_logical_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_60_ra$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_60_rb$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_60_xer_so$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_60_divisor_neg$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_60_dividend_neg$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_60_dive_abs_ov32$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_60_dive_abs_ov64$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_60_div_by_zero$60 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_60_divisor_radicand$61 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_60_operation$62 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_60_quotient_root$63 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_60_root_times_radicand$64 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_60_compare_lhs$65 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_60_compare_rhs$66 - cell \core_calculate_stage_60 \core_calculate_stage_60 - connect \muxid \core_calculate_stage_60_muxid - connect \logical_op__insn_type \core_calculate_stage_60_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_60_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_60_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_60_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_60_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_60_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_60_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_60_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_60_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_60_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_60_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_60_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_60_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_60_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_60_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_60_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_60_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_60_logical_op__insn - connect \ra \core_calculate_stage_60_ra - connect \rb \core_calculate_stage_60_rb - connect \xer_so \core_calculate_stage_60_xer_so - connect \divisor_neg \core_calculate_stage_60_divisor_neg - connect \dividend_neg \core_calculate_stage_60_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_60_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_60_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_60_div_by_zero - connect \divisor_radicand \core_calculate_stage_60_divisor_radicand - connect \operation \core_calculate_stage_60_operation - connect \quotient_root \core_calculate_stage_60_quotient_root - connect \root_times_radicand \core_calculate_stage_60_root_times_radicand - connect \compare_lhs \core_calculate_stage_60_compare_lhs - connect \compare_rhs \core_calculate_stage_60_compare_rhs - connect \muxid$1 \core_calculate_stage_60_muxid$34 - connect \logical_op__insn_type$2 \core_calculate_stage_60_logical_op__insn_type$35 - connect \logical_op__fn_unit$3 \core_calculate_stage_60_logical_op__fn_unit$36 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_60_logical_op__imm_data__imm$37 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 - connect \logical_op__rc__rc$6 \core_calculate_stage_60_logical_op__rc__rc$39 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_60_logical_op__rc__rc_ok$40 - connect \logical_op__oe__oe$8 \core_calculate_stage_60_logical_op__oe__oe$41 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_60_logical_op__oe__oe_ok$42 - connect \logical_op__invert_in$10 \core_calculate_stage_60_logical_op__invert_in$43 - connect \logical_op__zero_a$11 \core_calculate_stage_60_logical_op__zero_a$44 - connect \logical_op__input_carry$12 \core_calculate_stage_60_logical_op__input_carry$45 - connect \logical_op__invert_out$13 \core_calculate_stage_60_logical_op__invert_out$46 - connect \logical_op__write_cr0$14 \core_calculate_stage_60_logical_op__write_cr0$47 - connect \logical_op__output_carry$15 \core_calculate_stage_60_logical_op__output_carry$48 - connect \logical_op__is_32bit$16 \core_calculate_stage_60_logical_op__is_32bit$49 - connect \logical_op__is_signed$17 \core_calculate_stage_60_logical_op__is_signed$50 - connect \logical_op__data_len$18 \core_calculate_stage_60_logical_op__data_len$51 - connect \logical_op__insn$19 \core_calculate_stage_60_logical_op__insn$52 - connect \ra$20 \core_calculate_stage_60_ra$53 - connect \rb$21 \core_calculate_stage_60_rb$54 - connect \xer_so$22 \core_calculate_stage_60_xer_so$55 - connect \divisor_neg$23 \core_calculate_stage_60_divisor_neg$56 - connect \dividend_neg$24 \core_calculate_stage_60_dividend_neg$57 - connect \dive_abs_ov32$25 \core_calculate_stage_60_dive_abs_ov32$58 - connect \dive_abs_ov64$26 \core_calculate_stage_60_dive_abs_ov64$59 - connect \div_by_zero$27 \core_calculate_stage_60_div_by_zero$60 - connect \divisor_radicand$28 \core_calculate_stage_60_divisor_radicand$61 - connect \operation$29 \core_calculate_stage_60_operation$62 - connect \quotient_root$30 \core_calculate_stage_60_quotient_root$63 - connect \root_times_radicand$31 \core_calculate_stage_60_root_times_radicand$64 - connect \compare_lhs$32 \core_calculate_stage_60_compare_lhs$65 - connect \compare_rhs$33 \core_calculate_stage_60_compare_rhs$66 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_61_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_61_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_61_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_61_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_61_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_61_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_61_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_61_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_61_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_61_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_61_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_61_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_61_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_61_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_61_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_61_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_61_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_61_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_61_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_61_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_61_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_61_muxid$67 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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11 \core_calculate_stage_61_logical_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_61_logical_op__imm_data__imm$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__imm_data__imm_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__rc__rc$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__rc__rc_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__oe__oe_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__invert_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__zero_a$77 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_61_logical_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__invert_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__write_cr0$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__output_carry$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_61_logical_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_61_logical_op__data_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_61_logical_op__insn$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_61_ra$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_61_rb$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_61_xer_so$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_61_divisor_neg$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_61_dividend_neg$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_61_dive_abs_ov32$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_61_dive_abs_ov64$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_61_div_by_zero$93 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_61_divisor_radicand$94 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_61_operation$95 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_61_quotient_root$96 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_61_root_times_radicand$97 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_61_compare_lhs$98 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_61_compare_rhs$99 - cell \core_calculate_stage_61 \core_calculate_stage_61 - connect \muxid \core_calculate_stage_61_muxid - connect \logical_op__insn_type \core_calculate_stage_61_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_61_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_61_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_61_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_61_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_61_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_61_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_61_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_61_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_61_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_61_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_61_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_61_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_61_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_61_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_61_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_61_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_61_logical_op__insn - connect \ra \core_calculate_stage_61_ra - connect \rb \core_calculate_stage_61_rb - connect \xer_so \core_calculate_stage_61_xer_so - connect \divisor_neg \core_calculate_stage_61_divisor_neg - connect \dividend_neg \core_calculate_stage_61_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_61_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_61_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_61_div_by_zero - connect \divisor_radicand \core_calculate_stage_61_divisor_radicand - connect \operation \core_calculate_stage_61_operation - connect \quotient_root \core_calculate_stage_61_quotient_root - connect \root_times_radicand \core_calculate_stage_61_root_times_radicand - connect \compare_lhs \core_calculate_stage_61_compare_lhs - connect \compare_rhs \core_calculate_stage_61_compare_rhs - connect \muxid$1 \core_calculate_stage_61_muxid$67 - connect \logical_op__insn_type$2 \core_calculate_stage_61_logical_op__insn_type$68 - connect \logical_op__fn_unit$3 \core_calculate_stage_61_logical_op__fn_unit$69 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_61_logical_op__imm_data__imm$70 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_61_logical_op__imm_data__imm_ok$71 - connect \logical_op__rc__rc$6 \core_calculate_stage_61_logical_op__rc__rc$72 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_61_logical_op__rc__rc_ok$73 - connect \logical_op__oe__oe$8 \core_calculate_stage_61_logical_op__oe__oe$74 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_61_logical_op__oe__oe_ok$75 - connect \logical_op__invert_in$10 \core_calculate_stage_61_logical_op__invert_in$76 - connect \logical_op__zero_a$11 \core_calculate_stage_61_logical_op__zero_a$77 - connect \logical_op__input_carry$12 \core_calculate_stage_61_logical_op__input_carry$78 - connect \logical_op__invert_out$13 \core_calculate_stage_61_logical_op__invert_out$79 - connect \logical_op__write_cr0$14 \core_calculate_stage_61_logical_op__write_cr0$80 - connect \logical_op__output_carry$15 \core_calculate_stage_61_logical_op__output_carry$81 - connect \logical_op__is_32bit$16 \core_calculate_stage_61_logical_op__is_32bit$82 - connect \logical_op__is_signed$17 \core_calculate_stage_61_logical_op__is_signed$83 - connect \logical_op__data_len$18 \core_calculate_stage_61_logical_op__data_len$84 - connect \logical_op__insn$19 \core_calculate_stage_61_logical_op__insn$85 - connect \ra$20 \core_calculate_stage_61_ra$86 - connect \rb$21 \core_calculate_stage_61_rb$87 - connect \xer_so$22 \core_calculate_stage_61_xer_so$88 - connect \divisor_neg$23 \core_calculate_stage_61_divisor_neg$89 - connect \dividend_neg$24 \core_calculate_stage_61_dividend_neg$90 - connect \dive_abs_ov32$25 \core_calculate_stage_61_dive_abs_ov32$91 - connect \dive_abs_ov64$26 \core_calculate_stage_61_dive_abs_ov64$92 - connect \div_by_zero$27 \core_calculate_stage_61_div_by_zero$93 - connect \divisor_radicand$28 \core_calculate_stage_61_divisor_radicand$94 - connect \operation$29 \core_calculate_stage_61_operation$95 - connect \quotient_root$30 \core_calculate_stage_61_quotient_root$96 - connect \root_times_radicand$31 \core_calculate_stage_61_root_times_radicand$97 - connect \compare_lhs$32 \core_calculate_stage_61_compare_lhs$98 - connect \compare_rhs$33 \core_calculate_stage_61_compare_rhs$99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_62_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_62_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_62_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_62_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_62_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_62_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_62_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_62_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_62_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_62_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_62_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_62_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_62_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_62_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_62_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_62_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_62_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_62_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_62_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_62_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_62_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_62_muxid$100 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_62_logical_op__insn_type$101 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_62_logical_op__fn_unit$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_62_logical_op__imm_data__imm$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__imm_data__imm_ok$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__rc__rc$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__rc__rc_ok$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__oe__oe$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__oe__oe_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__invert_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__zero_a$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_62_logical_op__input_carry$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__invert_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__write_cr0$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__output_carry$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__is_32bit$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_62_logical_op__is_signed$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_62_logical_op__data_len$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_62_logical_op__insn$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_62_ra$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_62_rb$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_62_xer_so$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_62_divisor_neg$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_62_dividend_neg$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_62_dive_abs_ov32$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_62_dive_abs_ov64$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_62_div_by_zero$126 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_62_divisor_radicand$127 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_62_operation$128 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_62_quotient_root$129 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_62_root_times_radicand$130 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_62_compare_lhs$131 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_62_compare_rhs$132 - cell \core_calculate_stage_62 \core_calculate_stage_62 - connect \muxid \core_calculate_stage_62_muxid - connect \logical_op__insn_type \core_calculate_stage_62_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_62_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_62_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_62_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_62_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_62_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_62_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_62_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_62_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_62_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_62_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_62_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_62_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_62_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_62_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_62_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_62_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_62_logical_op__insn - connect \ra \core_calculate_stage_62_ra - connect \rb \core_calculate_stage_62_rb - connect \xer_so \core_calculate_stage_62_xer_so - connect \divisor_neg \core_calculate_stage_62_divisor_neg - connect \dividend_neg \core_calculate_stage_62_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_62_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_62_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_62_div_by_zero - connect \divisor_radicand \core_calculate_stage_62_divisor_radicand - connect \operation \core_calculate_stage_62_operation - connect \quotient_root \core_calculate_stage_62_quotient_root - connect \root_times_radicand \core_calculate_stage_62_root_times_radicand - connect \compare_lhs \core_calculate_stage_62_compare_lhs - connect \compare_rhs \core_calculate_stage_62_compare_rhs - connect \muxid$1 \core_calculate_stage_62_muxid$100 - connect \logical_op__insn_type$2 \core_calculate_stage_62_logical_op__insn_type$101 - connect \logical_op__fn_unit$3 \core_calculate_stage_62_logical_op__fn_unit$102 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_62_logical_op__imm_data__imm$103 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_62_logical_op__imm_data__imm_ok$104 - connect \logical_op__rc__rc$6 \core_calculate_stage_62_logical_op__rc__rc$105 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_62_logical_op__rc__rc_ok$106 - connect \logical_op__oe__oe$8 \core_calculate_stage_62_logical_op__oe__oe$107 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_62_logical_op__oe__oe_ok$108 - connect \logical_op__invert_in$10 \core_calculate_stage_62_logical_op__invert_in$109 - connect \logical_op__zero_a$11 \core_calculate_stage_62_logical_op__zero_a$110 - connect \logical_op__input_carry$12 \core_calculate_stage_62_logical_op__input_carry$111 - connect \logical_op__invert_out$13 \core_calculate_stage_62_logical_op__invert_out$112 - connect \logical_op__write_cr0$14 \core_calculate_stage_62_logical_op__write_cr0$113 - connect \logical_op__output_carry$15 \core_calculate_stage_62_logical_op__output_carry$114 - connect \logical_op__is_32bit$16 \core_calculate_stage_62_logical_op__is_32bit$115 - connect \logical_op__is_signed$17 \core_calculate_stage_62_logical_op__is_signed$116 - connect \logical_op__data_len$18 \core_calculate_stage_62_logical_op__data_len$117 - connect \logical_op__insn$19 \core_calculate_stage_62_logical_op__insn$118 - connect \ra$20 \core_calculate_stage_62_ra$119 - connect \rb$21 \core_calculate_stage_62_rb$120 - connect \xer_so$22 \core_calculate_stage_62_xer_so$121 - connect \divisor_neg$23 \core_calculate_stage_62_divisor_neg$122 - connect \dividend_neg$24 \core_calculate_stage_62_dividend_neg$123 - connect \dive_abs_ov32$25 \core_calculate_stage_62_dive_abs_ov32$124 - connect \dive_abs_ov64$26 \core_calculate_stage_62_dive_abs_ov64$125 - connect \div_by_zero$27 \core_calculate_stage_62_div_by_zero$126 - connect \divisor_radicand$28 \core_calculate_stage_62_divisor_radicand$127 - connect \operation$29 \core_calculate_stage_62_operation$128 - connect \quotient_root$30 \core_calculate_stage_62_quotient_root$129 - connect \root_times_radicand$31 \core_calculate_stage_62_root_times_radicand$130 - connect \compare_lhs$32 \core_calculate_stage_62_compare_lhs$131 - connect \compare_rhs$33 \core_calculate_stage_62_compare_rhs$132 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_63_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_63_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_63_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_63_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_63_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_63_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_63_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_63_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_63_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_63_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_63_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_63_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_63_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_63_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_63_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_63_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_63_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_63_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_63_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_63_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_63_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_calculate_stage_63_muxid$133 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_calculate_stage_63_logical_op__insn_type$134 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \core_calculate_stage_63_logical_op__fn_unit$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_calculate_stage_63_logical_op__imm_data__imm$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__rc__rc$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__rc__rc_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__oe__oe$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__oe__oe_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__invert_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__zero_a$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_calculate_stage_63_logical_op__input_carry$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__invert_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__write_cr0$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__output_carry$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__is_32bit$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_calculate_stage_63_logical_op__is_signed$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_calculate_stage_63_logical_op__data_len$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_calculate_stage_63_logical_op__insn$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_63_ra$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_calculate_stage_63_rb$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_calculate_stage_63_xer_so$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_calculate_stage_63_divisor_neg$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_calculate_stage_63_dividend_neg$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_calculate_stage_63_dive_abs_ov32$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_calculate_stage_63_dive_abs_ov64$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_calculate_stage_63_div_by_zero$159 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_calculate_stage_63_divisor_radicand$160 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_calculate_stage_63_operation$161 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_calculate_stage_63_quotient_root$162 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_calculate_stage_63_root_times_radicand$163 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_calculate_stage_63_compare_lhs$164 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_calculate_stage_63_compare_rhs$165 - cell \core_calculate_stage_63 \core_calculate_stage_63 - connect \muxid \core_calculate_stage_63_muxid - connect \logical_op__insn_type \core_calculate_stage_63_logical_op__insn_type - connect \logical_op__fn_unit \core_calculate_stage_63_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_calculate_stage_63_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_calculate_stage_63_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_calculate_stage_63_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_calculate_stage_63_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_calculate_stage_63_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_calculate_stage_63_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_calculate_stage_63_logical_op__invert_in - connect \logical_op__zero_a \core_calculate_stage_63_logical_op__zero_a - connect \logical_op__input_carry \core_calculate_stage_63_logical_op__input_carry - connect \logical_op__invert_out \core_calculate_stage_63_logical_op__invert_out - connect \logical_op__write_cr0 \core_calculate_stage_63_logical_op__write_cr0 - connect \logical_op__output_carry \core_calculate_stage_63_logical_op__output_carry - connect \logical_op__is_32bit \core_calculate_stage_63_logical_op__is_32bit - connect \logical_op__is_signed \core_calculate_stage_63_logical_op__is_signed - connect \logical_op__data_len \core_calculate_stage_63_logical_op__data_len - connect \logical_op__insn \core_calculate_stage_63_logical_op__insn - connect \ra \core_calculate_stage_63_ra - connect \rb \core_calculate_stage_63_rb - connect \xer_so \core_calculate_stage_63_xer_so - connect \divisor_neg \core_calculate_stage_63_divisor_neg - connect \dividend_neg \core_calculate_stage_63_dividend_neg - connect \dive_abs_ov32 \core_calculate_stage_63_dive_abs_ov32 - connect \dive_abs_ov64 \core_calculate_stage_63_dive_abs_ov64 - connect \div_by_zero \core_calculate_stage_63_div_by_zero - connect \divisor_radicand \core_calculate_stage_63_divisor_radicand - connect \operation \core_calculate_stage_63_operation - connect \quotient_root \core_calculate_stage_63_quotient_root - connect \root_times_radicand \core_calculate_stage_63_root_times_radicand - connect \compare_lhs \core_calculate_stage_63_compare_lhs - connect \compare_rhs \core_calculate_stage_63_compare_rhs - connect \muxid$1 \core_calculate_stage_63_muxid$133 - connect \logical_op__insn_type$2 \core_calculate_stage_63_logical_op__insn_type$134 - connect \logical_op__fn_unit$3 \core_calculate_stage_63_logical_op__fn_unit$135 - connect \logical_op__imm_data__imm$4 \core_calculate_stage_63_logical_op__imm_data__imm$136 - connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 - connect \logical_op__rc__rc$6 \core_calculate_stage_63_logical_op__rc__rc$138 - connect \logical_op__rc__rc_ok$7 \core_calculate_stage_63_logical_op__rc__rc_ok$139 - connect \logical_op__oe__oe$8 \core_calculate_stage_63_logical_op__oe__oe$140 - connect \logical_op__oe__oe_ok$9 \core_calculate_stage_63_logical_op__oe__oe_ok$141 - connect \logical_op__invert_in$10 \core_calculate_stage_63_logical_op__invert_in$142 - connect \logical_op__zero_a$11 \core_calculate_stage_63_logical_op__zero_a$143 - connect \logical_op__input_carry$12 \core_calculate_stage_63_logical_op__input_carry$144 - connect \logical_op__invert_out$13 \core_calculate_stage_63_logical_op__invert_out$145 - connect \logical_op__write_cr0$14 \core_calculate_stage_63_logical_op__write_cr0$146 - connect \logical_op__output_carry$15 \core_calculate_stage_63_logical_op__output_carry$147 - connect \logical_op__is_32bit$16 \core_calculate_stage_63_logical_op__is_32bit$148 - connect \logical_op__is_signed$17 \core_calculate_stage_63_logical_op__is_signed$149 - connect \logical_op__data_len$18 \core_calculate_stage_63_logical_op__data_len$150 - connect \logical_op__insn$19 \core_calculate_stage_63_logical_op__insn$151 - connect \ra$20 \core_calculate_stage_63_ra$152 - connect \rb$21 \core_calculate_stage_63_rb$153 - connect \xer_so$22 \core_calculate_stage_63_xer_so$154 - connect \divisor_neg$23 \core_calculate_stage_63_divisor_neg$155 - connect \dividend_neg$24 \core_calculate_stage_63_dividend_neg$156 - connect \dive_abs_ov32$25 \core_calculate_stage_63_dive_abs_ov32$157 - connect \dive_abs_ov64$26 \core_calculate_stage_63_dive_abs_ov64$158 - connect \div_by_zero$27 \core_calculate_stage_63_div_by_zero$159 - connect \divisor_radicand$28 \core_calculate_stage_63_divisor_radicand$160 - connect \operation$29 \core_calculate_stage_63_operation$161 - connect \quotient_root$30 \core_calculate_stage_63_quotient_root$162 - connect \root_times_radicand$31 \core_calculate_stage_63_root_times_radicand$163 - connect \compare_lhs$32 \core_calculate_stage_63_compare_lhs$164 - connect \compare_rhs$33 \core_calculate_stage_63_compare_rhs$165 - end - process $group_0 - assign \core_calculate_stage_60_muxid 2'00 - assign \core_calculate_stage_60_muxid \muxid - sync init - end - process $group_1 - assign \core_calculate_stage_60_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_60_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_60_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_60_logical_op__rc__rc 1'0 - assign \core_calculate_stage_60_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_60_logical_op__oe__oe 1'0 - assign \core_calculate_stage_60_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_60_logical_op__invert_in 1'0 - assign \core_calculate_stage_60_logical_op__zero_a 1'0 - assign \core_calculate_stage_60_logical_op__input_carry 2'00 - assign \core_calculate_stage_60_logical_op__invert_out 1'0 - assign \core_calculate_stage_60_logical_op__write_cr0 1'0 - assign \core_calculate_stage_60_logical_op__output_carry 1'0 - assign \core_calculate_stage_60_logical_op__is_32bit 1'0 - assign \core_calculate_stage_60_logical_op__is_signed 1'0 - assign \core_calculate_stage_60_logical_op__data_len 4'0000 - assign \core_calculate_stage_60_logical_op__insn 32'00000000000000000000000000000000 - assign { \core_calculate_stage_60_logical_op__insn \core_calculate_stage_60_logical_op__data_len \core_calculate_stage_60_logical_op__is_signed \core_calculate_stage_60_logical_op__is_32bit \core_calculate_stage_60_logical_op__output_carry \core_calculate_stage_60_logical_op__write_cr0 \core_calculate_stage_60_logical_op__invert_out \core_calculate_stage_60_logical_op__input_carry \core_calculate_stage_60_logical_op__zero_a \core_calculate_stage_60_logical_op__invert_in { \core_calculate_stage_60_logical_op__oe__oe_ok \core_calculate_stage_60_logical_op__oe__oe } { \core_calculate_stage_60_logical_op__rc__rc_ok \core_calculate_stage_60_logical_op__rc__rc } { \core_calculate_stage_60_logical_op__imm_data__imm_ok \core_calculate_stage_60_logical_op__imm_data__imm } \core_calculate_stage_60_logical_op__fn_unit \core_calculate_stage_60_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \core_calculate_stage_60_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_ra \ra - sync init - end - process $group_20 - assign \core_calculate_stage_60_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_rb \rb - sync init - end - process $group_21 - assign \core_calculate_stage_60_xer_so 1'0 - assign \core_calculate_stage_60_xer_so \xer_so - sync init - end - process $group_22 - assign \core_calculate_stage_60_divisor_neg 1'0 - assign \core_calculate_stage_60_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \core_calculate_stage_60_dividend_neg 1'0 - assign \core_calculate_stage_60_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \core_calculate_stage_60_dive_abs_ov32 1'0 - assign \core_calculate_stage_60_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \core_calculate_stage_60_dive_abs_ov64 1'0 - assign \core_calculate_stage_60_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \core_calculate_stage_60_div_by_zero 1'0 - assign \core_calculate_stage_60_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \core_calculate_stage_60_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_divisor_radicand \divisor_radicand - sync init - end - process $group_28 - assign \core_calculate_stage_60_operation 2'00 - assign \core_calculate_stage_60_operation \operation - sync init - end - process $group_29 - assign \core_calculate_stage_60_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_quotient_root \quotient_root - sync init - end - process $group_30 - assign \core_calculate_stage_60_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_root_times_radicand \root_times_radicand - sync init - end - process $group_31 - assign \core_calculate_stage_60_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_compare_lhs \compare_lhs - sync init - end - process $group_32 - assign \core_calculate_stage_60_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_60_compare_rhs \compare_rhs - sync init - end - process $group_33 - assign \core_calculate_stage_61_muxid 2'00 - assign \core_calculate_stage_61_muxid \core_calculate_stage_60_muxid$34 - sync init - end - process $group_34 - assign \core_calculate_stage_61_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_61_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_61_logical_op__imm_data__imm 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\core_calculate_stage_60_logical_op__is_signed$50 \core_calculate_stage_60_logical_op__is_32bit$49 \core_calculate_stage_60_logical_op__output_carry$48 \core_calculate_stage_60_logical_op__write_cr0$47 \core_calculate_stage_60_logical_op__invert_out$46 \core_calculate_stage_60_logical_op__input_carry$45 \core_calculate_stage_60_logical_op__zero_a$44 \core_calculate_stage_60_logical_op__invert_in$43 { \core_calculate_stage_60_logical_op__oe__oe_ok$42 \core_calculate_stage_60_logical_op__oe__oe$41 } { \core_calculate_stage_60_logical_op__rc__rc_ok$40 \core_calculate_stage_60_logical_op__rc__rc$39 } { \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 \core_calculate_stage_60_logical_op__imm_data__imm$37 } \core_calculate_stage_60_logical_op__fn_unit$36 \core_calculate_stage_60_logical_op__insn_type$35 } - sync init - end - process $group_52 - assign \core_calculate_stage_61_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_61_ra 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\core_calculate_stage_60_compare_rhs$66 - sync init - end - process $group_66 - assign \core_calculate_stage_62_muxid 2'00 - assign \core_calculate_stage_62_muxid \core_calculate_stage_61_muxid$67 - sync init - end - process $group_67 - assign \core_calculate_stage_62_logical_op__insn_type 7'0000000 - assign \core_calculate_stage_62_logical_op__fn_unit 11'00000000000 - assign \core_calculate_stage_62_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_calculate_stage_62_logical_op__imm_data__imm_ok 1'0 - assign \core_calculate_stage_62_logical_op__rc__rc 1'0 - assign \core_calculate_stage_62_logical_op__rc__rc_ok 1'0 - assign \core_calculate_stage_62_logical_op__oe__oe 1'0 - assign \core_calculate_stage_62_logical_op__oe__oe_ok 1'0 - assign \core_calculate_stage_62_logical_op__invert_in 1'0 - assign \core_calculate_stage_62_logical_op__zero_a 1'0 - assign \core_calculate_stage_62_logical_op__input_carry 2'00 - assign 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\core_calculate_stage_62_logical_op__oe__oe } { \core_calculate_stage_62_logical_op__rc__rc_ok \core_calculate_stage_62_logical_op__rc__rc } { \core_calculate_stage_62_logical_op__imm_data__imm_ok \core_calculate_stage_62_logical_op__imm_data__imm } \core_calculate_stage_62_logical_op__fn_unit \core_calculate_stage_62_logical_op__insn_type } { \core_calculate_stage_61_logical_op__insn$85 \core_calculate_stage_61_logical_op__data_len$84 \core_calculate_stage_61_logical_op__is_signed$83 \core_calculate_stage_61_logical_op__is_32bit$82 \core_calculate_stage_61_logical_op__output_carry$81 \core_calculate_stage_61_logical_op__write_cr0$80 \core_calculate_stage_61_logical_op__invert_out$79 \core_calculate_stage_61_logical_op__input_carry$78 \core_calculate_stage_61_logical_op__zero_a$77 \core_calculate_stage_61_logical_op__invert_in$76 { \core_calculate_stage_61_logical_op__oe__oe_ok$75 \core_calculate_stage_61_logical_op__oe__oe$74 } { \core_calculate_stage_61_logical_op__rc__rc_ok$73 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\enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$170 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$179 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$187 - process $group_136 - assign \logical_op__insn_type$170 7'0000000 - assign \logical_op__fn_unit$171 11'00000000000 - assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$173 1'0 - assign \logical_op__rc__rc$174 1'0 - assign \logical_op__rc__rc_ok$175 1'0 - assign \logical_op__oe__oe$176 1'0 - assign \logical_op__oe__oe_ok$177 1'0 - assign \logical_op__invert_in$178 1'0 - assign \logical_op__zero_a$179 1'0 - assign \logical_op__input_carry$180 2'00 - assign \logical_op__invert_out$181 1'0 - assign \logical_op__write_cr0$182 1'0 - assign \logical_op__output_carry$183 1'0 - assign \logical_op__is_32bit$184 1'0 - assign \logical_op__is_signed$185 1'0 - assign \logical_op__data_len$186 4'0000 - assign \logical_op__insn$187 32'00000000000000000000000000000000 - assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_63_logical_op__insn$151 \core_calculate_stage_63_logical_op__data_len$150 \core_calculate_stage_63_logical_op__is_signed$149 \core_calculate_stage_63_logical_op__is_32bit$148 \core_calculate_stage_63_logical_op__output_carry$147 \core_calculate_stage_63_logical_op__write_cr0$146 \core_calculate_stage_63_logical_op__invert_out$145 \core_calculate_stage_63_logical_op__input_carry$144 \core_calculate_stage_63_logical_op__zero_a$143 \core_calculate_stage_63_logical_op__invert_in$142 { \core_calculate_stage_63_logical_op__oe__oe_ok$141 \core_calculate_stage_63_logical_op__oe__oe$140 } { \core_calculate_stage_63_logical_op__rc__rc_ok$139 \core_calculate_stage_63_logical_op__rc__rc$138 } { \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 \core_calculate_stage_63_logical_op__imm_data__imm$136 } \core_calculate_stage_63_logical_op__fn_unit$135 \core_calculate_stage_63_logical_op__insn_type$134 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$188 - process $group_154 - assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$188 \core_calculate_stage_63_ra$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$189 - process $group_155 - assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$189 \core_calculate_stage_63_rb$153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$190 - process $group_156 - assign \xer_so$190 1'0 - assign \xer_so$190 \core_calculate_stage_63_xer_so$154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$191 - process $group_157 - assign \divisor_neg$191 1'0 - assign \divisor_neg$191 \core_calculate_stage_63_divisor_neg$155 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$192 - process $group_158 - assign \dividend_neg$192 1'0 - assign \dividend_neg$192 \core_calculate_stage_63_dividend_neg$156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$193 - process $group_159 - assign \dive_abs_ov32$193 1'0 - assign \dive_abs_ov32$193 \core_calculate_stage_63_dive_abs_ov32$157 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$194 - process $group_160 - assign \dive_abs_ov64$194 1'0 - assign \dive_abs_ov64$194 \core_calculate_stage_63_dive_abs_ov64$158 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$195 - process $group_161 - assign \div_by_zero$195 1'0 - assign \div_by_zero$195 \core_calculate_stage_63_div_by_zero$159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \divisor_radicand$196 - process $group_162 - assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$196 \core_calculate_stage_63_divisor_radicand$160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \operation$197 - process $group_163 - assign \operation$197 2'00 - assign \operation$197 \core_calculate_stage_63_operation$161 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \quotient_root$198 - process $group_164 - assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$198 \core_calculate_stage_63_quotient_root$162 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \root_times_radicand$199 - process $group_165 - assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \root_times_radicand$199 \core_calculate_stage_63_root_times_radicand$163 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \compare_lhs$200 - process $group_166 - assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_lhs$200 \core_calculate_stage_63_compare_lhs$164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \compare_rhs$201 - process $group_167 - assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \compare_rhs$201 \core_calculate_stage_63_compare_rhs$165 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_168 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_169 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$169 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_170 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_188 - assign \ra$20$next \ra$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$20$next \ra$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$20$next \ra$188 - end - sync init - update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$20 \ra$20$next - end - process $group_189 - assign \rb$21$next \rb$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$21$next \rb$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$21$next \rb$189 - end - sync init - update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$21 \rb$21$next - end - process $group_190 - assign \xer_so$22$next \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$22$next \xer_so$190 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$22$next \xer_so$190 - end - sync init - update \xer_so$22 1'0 - sync posedge \coresync_clk - update \xer_so$22 \xer_so$22$next - end - process $group_191 - assign \divisor_neg$23$next \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$23$next \divisor_neg$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$23$next \divisor_neg$191 - end - sync init - update \divisor_neg$23 1'0 - sync posedge \coresync_clk - update \divisor_neg$23 \divisor_neg$23$next - end - process $group_192 - assign \dividend_neg$24$next \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$24$next \dividend_neg$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$24$next \dividend_neg$192 - end - sync init - update \dividend_neg$24 1'0 - sync posedge \coresync_clk - update \dividend_neg$24 \dividend_neg$24$next - end - process $group_193 - assign \dive_abs_ov32$25$next \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$25$next \dive_abs_ov32$193 - end - sync init - update \dive_abs_ov32$25 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$25 \dive_abs_ov32$25$next - end - process $group_194 - assign \dive_abs_ov64$26$next \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$26$next \dive_abs_ov64$194 - end - sync init - update \dive_abs_ov64$26 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$26 \dive_abs_ov64$26$next - end - process $group_195 - assign \div_by_zero$27$next \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$27$next \div_by_zero$195 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$27$next \div_by_zero$195 - end - sync init - update \div_by_zero$27 1'0 - sync posedge \coresync_clk - update \div_by_zero$27 \div_by_zero$27$next - end - process $group_196 - assign \divisor_radicand$28$next \divisor_radicand$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$28$next \divisor_radicand$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$28$next \divisor_radicand$196 - end - sync init - update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$28 \divisor_radicand$28$next - end - process $group_197 - assign \operation$29$next \operation$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$29$next \operation$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$29$next \operation$197 - end - sync init - update \operation$29 2'00 - sync posedge \coresync_clk - update \operation$29 \operation$29$next - end - process $group_198 - assign \quotient_root$30$next \quotient_root$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \quotient_root$30$next \quotient_root$198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \quotient_root$30$next \quotient_root$198 - end - sync init - update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \quotient_root$30 \quotient_root$30$next - end - process $group_199 - assign \root_times_radicand$31$next \root_times_radicand$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \root_times_radicand$31$next \root_times_radicand$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \root_times_radicand$31$next \root_times_radicand$199 - end - sync init - update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \root_times_radicand$31 \root_times_radicand$31$next - end - process $group_200 - assign \compare_lhs$32$next \compare_lhs$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_lhs$32$next \compare_lhs$200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_lhs$32$next \compare_lhs$200 - end - sync init - update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_lhs$32 \compare_lhs$32$next - end - process $group_201 - assign \compare_rhs$33$next \compare_rhs$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \compare_rhs$33$next \compare_rhs$201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \compare_rhs$33$next \compare_rhs$201 - end - sync init - update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \compare_rhs$33 \compare_rhs$33$next - end - process $group_202 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_203 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" -module \p$362 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" -module \n$363 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.core_final_stage.core" -module \core$364 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 0 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 1 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 2 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" - wire width 64 output 3 \quotient_root$1 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" - wire width 192 output 4 \remainder - process $group_0 - assign \quotient_root$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root$1 \quotient_root - sync init - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" - wire width 193 $2 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" - wire width 193 $3 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" - cell $sub $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \B_SIGNED 0 - parameter \B_WIDTH 192 - parameter \Y_WIDTH 193 - connect \A \compare_lhs - connect \B \compare_rhs - connect \Y $3 - end - connect $2 $3 - process $group_1 - assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \remainder $2 [191:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.core_final_stage" -module \core_final_stage - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 22 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 23 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 24 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 25 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 26 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 27 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 28 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 29 \quotient_root - attribute \src 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 20 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 21 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 22 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 23 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 24 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" - wire width 64 input 25 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" - wire width 192 input 26 \remainder - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 44 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" - wire width 1 \quotient_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dividend_neg - connect \B \divisor_neg - connect \Y $21 - end - process $group_0 - assign \quotient_neg 1'0 - assign \quotient_neg $21 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" - wire width 1 \remainder_neg - process $group_1 - assign \remainder_neg 1'0 - assign \remainder_neg \dividend_neg - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" - wire width 65 \quotient_65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" - wire width 65 $25 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" - cell $pos $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $28 - parameter \WIDTH 65 - connect \A $25 - connect \B $23 - connect \S \quotient_neg - connect \Y $27 - end - process $group_2 - assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_65 $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" - wire width 64 \remainder_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $35 - parameter \WIDTH 65 - connect \A $32 - connect \B $30 - connect \S \remainder_neg - connect \Y $34 - end - connect $29 $34 - process $group_3 - assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \remainder_64 $29 [63:0] - sync init - end - wire width 1 $verilog_initial_trigger - process $group_4 - assign \xer_ov_ok 1'0 - assign \xer_ov_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" - wire width 1 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_32bit - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_signed - connect \B $38 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [32] - connect \B \quotient_65 [31] - connect \Y $42 - end - process $group_5 - assign \ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed $36 \div_by_zero } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - case 3'--1 - assign \ov 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - case 3'-1- - assign \ov \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch { $40 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" - case 3'1-- - assign \ov \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch { $42 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" - case - assign \ov \dive_abs_ov32 - end - sync init - end - process $group_6 - assign \xer_ov 2'00 - assign \xer_ov { \ov \ov } - sync init - end - process $group_7 - assign \o_ok 1'0 - assign \o_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - cell $not $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ov - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - wire width 64 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - wire width 64 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - wire width 64 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - wire width 64 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - wire width 64 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - cell $pos $55 - parameter \A_SIGNED 1 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $54 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - wire width 64 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $56 - end - process $group_8 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" - attribute \nmigen.decoding "OP_DIVE/30" - case 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - switch { \logical_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - case 1'1 - assign \o $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" - case - assign \o $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" - case - assign \o \quotient_65 [63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" - attribute \nmigen.decoding "OP_DIV/29" - case 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" - switch { 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $27 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $30 - end - process $group_0 - assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - case 1'1 - assign \o$25 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - case - assign \o$25 $30 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$25 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $32 - end - process $group_2 - assign \is_cmp 1'0 - assign \is_cmp $32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $34 - end - process $group_3 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_4 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $36 - end - process $group_5 - assign \is_nzero 1'0 - assign \is_nzero $36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $38 - connect \Y $40 - end - process $group_6 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $40 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $42 - connect \Y $44 - end - process $group_7 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $46 - end - process $group_8 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - case - assign \cr0 { \is_negative \is_positive $46 \xer_so$24 } - end - sync init - end - process $group_9 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$25 [63:0] - sync init - end - process $group_10 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok - sync init - end - process $group_11 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 - sync init - end - process $group_12 - assign \cr_a_ok 1'0 - assign \cr_a_ok \logical_op__write_cr0 - sync init - end - process $group_13 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_14 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__oe_ok - connect \Y $48 - end - process $group_32 - assign \oe 1'0 - assign \oe $48 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $50 - end - process $group_33 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $50 - end - sync init - end - process $group_34 - assign \xer_so$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so$24 \so - end - sync init - end - process $group_35 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so_ok 1'1 - end - sync init - end - process $group_36 - assign \xer_ov$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov$23 \xer_ov - end - sync init - end - process $group_37 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" -module \pipe_end - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:102" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - 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width 64 input 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - 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input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 input 31 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 input 32 \operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 input 33 \quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 input 34 \root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 input 35 \compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 input 36 \compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 37 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 38 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 39 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute 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\enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 40 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 41 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 42 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 50 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 53 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 54 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 55 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 56 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 57 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 58 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 59 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 60 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 61 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 62 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 63 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 64 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 65 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - cell \p$362 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$363 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_final_stage_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \core_final_stage_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_final_stage_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__is_32bit - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_final_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_final_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_final_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \core_final_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \core_final_stage_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \core_final_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \core_final_stage_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \core_final_stage_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \core_final_stage_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \core_final_stage_muxid$21 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute 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\enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \core_final_stage_logical_op__insn_type$22 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute 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1 \core_final_stage_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__oe__oe_ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__zero_a$31 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \core_final_stage_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \core_final_stage_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \core_final_stage_logical_op__data_len$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \core_final_stage_logical_op__insn$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_final_stage_ra$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \core_final_stage_rb$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \core_final_stage_xer_so$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \core_final_stage_divisor_neg$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \core_final_stage_dividend_neg$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \core_final_stage_dive_abs_ov32$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \core_final_stage_dive_abs_ov64$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \core_final_stage_div_by_zero$47 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" - wire width 64 \core_final_stage_quotient_root$48 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" - wire width 192 \core_final_stage_remainder - cell \core_final_stage \core_final_stage - connect \muxid \core_final_stage_muxid - connect \logical_op__insn_type \core_final_stage_logical_op__insn_type - connect \logical_op__fn_unit \core_final_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \core_final_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \core_final_stage_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \core_final_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \core_final_stage_logical_op__rc__rc_ok - connect \logical_op__oe__oe \core_final_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \core_final_stage_logical_op__oe__oe_ok - connect \logical_op__invert_in \core_final_stage_logical_op__invert_in - connect \logical_op__zero_a \core_final_stage_logical_op__zero_a - connect \logical_op__input_carry \core_final_stage_logical_op__input_carry - connect \logical_op__invert_out \core_final_stage_logical_op__invert_out - connect \logical_op__write_cr0 \core_final_stage_logical_op__write_cr0 - connect \logical_op__output_carry \core_final_stage_logical_op__output_carry - connect \logical_op__is_32bit \core_final_stage_logical_op__is_32bit - connect \logical_op__is_signed \core_final_stage_logical_op__is_signed - connect \logical_op__data_len \core_final_stage_logical_op__data_len - connect \logical_op__insn \core_final_stage_logical_op__insn - connect \ra \core_final_stage_ra - connect \rb \core_final_stage_rb - connect \xer_so \core_final_stage_xer_so - connect \divisor_neg \core_final_stage_divisor_neg - connect \dividend_neg \core_final_stage_dividend_neg - connect \dive_abs_ov32 \core_final_stage_dive_abs_ov32 - connect \dive_abs_ov64 \core_final_stage_dive_abs_ov64 - connect \div_by_zero \core_final_stage_div_by_zero - connect \divisor_radicand \core_final_stage_divisor_radicand - connect \operation \core_final_stage_operation - connect \quotient_root \core_final_stage_quotient_root - connect \root_times_radicand \core_final_stage_root_times_radicand - connect \compare_lhs \core_final_stage_compare_lhs - connect \compare_rhs \core_final_stage_compare_rhs - connect \muxid$1 \core_final_stage_muxid$21 - connect \logical_op__insn_type$2 \core_final_stage_logical_op__insn_type$22 - connect \logical_op__fn_unit$3 \core_final_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__imm$4 \core_final_stage_logical_op__imm_data__imm$24 - connect \logical_op__imm_data__imm_ok$5 \core_final_stage_logical_op__imm_data__imm_ok$25 - connect \logical_op__rc__rc$6 \core_final_stage_logical_op__rc__rc$26 - connect \logical_op__rc__rc_ok$7 \core_final_stage_logical_op__rc__rc_ok$27 - connect \logical_op__oe__oe$8 \core_final_stage_logical_op__oe__oe$28 - connect \logical_op__oe__oe_ok$9 \core_final_stage_logical_op__oe__oe_ok$29 - connect \logical_op__invert_in$10 \core_final_stage_logical_op__invert_in$30 - connect \logical_op__zero_a$11 \core_final_stage_logical_op__zero_a$31 - connect \logical_op__input_carry$12 \core_final_stage_logical_op__input_carry$32 - connect \logical_op__invert_out$13 \core_final_stage_logical_op__invert_out$33 - connect \logical_op__write_cr0$14 \core_final_stage_logical_op__write_cr0$34 - connect \logical_op__output_carry$15 \core_final_stage_logical_op__output_carry$35 - connect \logical_op__is_32bit$16 \core_final_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed$17 \core_final_stage_logical_op__is_signed$37 - connect \logical_op__data_len$18 \core_final_stage_logical_op__data_len$38 - connect \logical_op__insn$19 \core_final_stage_logical_op__insn$39 - connect \ra$20 \core_final_stage_ra$40 - connect \rb$21 \core_final_stage_rb$41 - connect \xer_so$22 \core_final_stage_xer_so$42 - connect \divisor_neg$23 \core_final_stage_divisor_neg$43 - connect \dividend_neg$24 \core_final_stage_dividend_neg$44 - connect \dive_abs_ov32$25 \core_final_stage_dive_abs_ov32$45 - connect \dive_abs_ov64$26 \core_final_stage_dive_abs_ov64$46 - connect \div_by_zero$27 \core_final_stage_div_by_zero$47 - connect \quotient_root$28 \core_final_stage_quotient_root$48 - connect \remainder \core_final_stage_remainder - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_stage_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - 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\output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$67 \output_stage_logical_op__data_len$66 \output_stage_logical_op__is_signed$65 \output_stage_logical_op__is_32bit$64 \output_stage_logical_op__output_carry$63 \output_stage_logical_op__write_cr0$62 \output_stage_logical_op__invert_out$61 \output_stage_logical_op__input_carry$60 \output_stage_logical_op__zero_a$59 \output_stage_logical_op__invert_in$58 { \output_stage_logical_op__oe__oe_ok$57 \output_stage_logical_op__oe__oe$56 } { \output_stage_logical_op__rc__rc_ok$55 \output_stage_logical_op__rc__rc$54 } { \output_stage_logical_op__imm_data__imm_ok$53 \output_stage_logical_op__imm_data__imm$52 } \output_stage_logical_op__fn_unit$51 \output_stage_logical_op__insn_type$50 } - sync init - end - process $group_81 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$97 - process $group_83 - assign \output_cr_a 4'0000 - assign \cr_a_ok$95 1'0 - assign { \cr_a_ok$95 \output_cr_a } { \cr_a_ok$97 \cr_a$96 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$98 - process $group_85 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$98 1'0 - assign { \xer_ov_ok$98 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$100 - process $group_87 - assign \output_xer_so 1'0 - assign \xer_so_ok$99 1'0 - assign { \xer_so_ok$99 \output_xer_so } { \xer_so_ok$100 \output_stage_xer_so$68 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$101 - process $group_89 - assign \p_valid_i$101 1'0 - assign \p_valid_i$101 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_90 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$101 - connect \B \p_ready_o - connect \Y $102 - end - process $group_91 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $102 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$104 - process $group_92 - assign \muxid$104 2'00 - assign \muxid$104 \output_muxid$69 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$105 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$114 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$122 - process $group_93 - assign \logical_op__insn_type$105 7'0000000 - assign \logical_op__fn_unit$106 11'00000000000 - assign \logical_op__imm_data__imm$107 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$108 1'0 - assign \logical_op__rc__rc$109 1'0 - assign \logical_op__rc__rc_ok$110 1'0 - assign \logical_op__oe__oe$111 1'0 - assign \logical_op__oe__oe_ok$112 1'0 - assign \logical_op__invert_in$113 1'0 - assign \logical_op__zero_a$114 1'0 - assign \logical_op__input_carry$115 2'00 - assign \logical_op__invert_out$116 1'0 - assign \logical_op__write_cr0$117 1'0 - assign \logical_op__output_carry$118 1'0 - assign \logical_op__is_32bit$119 1'0 - assign \logical_op__is_signed$120 1'0 - assign \logical_op__data_len$121 4'0000 - assign \logical_op__insn$122 32'00000000000000000000000000000000 - assign { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } { \output_logical_op__insn$87 \output_logical_op__data_len$86 \output_logical_op__is_signed$85 \output_logical_op__is_32bit$84 \output_logical_op__output_carry$83 \output_logical_op__write_cr0$82 \output_logical_op__invert_out$81 \output_logical_op__input_carry$80 \output_logical_op__zero_a$79 \output_logical_op__invert_in$78 { \output_logical_op__oe__oe_ok$77 \output_logical_op__oe__oe$76 } { \output_logical_op__rc__rc_ok$75 \output_logical_op__rc__rc$74 } { \output_logical_op__imm_data__imm_ok$73 \output_logical_op__imm_data__imm$72 } \output_logical_op__fn_unit$71 \output_logical_op__insn_type$70 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$124 - process $group_111 - assign \o$123 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$124 1'0 - assign { \o_ok$124 \o$123 } { \output_o_ok$89 \output_o$88 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$126 - process $group_113 - assign \cr_a$125 4'0000 - assign \cr_a_ok$126 1'0 - assign { \cr_a_ok$126 \cr_a$125 } { \output_cr_a_ok \output_cr_a$90 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$128 - process $group_115 - assign \xer_ov$127 2'00 - assign \xer_ov_ok$128 1'0 - assign { \xer_ov_ok$128 \xer_ov$127 } { \output_xer_ov_ok \output_xer_ov$91 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$130 - process $group_117 - assign \xer_so$129 1'0 - assign \xer_so_ok$130 1'0 - assign { \xer_so_ok$130 \xer_so$129 } { \output_xer_so_ok \output_xer_so$92 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_119 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_120 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$104 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$104 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_121 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_139 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$124 \o$123 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$124 \o$123 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_141 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$126 \cr_a$125 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$126 \cr_a$125 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_143 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$128 \xer_ov$127 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$128 \xer_ov$127 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_145 - assign \xer_so$20$next \xer_so$20 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$130 \xer_so$129 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$130 \xer_so$129 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$20 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$20 \xer_so$20$next - update \xer_so_ok \xer_so_ok$next - end - process $group_147 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_148 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$96 4'0000 - connect \cr_a_ok$97 1'0 - connect \xer_so_ok$100 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" -module \alu_div0 - attribute \src "simple/issuer.py:102" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:102" - wire width 1 input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 7 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 9 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 24 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 25 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 27 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 28 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 34 \p_ready_o - cell \p$71 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$72 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_start_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_start_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_start_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_start_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_start_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_start_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_start_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_start_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_start_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_start_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_start_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_start_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_start_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_start_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_start_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_start_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_start_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_start_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_start_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type$3 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_start_logical_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__zero_a$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_start_logical_op__input_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__output_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_32bit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_signed$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_start_logical_op__insn$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_start_xer_so$23 - cell \pipe_start \pipe_start - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \pipe_start_n_valid_o - connect \n_ready_i \pipe_start_n_ready_i - connect \muxid \pipe_start_muxid - connect \logical_op__insn_type \pipe_start_logical_op__insn_type - connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_start_logical_op__invert_in - connect \logical_op__zero_a \pipe_start_logical_op__zero_a - connect \logical_op__input_carry \pipe_start_logical_op__input_carry - connect \logical_op__invert_out \pipe_start_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_start_logical_op__output_carry - connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit - connect \logical_op__is_signed \pipe_start_logical_op__is_signed - connect \logical_op__data_len \pipe_start_logical_op__data_len - connect \logical_op__insn \pipe_start_logical_op__insn - connect \ra \pipe_start_ra - connect \rb \pipe_start_rb - connect \xer_so \pipe_start_xer_so - connect \divisor_neg \pipe_start_divisor_neg - connect \dividend_neg \pipe_start_dividend_neg - connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \div_by_zero \pipe_start_div_by_zero - connect \divisor_radicand \pipe_start_divisor_radicand - connect \operation \pipe_start_operation - connect \quotient_root \pipe_start_quotient_root - connect \root_times_radicand \pipe_start_root_times_radicand - connect \compare_lhs \pipe_start_compare_lhs - connect \compare_rhs \pipe_start_compare_rhs - connect \p_valid_i \pipe_start_p_valid_i - connect \p_ready_o \pipe_start_p_ready_o - connect \muxid$1 \pipe_start_muxid$2 - connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 - connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5 - connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6 - connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8 - connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10 - connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 - connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 - connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 - connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 - connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 - connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 - connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 - connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 - connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 - connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 - connect \ra$20 \pipe_start_ra$21 - connect \rb$21 \pipe_start_rb$22 - connect \xer_so$22 \pipe_start_xer_so$23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_0_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_0_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_0_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_0_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_0_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_0_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid$24 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_0_logical_op__insn_type$25 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_0_logical_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero$50 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_0_divisor_radicand$51 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_0_operation$52 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_0_quotient_root$53 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_0_root_times_radicand$54 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_0_compare_lhs$55 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_0_compare_rhs$56 - cell \pipe_middle_0 \pipe_middle_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_0_p_valid_i - connect \p_ready_o \pipe_middle_0_p_ready_o - connect \muxid \pipe_middle_0_muxid - connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_0_logical_op__data_len - connect \logical_op__insn \pipe_middle_0_logical_op__insn - connect \ra \pipe_middle_0_ra - connect \rb \pipe_middle_0_rb - connect \xer_so \pipe_middle_0_xer_so - connect \divisor_neg \pipe_middle_0_divisor_neg - connect \dividend_neg \pipe_middle_0_dividend_neg - connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 - connect \div_by_zero \pipe_middle_0_div_by_zero - connect \divisor_radicand \pipe_middle_0_divisor_radicand - connect \operation \pipe_middle_0_operation - connect \quotient_root \pipe_middle_0_quotient_root - connect \root_times_radicand \pipe_middle_0_root_times_radicand - connect \compare_lhs \pipe_middle_0_compare_lhs - connect \compare_rhs \pipe_middle_0_compare_rhs - connect \n_valid_o \pipe_middle_0_n_valid_o - connect \n_ready_i \pipe_middle_0_n_ready_i - connect \muxid$1 \pipe_middle_0_muxid$24 - connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 - connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28 - connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30 - connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32 - connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 - connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 - connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 - connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 - connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 - connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 - connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 - connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 - connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 - connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 - connect \ra$20 \pipe_middle_0_ra$43 - connect \rb$21 \pipe_middle_0_rb$44 - connect \xer_so$22 \pipe_middle_0_xer_so$45 - connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 - connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 - connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 - connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 - connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 - connect \divisor_radicand$28 \pipe_middle_0_divisor_radicand$51 - connect \operation$29 \pipe_middle_0_operation$52 - connect \quotient_root$30 \pipe_middle_0_quotient_root$53 - connect \root_times_radicand$31 \pipe_middle_0_root_times_radicand$54 - connect \compare_lhs$32 \pipe_middle_0_compare_lhs$55 - connect \compare_rhs$33 \pipe_middle_0_compare_rhs$56 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_1_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_1_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_1_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_1_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_1_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_1_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_1_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_1_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_1_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_1_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_1_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_1_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_1_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_1_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_1_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_1_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_1_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_1_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_1_muxid$57 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_1_logical_op__insn_type$58 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_1_logical_op__fn_unit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_1_logical_op__imm_data__imm$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__imm_data__imm_ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__rc__rc$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__rc__rc_ok$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__oe__oe$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__oe__oe_ok$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__invert_in$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__zero_a$67 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_1_logical_op__input_carry$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__invert_out$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__write_cr0$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__output_carry$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__is_32bit$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_1_logical_op__is_signed$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_1_logical_op__data_len$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_1_logical_op__insn$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_1_ra$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_1_rb$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_1_xer_so$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_1_divisor_neg$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_1_dividend_neg$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_1_dive_abs_ov32$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_1_dive_abs_ov64$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_1_div_by_zero$83 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_1_divisor_radicand$84 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_1_operation$85 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_1_quotient_root$86 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_1_root_times_radicand$87 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_1_compare_lhs$88 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_1_compare_rhs$89 - cell \pipe_middle_1 \pipe_middle_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_1_p_valid_i - connect \p_ready_o \pipe_middle_1_p_ready_o - connect \muxid \pipe_middle_1_muxid - connect \logical_op__insn_type \pipe_middle_1_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_1_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_1_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_1_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_1_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_1_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_1_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_1_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_1_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_1_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_1_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_1_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_1_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_1_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_1_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_1_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_1_logical_op__data_len - connect \logical_op__insn \pipe_middle_1_logical_op__insn - connect \ra \pipe_middle_1_ra - connect \rb \pipe_middle_1_rb - connect \xer_so \pipe_middle_1_xer_so - connect \divisor_neg \pipe_middle_1_divisor_neg - connect \dividend_neg \pipe_middle_1_dividend_neg - connect \dive_abs_ov32 \pipe_middle_1_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_1_dive_abs_ov64 - connect \div_by_zero \pipe_middle_1_div_by_zero - connect \divisor_radicand \pipe_middle_1_divisor_radicand - connect \operation \pipe_middle_1_operation - connect \quotient_root \pipe_middle_1_quotient_root - connect \root_times_radicand \pipe_middle_1_root_times_radicand - connect \compare_lhs \pipe_middle_1_compare_lhs - connect \compare_rhs \pipe_middle_1_compare_rhs - connect \n_valid_o \pipe_middle_1_n_valid_o - connect \n_ready_i \pipe_middle_1_n_ready_i - connect \muxid$1 \pipe_middle_1_muxid$57 - connect \logical_op__insn_type$2 \pipe_middle_1_logical_op__insn_type$58 - connect \logical_op__fn_unit$3 \pipe_middle_1_logical_op__fn_unit$59 - connect \logical_op__imm_data__imm$4 \pipe_middle_1_logical_op__imm_data__imm$60 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_1_logical_op__imm_data__imm_ok$61 - connect \logical_op__rc__rc$6 \pipe_middle_1_logical_op__rc__rc$62 - connect \logical_op__rc__rc_ok$7 \pipe_middle_1_logical_op__rc__rc_ok$63 - connect \logical_op__oe__oe$8 \pipe_middle_1_logical_op__oe__oe$64 - connect \logical_op__oe__oe_ok$9 \pipe_middle_1_logical_op__oe__oe_ok$65 - connect \logical_op__invert_in$10 \pipe_middle_1_logical_op__invert_in$66 - connect \logical_op__zero_a$11 \pipe_middle_1_logical_op__zero_a$67 - connect \logical_op__input_carry$12 \pipe_middle_1_logical_op__input_carry$68 - connect \logical_op__invert_out$13 \pipe_middle_1_logical_op__invert_out$69 - connect \logical_op__write_cr0$14 \pipe_middle_1_logical_op__write_cr0$70 - connect \logical_op__output_carry$15 \pipe_middle_1_logical_op__output_carry$71 - connect \logical_op__is_32bit$16 \pipe_middle_1_logical_op__is_32bit$72 - connect \logical_op__is_signed$17 \pipe_middle_1_logical_op__is_signed$73 - connect \logical_op__data_len$18 \pipe_middle_1_logical_op__data_len$74 - connect \logical_op__insn$19 \pipe_middle_1_logical_op__insn$75 - connect \ra$20 \pipe_middle_1_ra$76 - connect \rb$21 \pipe_middle_1_rb$77 - connect \xer_so$22 \pipe_middle_1_xer_so$78 - connect \divisor_neg$23 \pipe_middle_1_divisor_neg$79 - connect \dividend_neg$24 \pipe_middle_1_dividend_neg$80 - connect \dive_abs_ov32$25 \pipe_middle_1_dive_abs_ov32$81 - connect \dive_abs_ov64$26 \pipe_middle_1_dive_abs_ov64$82 - connect \div_by_zero$27 \pipe_middle_1_div_by_zero$83 - connect \divisor_radicand$28 \pipe_middle_1_divisor_radicand$84 - connect \operation$29 \pipe_middle_1_operation$85 - connect \quotient_root$30 \pipe_middle_1_quotient_root$86 - connect \root_times_radicand$31 \pipe_middle_1_root_times_radicand$87 - connect \compare_lhs$32 \pipe_middle_1_compare_lhs$88 - connect \compare_rhs$33 \pipe_middle_1_compare_rhs$89 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_2_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_2_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_2_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_2_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_2_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_2_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_2_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_2_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_2_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_2_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_2_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_2_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_2_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_2_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_2_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_2_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_2_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_2_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_2_muxid$90 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_2_logical_op__insn_type$91 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_2_logical_op__fn_unit$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_2_logical_op__imm_data__imm$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__imm_data__imm_ok$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__rc__rc$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__rc__rc_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__oe__oe$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__oe__oe_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__invert_in$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__zero_a$100 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_2_logical_op__input_carry$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__invert_out$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__write_cr0$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__output_carry$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__is_32bit$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_2_logical_op__is_signed$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_2_logical_op__data_len$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_2_logical_op__insn$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_2_ra$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_2_rb$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_2_xer_so$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_2_divisor_neg$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_2_dividend_neg$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_2_dive_abs_ov32$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_2_dive_abs_ov64$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_2_div_by_zero$116 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_2_divisor_radicand$117 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_2_operation$118 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_2_quotient_root$119 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_2_root_times_radicand$120 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_2_compare_lhs$121 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_2_compare_rhs$122 - cell \pipe_middle_2 \pipe_middle_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_2_p_valid_i - connect \p_ready_o \pipe_middle_2_p_ready_o - connect \muxid \pipe_middle_2_muxid - connect \logical_op__insn_type \pipe_middle_2_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_2_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_2_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_2_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_2_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_2_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_2_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_2_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_2_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_2_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_2_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_2_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_2_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_2_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_2_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_2_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_2_logical_op__data_len - connect \logical_op__insn \pipe_middle_2_logical_op__insn - connect \ra \pipe_middle_2_ra - connect \rb \pipe_middle_2_rb - connect \xer_so \pipe_middle_2_xer_so - connect \divisor_neg \pipe_middle_2_divisor_neg - connect \dividend_neg \pipe_middle_2_dividend_neg - connect \dive_abs_ov32 \pipe_middle_2_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_2_dive_abs_ov64 - connect \div_by_zero \pipe_middle_2_div_by_zero - connect \divisor_radicand \pipe_middle_2_divisor_radicand - connect \operation \pipe_middle_2_operation - connect \quotient_root \pipe_middle_2_quotient_root - connect \root_times_radicand \pipe_middle_2_root_times_radicand - connect \compare_lhs \pipe_middle_2_compare_lhs - connect \compare_rhs \pipe_middle_2_compare_rhs - connect \n_valid_o \pipe_middle_2_n_valid_o - connect \n_ready_i \pipe_middle_2_n_ready_i - connect \muxid$1 \pipe_middle_2_muxid$90 - connect \logical_op__insn_type$2 \pipe_middle_2_logical_op__insn_type$91 - connect \logical_op__fn_unit$3 \pipe_middle_2_logical_op__fn_unit$92 - connect \logical_op__imm_data__imm$4 \pipe_middle_2_logical_op__imm_data__imm$93 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_2_logical_op__imm_data__imm_ok$94 - connect \logical_op__rc__rc$6 \pipe_middle_2_logical_op__rc__rc$95 - connect \logical_op__rc__rc_ok$7 \pipe_middle_2_logical_op__rc__rc_ok$96 - connect \logical_op__oe__oe$8 \pipe_middle_2_logical_op__oe__oe$97 - connect \logical_op__oe__oe_ok$9 \pipe_middle_2_logical_op__oe__oe_ok$98 - connect \logical_op__invert_in$10 \pipe_middle_2_logical_op__invert_in$99 - connect \logical_op__zero_a$11 \pipe_middle_2_logical_op__zero_a$100 - connect \logical_op__input_carry$12 \pipe_middle_2_logical_op__input_carry$101 - connect \logical_op__invert_out$13 \pipe_middle_2_logical_op__invert_out$102 - connect \logical_op__write_cr0$14 \pipe_middle_2_logical_op__write_cr0$103 - connect \logical_op__output_carry$15 \pipe_middle_2_logical_op__output_carry$104 - connect \logical_op__is_32bit$16 \pipe_middle_2_logical_op__is_32bit$105 - connect \logical_op__is_signed$17 \pipe_middle_2_logical_op__is_signed$106 - connect \logical_op__data_len$18 \pipe_middle_2_logical_op__data_len$107 - connect \logical_op__insn$19 \pipe_middle_2_logical_op__insn$108 - connect \ra$20 \pipe_middle_2_ra$109 - connect \rb$21 \pipe_middle_2_rb$110 - connect \xer_so$22 \pipe_middle_2_xer_so$111 - connect \divisor_neg$23 \pipe_middle_2_divisor_neg$112 - connect \dividend_neg$24 \pipe_middle_2_dividend_neg$113 - connect \dive_abs_ov32$25 \pipe_middle_2_dive_abs_ov32$114 - connect \dive_abs_ov64$26 \pipe_middle_2_dive_abs_ov64$115 - connect \div_by_zero$27 \pipe_middle_2_div_by_zero$116 - connect \divisor_radicand$28 \pipe_middle_2_divisor_radicand$117 - connect \operation$29 \pipe_middle_2_operation$118 - connect \quotient_root$30 \pipe_middle_2_quotient_root$119 - connect \root_times_radicand$31 \pipe_middle_2_root_times_radicand$120 - connect \compare_lhs$32 \pipe_middle_2_compare_lhs$121 - connect \compare_rhs$33 \pipe_middle_2_compare_rhs$122 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_3_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_3_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_3_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_3_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_3_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_3_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_3_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_3_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_3_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_3_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_3_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_3_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_3_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_3_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_3_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_3_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_3_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_3_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_3_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_3_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_3_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_3_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_3_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_3_muxid$123 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_3_logical_op__insn_type$124 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_3_logical_op__fn_unit$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_3_logical_op__imm_data__imm$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__imm_data__imm_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__rc__rc$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__rc__rc_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__oe__oe$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__oe__oe_ok$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__invert_in$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__zero_a$133 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_3_logical_op__input_carry$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__invert_out$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__write_cr0$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__output_carry$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__is_32bit$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_3_logical_op__is_signed$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_3_logical_op__data_len$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_3_logical_op__insn$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_3_ra$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_3_rb$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_3_xer_so$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_3_divisor_neg$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_3_dividend_neg$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_3_dive_abs_ov32$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_3_dive_abs_ov64$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_3_div_by_zero$149 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_3_divisor_radicand$150 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_3_operation$151 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_3_quotient_root$152 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_3_root_times_radicand$153 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_3_compare_lhs$154 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_3_compare_rhs$155 - cell \pipe_middle_3 \pipe_middle_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_3_p_valid_i - connect \p_ready_o \pipe_middle_3_p_ready_o - connect \muxid \pipe_middle_3_muxid - connect \logical_op__insn_type \pipe_middle_3_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_3_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_3_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_3_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_3_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_3_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_3_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_3_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_3_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_3_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_3_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_3_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_3_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_3_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_3_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_3_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_3_logical_op__data_len - connect \logical_op__insn \pipe_middle_3_logical_op__insn - connect \ra \pipe_middle_3_ra - connect \rb \pipe_middle_3_rb - connect \xer_so \pipe_middle_3_xer_so - connect \divisor_neg \pipe_middle_3_divisor_neg - connect \dividend_neg \pipe_middle_3_dividend_neg - connect \dive_abs_ov32 \pipe_middle_3_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_3_dive_abs_ov64 - connect \div_by_zero \pipe_middle_3_div_by_zero - connect \divisor_radicand \pipe_middle_3_divisor_radicand - connect \operation \pipe_middle_3_operation - connect \quotient_root \pipe_middle_3_quotient_root - connect \root_times_radicand \pipe_middle_3_root_times_radicand - connect \compare_lhs \pipe_middle_3_compare_lhs - connect \compare_rhs \pipe_middle_3_compare_rhs - connect \n_valid_o \pipe_middle_3_n_valid_o - connect \n_ready_i \pipe_middle_3_n_ready_i - connect \muxid$1 \pipe_middle_3_muxid$123 - connect \logical_op__insn_type$2 \pipe_middle_3_logical_op__insn_type$124 - connect \logical_op__fn_unit$3 \pipe_middle_3_logical_op__fn_unit$125 - connect \logical_op__imm_data__imm$4 \pipe_middle_3_logical_op__imm_data__imm$126 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_3_logical_op__imm_data__imm_ok$127 - connect \logical_op__rc__rc$6 \pipe_middle_3_logical_op__rc__rc$128 - connect \logical_op__rc__rc_ok$7 \pipe_middle_3_logical_op__rc__rc_ok$129 - connect \logical_op__oe__oe$8 \pipe_middle_3_logical_op__oe__oe$130 - connect \logical_op__oe__oe_ok$9 \pipe_middle_3_logical_op__oe__oe_ok$131 - connect \logical_op__invert_in$10 \pipe_middle_3_logical_op__invert_in$132 - connect \logical_op__zero_a$11 \pipe_middle_3_logical_op__zero_a$133 - connect \logical_op__input_carry$12 \pipe_middle_3_logical_op__input_carry$134 - connect \logical_op__invert_out$13 \pipe_middle_3_logical_op__invert_out$135 - connect \logical_op__write_cr0$14 \pipe_middle_3_logical_op__write_cr0$136 - connect \logical_op__output_carry$15 \pipe_middle_3_logical_op__output_carry$137 - connect \logical_op__is_32bit$16 \pipe_middle_3_logical_op__is_32bit$138 - connect \logical_op__is_signed$17 \pipe_middle_3_logical_op__is_signed$139 - connect \logical_op__data_len$18 \pipe_middle_3_logical_op__data_len$140 - connect \logical_op__insn$19 \pipe_middle_3_logical_op__insn$141 - connect \ra$20 \pipe_middle_3_ra$142 - connect \rb$21 \pipe_middle_3_rb$143 - connect \xer_so$22 \pipe_middle_3_xer_so$144 - connect \divisor_neg$23 \pipe_middle_3_divisor_neg$145 - connect \dividend_neg$24 \pipe_middle_3_dividend_neg$146 - connect \dive_abs_ov32$25 \pipe_middle_3_dive_abs_ov32$147 - connect \dive_abs_ov64$26 \pipe_middle_3_dive_abs_ov64$148 - connect \div_by_zero$27 \pipe_middle_3_div_by_zero$149 - connect \divisor_radicand$28 \pipe_middle_3_divisor_radicand$150 - connect \operation$29 \pipe_middle_3_operation$151 - connect \quotient_root$30 \pipe_middle_3_quotient_root$152 - connect \root_times_radicand$31 \pipe_middle_3_root_times_radicand$153 - connect \compare_lhs$32 \pipe_middle_3_compare_lhs$154 - connect \compare_rhs$33 \pipe_middle_3_compare_rhs$155 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_4_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_4_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_4_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_4_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_4_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_4_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_4_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_4_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_4_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_4_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_4_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_4_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_4_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_4_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_4_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_4_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_4_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_4_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_4_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_4_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_4_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_4_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_4_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_4_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_4_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_4_muxid$156 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_4_logical_op__insn_type$157 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_4_logical_op__fn_unit$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_4_logical_op__imm_data__imm$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__imm_data__imm_ok$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__rc__rc$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__rc__rc_ok$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__oe__oe$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__oe__oe_ok$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__invert_in$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__zero_a$166 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_4_logical_op__input_carry$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__invert_out$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__write_cr0$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__output_carry$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__is_32bit$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_4_logical_op__is_signed$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_4_logical_op__data_len$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_4_logical_op__insn$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_4_ra$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_4_rb$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_4_xer_so$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_4_divisor_neg$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_4_dividend_neg$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_4_dive_abs_ov32$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_4_dive_abs_ov64$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_4_div_by_zero$182 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_4_divisor_radicand$183 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_4_operation$184 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_4_quotient_root$185 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_4_root_times_radicand$186 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_4_compare_lhs$187 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_4_compare_rhs$188 - cell \pipe_middle_4 \pipe_middle_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_4_p_valid_i - connect \p_ready_o \pipe_middle_4_p_ready_o - connect \muxid \pipe_middle_4_muxid - connect \logical_op__insn_type \pipe_middle_4_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_4_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_4_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_4_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_4_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_4_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_4_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_4_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_4_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_4_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_4_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_4_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_4_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_4_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_4_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_4_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_4_logical_op__data_len - connect \logical_op__insn \pipe_middle_4_logical_op__insn - connect \ra \pipe_middle_4_ra - connect \rb \pipe_middle_4_rb - connect \xer_so \pipe_middle_4_xer_so - connect \divisor_neg \pipe_middle_4_divisor_neg - connect \dividend_neg \pipe_middle_4_dividend_neg - connect \dive_abs_ov32 \pipe_middle_4_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_4_dive_abs_ov64 - connect \div_by_zero \pipe_middle_4_div_by_zero - connect \divisor_radicand \pipe_middle_4_divisor_radicand - connect \operation \pipe_middle_4_operation - connect \quotient_root \pipe_middle_4_quotient_root - connect \root_times_radicand \pipe_middle_4_root_times_radicand - connect \compare_lhs \pipe_middle_4_compare_lhs - connect \compare_rhs \pipe_middle_4_compare_rhs - connect \n_valid_o \pipe_middle_4_n_valid_o - connect \n_ready_i \pipe_middle_4_n_ready_i - connect \muxid$1 \pipe_middle_4_muxid$156 - connect \logical_op__insn_type$2 \pipe_middle_4_logical_op__insn_type$157 - connect \logical_op__fn_unit$3 \pipe_middle_4_logical_op__fn_unit$158 - connect \logical_op__imm_data__imm$4 \pipe_middle_4_logical_op__imm_data__imm$159 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_4_logical_op__imm_data__imm_ok$160 - connect \logical_op__rc__rc$6 \pipe_middle_4_logical_op__rc__rc$161 - connect \logical_op__rc__rc_ok$7 \pipe_middle_4_logical_op__rc__rc_ok$162 - connect \logical_op__oe__oe$8 \pipe_middle_4_logical_op__oe__oe$163 - connect \logical_op__oe__oe_ok$9 \pipe_middle_4_logical_op__oe__oe_ok$164 - connect \logical_op__invert_in$10 \pipe_middle_4_logical_op__invert_in$165 - connect \logical_op__zero_a$11 \pipe_middle_4_logical_op__zero_a$166 - connect \logical_op__input_carry$12 \pipe_middle_4_logical_op__input_carry$167 - connect \logical_op__invert_out$13 \pipe_middle_4_logical_op__invert_out$168 - connect \logical_op__write_cr0$14 \pipe_middle_4_logical_op__write_cr0$169 - connect \logical_op__output_carry$15 \pipe_middle_4_logical_op__output_carry$170 - connect \logical_op__is_32bit$16 \pipe_middle_4_logical_op__is_32bit$171 - connect \logical_op__is_signed$17 \pipe_middle_4_logical_op__is_signed$172 - connect \logical_op__data_len$18 \pipe_middle_4_logical_op__data_len$173 - connect \logical_op__insn$19 \pipe_middle_4_logical_op__insn$174 - connect \ra$20 \pipe_middle_4_ra$175 - connect \rb$21 \pipe_middle_4_rb$176 - connect \xer_so$22 \pipe_middle_4_xer_so$177 - connect \divisor_neg$23 \pipe_middle_4_divisor_neg$178 - connect \dividend_neg$24 \pipe_middle_4_dividend_neg$179 - connect \dive_abs_ov32$25 \pipe_middle_4_dive_abs_ov32$180 - connect \dive_abs_ov64$26 \pipe_middle_4_dive_abs_ov64$181 - connect \div_by_zero$27 \pipe_middle_4_div_by_zero$182 - connect \divisor_radicand$28 \pipe_middle_4_divisor_radicand$183 - connect \operation$29 \pipe_middle_4_operation$184 - connect \quotient_root$30 \pipe_middle_4_quotient_root$185 - connect \root_times_radicand$31 \pipe_middle_4_root_times_radicand$186 - connect \compare_lhs$32 \pipe_middle_4_compare_lhs$187 - connect \compare_rhs$33 \pipe_middle_4_compare_rhs$188 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_5_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_5_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_5_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_5_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_5_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_5_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_5_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_5_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_5_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_5_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_5_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_5_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_5_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_5_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_5_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_5_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_5_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_5_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_5_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_5_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_5_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_5_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_5_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_5_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_5_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_5_muxid$189 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_5_logical_op__insn_type$190 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_5_logical_op__fn_unit$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_5_logical_op__imm_data__imm$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__imm_data__imm_ok$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__rc__rc$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__rc__rc_ok$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__oe__oe$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__oe__oe_ok$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__invert_in$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__zero_a$199 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_5_logical_op__input_carry$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__invert_out$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__write_cr0$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__output_carry$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__is_32bit$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_5_logical_op__is_signed$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_5_logical_op__data_len$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_5_logical_op__insn$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_5_ra$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_5_rb$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_5_xer_so$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_5_divisor_neg$211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_5_dividend_neg$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_5_dive_abs_ov32$213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_5_dive_abs_ov64$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_5_div_by_zero$215 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_5_divisor_radicand$216 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_5_operation$217 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_5_quotient_root$218 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_5_root_times_radicand$219 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_5_compare_lhs$220 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_5_compare_rhs$221 - cell \pipe_middle_5 \pipe_middle_5 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_5_p_valid_i - connect \p_ready_o \pipe_middle_5_p_ready_o - connect \muxid \pipe_middle_5_muxid - connect \logical_op__insn_type \pipe_middle_5_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_5_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_5_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_5_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_5_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_5_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_5_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_5_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_5_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_5_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_5_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_5_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_5_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_5_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_5_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_5_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_5_logical_op__data_len - connect \logical_op__insn \pipe_middle_5_logical_op__insn - connect \ra \pipe_middle_5_ra - connect \rb \pipe_middle_5_rb - connect \xer_so \pipe_middle_5_xer_so - connect \divisor_neg \pipe_middle_5_divisor_neg - connect \dividend_neg \pipe_middle_5_dividend_neg - connect \dive_abs_ov32 \pipe_middle_5_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_5_dive_abs_ov64 - connect \div_by_zero \pipe_middle_5_div_by_zero - connect \divisor_radicand \pipe_middle_5_divisor_radicand - connect \operation \pipe_middle_5_operation - connect \quotient_root \pipe_middle_5_quotient_root - connect \root_times_radicand \pipe_middle_5_root_times_radicand - connect \compare_lhs \pipe_middle_5_compare_lhs - connect \compare_rhs \pipe_middle_5_compare_rhs - connect \n_valid_o \pipe_middle_5_n_valid_o - connect \n_ready_i \pipe_middle_5_n_ready_i - connect \muxid$1 \pipe_middle_5_muxid$189 - connect \logical_op__insn_type$2 \pipe_middle_5_logical_op__insn_type$190 - connect \logical_op__fn_unit$3 \pipe_middle_5_logical_op__fn_unit$191 - connect \logical_op__imm_data__imm$4 \pipe_middle_5_logical_op__imm_data__imm$192 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_5_logical_op__imm_data__imm_ok$193 - connect \logical_op__rc__rc$6 \pipe_middle_5_logical_op__rc__rc$194 - connect \logical_op__rc__rc_ok$7 \pipe_middle_5_logical_op__rc__rc_ok$195 - connect \logical_op__oe__oe$8 \pipe_middle_5_logical_op__oe__oe$196 - connect \logical_op__oe__oe_ok$9 \pipe_middle_5_logical_op__oe__oe_ok$197 - connect \logical_op__invert_in$10 \pipe_middle_5_logical_op__invert_in$198 - connect \logical_op__zero_a$11 \pipe_middle_5_logical_op__zero_a$199 - connect \logical_op__input_carry$12 \pipe_middle_5_logical_op__input_carry$200 - connect \logical_op__invert_out$13 \pipe_middle_5_logical_op__invert_out$201 - connect \logical_op__write_cr0$14 \pipe_middle_5_logical_op__write_cr0$202 - connect \logical_op__output_carry$15 \pipe_middle_5_logical_op__output_carry$203 - connect \logical_op__is_32bit$16 \pipe_middle_5_logical_op__is_32bit$204 - connect \logical_op__is_signed$17 \pipe_middle_5_logical_op__is_signed$205 - connect \logical_op__data_len$18 \pipe_middle_5_logical_op__data_len$206 - connect \logical_op__insn$19 \pipe_middle_5_logical_op__insn$207 - connect \ra$20 \pipe_middle_5_ra$208 - connect \rb$21 \pipe_middle_5_rb$209 - connect \xer_so$22 \pipe_middle_5_xer_so$210 - connect \divisor_neg$23 \pipe_middle_5_divisor_neg$211 - connect \dividend_neg$24 \pipe_middle_5_dividend_neg$212 - connect \dive_abs_ov32$25 \pipe_middle_5_dive_abs_ov32$213 - connect \dive_abs_ov64$26 \pipe_middle_5_dive_abs_ov64$214 - connect \div_by_zero$27 \pipe_middle_5_div_by_zero$215 - connect \divisor_radicand$28 \pipe_middle_5_divisor_radicand$216 - connect \operation$29 \pipe_middle_5_operation$217 - connect \quotient_root$30 \pipe_middle_5_quotient_root$218 - connect \root_times_radicand$31 \pipe_middle_5_root_times_radicand$219 - connect \compare_lhs$32 \pipe_middle_5_compare_lhs$220 - connect \compare_rhs$33 \pipe_middle_5_compare_rhs$221 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_6_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_6_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_6_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_6_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_6_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_6_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_6_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_6_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_6_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_6_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_6_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_6_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_6_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_6_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_6_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_6_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_6_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_6_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_6_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_6_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_6_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_6_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_6_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_6_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_6_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_6_muxid$222 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_6_logical_op__insn_type$223 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_6_logical_op__fn_unit$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_6_logical_op__imm_data__imm$225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__imm_data__imm_ok$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__rc__rc$227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__rc__rc_ok$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__oe__oe$229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__oe__oe_ok$230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__invert_in$231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__zero_a$232 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_6_logical_op__input_carry$233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__invert_out$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__write_cr0$235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__output_carry$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__is_32bit$237 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_6_logical_op__is_signed$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_6_logical_op__data_len$239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_6_logical_op__insn$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_6_ra$241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_6_rb$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_6_xer_so$243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_6_divisor_neg$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_6_dividend_neg$245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_6_dive_abs_ov32$246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_6_dive_abs_ov64$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_6_div_by_zero$248 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_6_divisor_radicand$249 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_6_operation$250 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_6_quotient_root$251 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_6_root_times_radicand$252 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_6_compare_lhs$253 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_6_compare_rhs$254 - cell \pipe_middle_6 \pipe_middle_6 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_6_p_valid_i - connect \p_ready_o \pipe_middle_6_p_ready_o - connect \muxid \pipe_middle_6_muxid - connect \logical_op__insn_type \pipe_middle_6_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_6_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_6_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_6_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_6_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_6_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_6_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_6_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_6_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_6_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_6_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_6_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_6_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_6_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_6_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_6_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_6_logical_op__data_len - connect \logical_op__insn \pipe_middle_6_logical_op__insn - connect \ra \pipe_middle_6_ra - connect \rb \pipe_middle_6_rb - connect \xer_so \pipe_middle_6_xer_so - connect \divisor_neg \pipe_middle_6_divisor_neg - connect \dividend_neg \pipe_middle_6_dividend_neg - connect \dive_abs_ov32 \pipe_middle_6_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_6_dive_abs_ov64 - connect \div_by_zero \pipe_middle_6_div_by_zero - connect \divisor_radicand \pipe_middle_6_divisor_radicand - connect \operation \pipe_middle_6_operation - connect \quotient_root \pipe_middle_6_quotient_root - connect \root_times_radicand \pipe_middle_6_root_times_radicand - connect \compare_lhs \pipe_middle_6_compare_lhs - connect \compare_rhs \pipe_middle_6_compare_rhs - connect \n_valid_o \pipe_middle_6_n_valid_o - connect \n_ready_i \pipe_middle_6_n_ready_i - connect \muxid$1 \pipe_middle_6_muxid$222 - connect \logical_op__insn_type$2 \pipe_middle_6_logical_op__insn_type$223 - connect \logical_op__fn_unit$3 \pipe_middle_6_logical_op__fn_unit$224 - connect \logical_op__imm_data__imm$4 \pipe_middle_6_logical_op__imm_data__imm$225 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_6_logical_op__imm_data__imm_ok$226 - connect \logical_op__rc__rc$6 \pipe_middle_6_logical_op__rc__rc$227 - connect \logical_op__rc__rc_ok$7 \pipe_middle_6_logical_op__rc__rc_ok$228 - connect \logical_op__oe__oe$8 \pipe_middle_6_logical_op__oe__oe$229 - connect \logical_op__oe__oe_ok$9 \pipe_middle_6_logical_op__oe__oe_ok$230 - connect \logical_op__invert_in$10 \pipe_middle_6_logical_op__invert_in$231 - connect \logical_op__zero_a$11 \pipe_middle_6_logical_op__zero_a$232 - connect \logical_op__input_carry$12 \pipe_middle_6_logical_op__input_carry$233 - connect \logical_op__invert_out$13 \pipe_middle_6_logical_op__invert_out$234 - connect \logical_op__write_cr0$14 \pipe_middle_6_logical_op__write_cr0$235 - connect \logical_op__output_carry$15 \pipe_middle_6_logical_op__output_carry$236 - connect \logical_op__is_32bit$16 \pipe_middle_6_logical_op__is_32bit$237 - connect \logical_op__is_signed$17 \pipe_middle_6_logical_op__is_signed$238 - connect \logical_op__data_len$18 \pipe_middle_6_logical_op__data_len$239 - connect \logical_op__insn$19 \pipe_middle_6_logical_op__insn$240 - connect \ra$20 \pipe_middle_6_ra$241 - connect \rb$21 \pipe_middle_6_rb$242 - connect \xer_so$22 \pipe_middle_6_xer_so$243 - connect \divisor_neg$23 \pipe_middle_6_divisor_neg$244 - connect \dividend_neg$24 \pipe_middle_6_dividend_neg$245 - connect \dive_abs_ov32$25 \pipe_middle_6_dive_abs_ov32$246 - connect \dive_abs_ov64$26 \pipe_middle_6_dive_abs_ov64$247 - connect \div_by_zero$27 \pipe_middle_6_div_by_zero$248 - connect \divisor_radicand$28 \pipe_middle_6_divisor_radicand$249 - connect \operation$29 \pipe_middle_6_operation$250 - connect \quotient_root$30 \pipe_middle_6_quotient_root$251 - connect \root_times_radicand$31 \pipe_middle_6_root_times_radicand$252 - connect \compare_lhs$32 \pipe_middle_6_compare_lhs$253 - connect \compare_rhs$33 \pipe_middle_6_compare_rhs$254 + end + sync init + update \div_by_zero$54 1'0 + sync posedge \coresync_clk + update \div_by_zero$54 \div_by_zero$54$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$66$next + process $group_65 + assign \dividend$66$next \dividend$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \dividend$66$next \dividend + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + end + sync init + update \dividend$66 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \dividend$66 \dividend$66$next + end + process $group_66 + assign \divisor_radicand$63$next \divisor_radicand$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \divisor_radicand$63$next \divisor_radicand + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + end + sync init + update \divisor_radicand$63 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$63 \divisor_radicand$63$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$67$next + process $group_67 + assign \operation$67$next \operation$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + switch { \empty } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + switch { \p_valid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" + case 1'1 + assign \operation$67$next \operation + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + case + end + sync init + update \operation$67 2'00 + sync posedge \coresync_clk + update \operation$67 \operation$67$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" +module \p$78 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_7_p_valid_i + wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_7_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_7_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_7_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_7_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_7_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_7_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_7_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_7_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_7_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_7_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_7_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_7_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_7_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_7_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_7_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_7_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_7_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_7_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_7_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_7_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_7_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_7_compare_rhs + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" +module \n$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_7_n_valid_o + wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_7_n_ready_i + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" +module \output_stage attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_7_muxid$255 + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -174122,7 +50512,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_7_logical_op__insn_type$256 + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -174136,151 +50526,61 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_7_logical_op__fn_unit$257 + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_7_logical_op__imm_data__imm$258 + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__imm_data__imm_ok$259 + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__rc__rc$260 + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__rc__rc_ok$261 + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__oe__oe$262 + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__oe__oe_ok$263 + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__invert_in$264 + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__zero_a$265 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_7_logical_op__input_carry$266 + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__invert_out$267 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__write_cr0$268 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__output_carry$269 + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__is_32bit$270 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_7_logical_op__is_signed$271 + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_7_logical_op__data_len$272 + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_7_logical_op__insn$273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_7_ra$274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_7_rb$275 + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_7_xer_so$276 + wire width 1 input 19 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_7_divisor_neg$277 + wire width 1 input 20 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_7_dividend_neg$278 + wire width 1 input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_7_dive_abs_ov32$279 + wire width 1 input 22 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_7_dive_abs_ov64$280 + wire width 1 input 23 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_7_div_by_zero$281 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_7_divisor_radicand$282 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_7_operation$283 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_7_quotient_root$284 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_7_root_times_radicand$285 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_7_compare_lhs$286 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_7_compare_rhs$287 - cell \pipe_middle_7 \pipe_middle_7 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_7_p_valid_i - connect \p_ready_o \pipe_middle_7_p_ready_o - connect \muxid \pipe_middle_7_muxid - connect \logical_op__insn_type \pipe_middle_7_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_7_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_7_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_7_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_7_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_7_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_7_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_7_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_7_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_7_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_7_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_7_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_7_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_7_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_7_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_7_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_7_logical_op__data_len - connect \logical_op__insn \pipe_middle_7_logical_op__insn - connect \ra \pipe_middle_7_ra - connect \rb \pipe_middle_7_rb - connect \xer_so \pipe_middle_7_xer_so - connect \divisor_neg \pipe_middle_7_divisor_neg - connect \dividend_neg \pipe_middle_7_dividend_neg - connect \dive_abs_ov32 \pipe_middle_7_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_7_dive_abs_ov64 - connect \div_by_zero \pipe_middle_7_div_by_zero - connect \divisor_radicand \pipe_middle_7_divisor_radicand - connect \operation \pipe_middle_7_operation - connect \quotient_root \pipe_middle_7_quotient_root - connect \root_times_radicand \pipe_middle_7_root_times_radicand - connect \compare_lhs \pipe_middle_7_compare_lhs - connect \compare_rhs \pipe_middle_7_compare_rhs - connect \n_valid_o \pipe_middle_7_n_valid_o - connect \n_ready_i \pipe_middle_7_n_ready_i - connect \muxid$1 \pipe_middle_7_muxid$255 - connect \logical_op__insn_type$2 \pipe_middle_7_logical_op__insn_type$256 - connect \logical_op__fn_unit$3 \pipe_middle_7_logical_op__fn_unit$257 - connect \logical_op__imm_data__imm$4 \pipe_middle_7_logical_op__imm_data__imm$258 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_7_logical_op__imm_data__imm_ok$259 - connect \logical_op__rc__rc$6 \pipe_middle_7_logical_op__rc__rc$260 - connect \logical_op__rc__rc_ok$7 \pipe_middle_7_logical_op__rc__rc_ok$261 - connect \logical_op__oe__oe$8 \pipe_middle_7_logical_op__oe__oe$262 - connect \logical_op__oe__oe_ok$9 \pipe_middle_7_logical_op__oe__oe_ok$263 - connect \logical_op__invert_in$10 \pipe_middle_7_logical_op__invert_in$264 - connect \logical_op__zero_a$11 \pipe_middle_7_logical_op__zero_a$265 - connect \logical_op__input_carry$12 \pipe_middle_7_logical_op__input_carry$266 - connect \logical_op__invert_out$13 \pipe_middle_7_logical_op__invert_out$267 - connect \logical_op__write_cr0$14 \pipe_middle_7_logical_op__write_cr0$268 - connect \logical_op__output_carry$15 \pipe_middle_7_logical_op__output_carry$269 - connect \logical_op__is_32bit$16 \pipe_middle_7_logical_op__is_32bit$270 - connect \logical_op__is_signed$17 \pipe_middle_7_logical_op__is_signed$271 - connect \logical_op__data_len$18 \pipe_middle_7_logical_op__data_len$272 - connect \logical_op__insn$19 \pipe_middle_7_logical_op__insn$273 - connect \ra$20 \pipe_middle_7_ra$274 - connect \rb$21 \pipe_middle_7_rb$275 - connect \xer_so$22 \pipe_middle_7_xer_so$276 - connect \divisor_neg$23 \pipe_middle_7_divisor_neg$277 - connect \dividend_neg$24 \pipe_middle_7_dividend_neg$278 - connect \dive_abs_ov32$25 \pipe_middle_7_dive_abs_ov32$279 - connect \dive_abs_ov64$26 \pipe_middle_7_dive_abs_ov64$280 - connect \div_by_zero$27 \pipe_middle_7_div_by_zero$281 - connect \divisor_radicand$28 \pipe_middle_7_divisor_radicand$282 - connect \operation$29 \pipe_middle_7_operation$283 - connect \quotient_root$30 \pipe_middle_7_quotient_root$284 - connect \root_times_radicand$31 \pipe_middle_7_root_times_radicand$285 - connect \compare_lhs$32 \pipe_middle_7_compare_lhs$286 - connect \compare_rhs$33 \pipe_middle_7_compare_rhs$287 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_8_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_8_p_ready_o + wire width 1 input 24 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_8_muxid + wire width 2 output 27 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -174355,7 +50655,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_8_logical_op__insn_type + wire width 7 output 28 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -174369,77 +50669,438 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_8_logical_op__fn_unit + wire width 11 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_8_logical_op__imm_data__imm + wire width 64 output 30 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__imm_data__imm_ok + wire width 1 output 31 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__rc__rc + wire width 1 output 32 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__rc__rc_ok + wire width 1 output 33 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__oe__oe + wire width 1 output 34 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__oe__oe_ok + wire width 1 output 35 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__invert_in + wire width 1 output 36 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__zero_a + wire width 1 output 37 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_8_logical_op__input_carry + wire width 2 output 38 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__invert_out + wire width 1 output 39 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__write_cr0 + wire width 1 output 40 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__output_carry + wire width 1 output 41 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__is_32bit + wire width 1 output 42 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__is_signed + wire width 1 output 43 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_8_logical_op__data_len + wire width 4 output 44 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_8_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_8_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_8_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_8_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_8_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_8_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_8_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_8_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_8_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_8_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_8_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_8_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_8_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_8_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_8_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_8_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_8_n_ready_i + wire width 32 output 45 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire width 1 \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $21 + end + process $group_0 + assign \quotient_neg 1'0 + assign \quotient_neg $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire width 1 \remainder_neg + process $group_1 + assign \remainder_neg 1'0 + assign \remainder_neg \dividend_neg + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 65 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $28 + parameter \WIDTH 65 + connect \A $25 + connect \B $23 + connect \S \quotient_neg + connect \Y $27 + end + process $group_2 + assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_65 $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 65 $32 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $35 + parameter \WIDTH 65 + connect \A $32 + connect \B $30 + connect \S \remainder_neg + connect \Y $34 + end + connect $29 $34 + process $group_3 + assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \remainder_64 $29 [63:0] + sync init + end + wire width 1 $verilog_initial_trigger + process $group_4 + assign \xer_ov_ok 1'0 + assign \xer_ov_ok 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire width 1 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B $38 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $42 + end + process $group_5 + assign \ov 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed $36 \div_by_zero } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + case 3'--1 + assign \ov 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + case 3'-1- + assign \ov \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch { $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + case 1'1 + assign \ov 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" + case 3'1-- + assign \ov \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch { $42 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + case 1'1 + assign \ov 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" + case + assign \ov \dive_abs_ov32 + end + sync init + end + process $group_6 + assign \xer_ov 2'00 + assign \xer_ov { \ov \ov } + sync init + end + process $group_7 + assign \o_ok 1'0 + assign \o_ok 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + cell $not $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + wire width 64 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + wire width 64 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + wire width 64 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + wire width 64 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + wire width 64 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + cell $pos $55 + parameter \A_SIGNED 1 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $54 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + wire width 64 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $56 + end + process $group_8 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + switch { $44 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" + attribute \nmigen.decoding "OP_DIVE/30" + case 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + case 1'1 + assign \o $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + case + assign \o $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + case + assign \o \quotient_65 [63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" + attribute \nmigen.decoding "OP_DIV/29" + case 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + case 1'1 + assign \o $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:112" + case + assign \o $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + case + assign \o \quotient_65 [63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:116" + attribute \nmigen.decoding "OP_MOD/47" + case 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + case 1'1 + assign \o $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:121" + case + assign \o $56 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + case + assign \o \remainder_64 + end + end + end + sync init + end + process $group_9 + assign \xer_so$20 1'0 + assign \xer_so$20 \xer_so + sync init + end + process $group_10 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_11 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" +module \output$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_8_muxid$288 + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -174514,7 +51175,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_8_logical_op__insn_type$289 + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -174528,151 +51189,55 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_8_logical_op__fn_unit$290 + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_8_logical_op__imm_data__imm$291 + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__imm_data__imm_ok$292 + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__rc__rc$293 + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__rc__rc_ok$294 + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__oe__oe$295 + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__oe__oe_ok$296 + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__invert_in$297 + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__zero_a$298 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_8_logical_op__input_carry$299 + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__invert_out$300 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__write_cr0$301 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__output_carry$302 + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__is_32bit$303 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_8_logical_op__is_signed$304 + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_8_logical_op__data_len$305 + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_8_logical_op__insn$306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_8_ra$307 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_8_rb$308 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_8_xer_so$309 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_8_divisor_neg$310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_8_dividend_neg$311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_8_dive_abs_ov32$312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_8_dive_abs_ov64$313 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_8_div_by_zero$314 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_8_divisor_radicand$315 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_8_operation$316 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_8_quotient_root$317 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_8_root_times_radicand$318 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_8_compare_lhs$319 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_8_compare_rhs$320 - cell \pipe_middle_8 \pipe_middle_8 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_8_p_valid_i - connect \p_ready_o \pipe_middle_8_p_ready_o - connect \muxid \pipe_middle_8_muxid - connect \logical_op__insn_type \pipe_middle_8_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_8_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_8_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_8_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_8_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_8_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_8_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_8_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_8_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_8_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_8_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_8_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_8_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_8_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_8_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_8_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_8_logical_op__data_len - connect \logical_op__insn \pipe_middle_8_logical_op__insn - connect \ra \pipe_middle_8_ra - connect \rb \pipe_middle_8_rb - connect \xer_so \pipe_middle_8_xer_so - connect \divisor_neg \pipe_middle_8_divisor_neg - connect \dividend_neg \pipe_middle_8_dividend_neg - connect \dive_abs_ov32 \pipe_middle_8_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_8_dive_abs_ov64 - connect \div_by_zero \pipe_middle_8_div_by_zero - connect \divisor_radicand \pipe_middle_8_divisor_radicand - connect \operation \pipe_middle_8_operation - connect \quotient_root \pipe_middle_8_quotient_root - connect \root_times_radicand \pipe_middle_8_root_times_radicand - connect \compare_lhs \pipe_middle_8_compare_lhs - connect \compare_rhs \pipe_middle_8_compare_rhs - connect \n_valid_o \pipe_middle_8_n_valid_o - connect \n_ready_i \pipe_middle_8_n_ready_i - connect \muxid$1 \pipe_middle_8_muxid$288 - connect \logical_op__insn_type$2 \pipe_middle_8_logical_op__insn_type$289 - connect \logical_op__fn_unit$3 \pipe_middle_8_logical_op__fn_unit$290 - connect \logical_op__imm_data__imm$4 \pipe_middle_8_logical_op__imm_data__imm$291 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_8_logical_op__imm_data__imm_ok$292 - connect \logical_op__rc__rc$6 \pipe_middle_8_logical_op__rc__rc$293 - connect \logical_op__rc__rc_ok$7 \pipe_middle_8_logical_op__rc__rc_ok$294 - connect \logical_op__oe__oe$8 \pipe_middle_8_logical_op__oe__oe$295 - connect \logical_op__oe__oe_ok$9 \pipe_middle_8_logical_op__oe__oe_ok$296 - connect \logical_op__invert_in$10 \pipe_middle_8_logical_op__invert_in$297 - connect \logical_op__zero_a$11 \pipe_middle_8_logical_op__zero_a$298 - connect \logical_op__input_carry$12 \pipe_middle_8_logical_op__input_carry$299 - connect \logical_op__invert_out$13 \pipe_middle_8_logical_op__invert_out$300 - connect \logical_op__write_cr0$14 \pipe_middle_8_logical_op__write_cr0$301 - connect \logical_op__output_carry$15 \pipe_middle_8_logical_op__output_carry$302 - connect \logical_op__is_32bit$16 \pipe_middle_8_logical_op__is_32bit$303 - connect \logical_op__is_signed$17 \pipe_middle_8_logical_op__is_signed$304 - connect \logical_op__data_len$18 \pipe_middle_8_logical_op__data_len$305 - connect \logical_op__insn$19 \pipe_middle_8_logical_op__insn$306 - connect \ra$20 \pipe_middle_8_ra$307 - connect \rb$21 \pipe_middle_8_rb$308 - connect \xer_so$22 \pipe_middle_8_xer_so$309 - connect \divisor_neg$23 \pipe_middle_8_divisor_neg$310 - connect \dividend_neg$24 \pipe_middle_8_dividend_neg$311 - connect \dive_abs_ov32$25 \pipe_middle_8_dive_abs_ov32$312 - connect \dive_abs_ov64$26 \pipe_middle_8_dive_abs_ov64$313 - connect \div_by_zero$27 \pipe_middle_8_div_by_zero$314 - connect \divisor_radicand$28 \pipe_middle_8_divisor_radicand$315 - connect \operation$29 \pipe_middle_8_operation$316 - connect \quotient_root$30 \pipe_middle_8_quotient_root$317 - connect \root_times_radicand$31 \pipe_middle_8_root_times_radicand$318 - connect \compare_lhs$32 \pipe_middle_8_compare_lhs$319 - connect \compare_rhs$33 \pipe_middle_8_compare_rhs$320 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_9_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_9_p_ready_o + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 23 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_9_muxid + wire width 2 output 24 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -174747,7 +51312,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_9_logical_op__insn_type + wire width 7 output 25 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -174761,77 +51326,422 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_9_logical_op__fn_unit + wire width 11 output 26 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_9_logical_op__imm_data__imm + wire width 64 output 27 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__imm_data__imm_ok + wire width 1 output 28 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__rc__rc + wire width 1 output 29 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__rc__rc_ok + wire width 1 output 30 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__oe__oe + wire width 1 output 31 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__oe__oe_ok + wire width 1 output 32 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__invert_in + wire width 1 output 33 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__zero_a + wire width 1 output 34 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_9_logical_op__input_carry + wire width 2 output 35 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__invert_out + wire width 1 output 36 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__write_cr0 + wire width 1 output 37 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__output_carry + wire width 1 output 38 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__is_32bit + wire width 1 output 39 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__is_signed + wire width 1 output 40 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_9_logical_op__data_len + wire width 4 output 41 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_9_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_9_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_9_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_9_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_9_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_9_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_9_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_9_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_9_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_9_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_9_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_9_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_9_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_9_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_9_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_9_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_9_n_ready_i + wire width 32 output 42 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 45 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 46 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 65 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 64 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $pos $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $27 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $30 + end + process $group_0 + assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + switch { \logical_op__invert_out } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + case 1'1 + assign \o$25 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + case + assign \o$25 $30 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$25 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $32 + end + process $group_2 + assign \is_cmp 1'0 + assign \is_cmp $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $34 + end + process $group_3 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $34 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test + process $group_4 + assign \msb_test 1'0 + assign \msb_test \target [63] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + cell $reduce_bool $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $36 + end + process $group_5 + assign \is_nzero 1'0 + assign \is_nzero $36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $38 + connect \Y $40 + end + process $group_6 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $40 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $and $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $42 + connect \Y $44 + end + process $group_7 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $46 + end + process $group_8 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $46 \xer_so$24 } + end + sync init + end + process $group_9 + assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$20 \o$25 [63:0] + sync init + end + process $group_10 + assign \o_ok$21 1'0 + assign \o_ok$21 \o_ok + sync init + end + process $group_11 + assign \cr_a$22 4'0000 + assign \cr_a$22 \cr0 + sync init + end + process $group_12 + assign \cr_a_ok 1'0 + assign \cr_a_ok \logical_op__write_cr0 + sync init + end + process $group_13 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_14 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + cell $and $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__oe_ok + connect \Y $48 + end + process $group_32 + assign \oe 1'0 + assign \oe $48 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + wire width 1 \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + cell $or $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $50 + end + process $group_33 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \so $50 + end + sync init + end + process $group_34 + assign \xer_so$24 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so$24 \so + end + sync init + end + process $group_35 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so_ok 1'1 + end + sync init + end + process $group_36 + assign \xer_ov$23 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov$23 \xer_ov + end + sync init + end + process $group_37 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" +module \pipe_end + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_9_muxid$321 + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -174906,7 +51816,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_9_logical_op__insn_type$322 + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -174920,151 +51830,71 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_9_logical_op__fn_unit$323 + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_9_logical_op__imm_data__imm$324 + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__imm_data__imm_ok$325 + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__rc__rc$326 + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__rc__rc_ok$327 + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__oe__oe$328 + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__oe__oe_ok$329 + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__invert_in$330 + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__zero_a$331 + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_9_logical_op__input_carry$332 + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__invert_out$333 + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__write_cr0$334 + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__output_carry$335 + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__is_32bit$336 + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_9_logical_op__is_signed$337 + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_9_logical_op__data_len$338 + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_9_logical_op__insn$339 + wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_9_ra$340 + wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_9_rb$341 + wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_9_xer_so$342 + wire width 1 input 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_9_divisor_neg$343 + wire width 1 input 26 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_9_dividend_neg$344 + wire width 1 input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_9_dive_abs_ov32$345 + wire width 1 input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_9_dive_abs_ov64$346 + wire width 1 input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_9_div_by_zero$347 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_9_divisor_radicand$348 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_9_operation$349 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_9_quotient_root$350 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_9_root_times_radicand$351 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_9_compare_lhs$352 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_9_compare_rhs$353 - cell \pipe_middle_9 \pipe_middle_9 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_9_p_valid_i - connect \p_ready_o \pipe_middle_9_p_ready_o - connect \muxid \pipe_middle_9_muxid - connect \logical_op__insn_type \pipe_middle_9_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_9_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_9_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_9_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_9_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_9_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_9_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_9_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_9_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_9_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_9_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_9_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_9_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_9_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_9_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_9_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_9_logical_op__data_len - connect \logical_op__insn \pipe_middle_9_logical_op__insn - connect \ra \pipe_middle_9_ra - connect \rb \pipe_middle_9_rb - connect \xer_so \pipe_middle_9_xer_so - connect \divisor_neg \pipe_middle_9_divisor_neg - connect \dividend_neg \pipe_middle_9_dividend_neg - connect \dive_abs_ov32 \pipe_middle_9_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_9_dive_abs_ov64 - connect \div_by_zero \pipe_middle_9_div_by_zero - connect \divisor_radicand \pipe_middle_9_divisor_radicand - connect \operation \pipe_middle_9_operation - connect \quotient_root \pipe_middle_9_quotient_root - connect \root_times_radicand \pipe_middle_9_root_times_radicand - connect \compare_lhs \pipe_middle_9_compare_lhs - connect \compare_rhs \pipe_middle_9_compare_rhs - connect \n_valid_o \pipe_middle_9_n_valid_o - connect \n_ready_i \pipe_middle_9_n_ready_i - connect \muxid$1 \pipe_middle_9_muxid$321 - connect \logical_op__insn_type$2 \pipe_middle_9_logical_op__insn_type$322 - connect \logical_op__fn_unit$3 \pipe_middle_9_logical_op__fn_unit$323 - connect \logical_op__imm_data__imm$4 \pipe_middle_9_logical_op__imm_data__imm$324 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_9_logical_op__imm_data__imm_ok$325 - connect \logical_op__rc__rc$6 \pipe_middle_9_logical_op__rc__rc$326 - connect \logical_op__rc__rc_ok$7 \pipe_middle_9_logical_op__rc__rc_ok$327 - connect \logical_op__oe__oe$8 \pipe_middle_9_logical_op__oe__oe$328 - connect \logical_op__oe__oe_ok$9 \pipe_middle_9_logical_op__oe__oe_ok$329 - connect \logical_op__invert_in$10 \pipe_middle_9_logical_op__invert_in$330 - connect \logical_op__zero_a$11 \pipe_middle_9_logical_op__zero_a$331 - connect \logical_op__input_carry$12 \pipe_middle_9_logical_op__input_carry$332 - connect \logical_op__invert_out$13 \pipe_middle_9_logical_op__invert_out$333 - connect \logical_op__write_cr0$14 \pipe_middle_9_logical_op__write_cr0$334 - connect \logical_op__output_carry$15 \pipe_middle_9_logical_op__output_carry$335 - connect \logical_op__is_32bit$16 \pipe_middle_9_logical_op__is_32bit$336 - connect \logical_op__is_signed$17 \pipe_middle_9_logical_op__is_signed$337 - connect \logical_op__data_len$18 \pipe_middle_9_logical_op__data_len$338 - connect \logical_op__insn$19 \pipe_middle_9_logical_op__insn$339 - connect \ra$20 \pipe_middle_9_ra$340 - connect \rb$21 \pipe_middle_9_rb$341 - connect \xer_so$22 \pipe_middle_9_xer_so$342 - connect \divisor_neg$23 \pipe_middle_9_divisor_neg$343 - connect \dividend_neg$24 \pipe_middle_9_dividend_neg$344 - connect \dive_abs_ov32$25 \pipe_middle_9_dive_abs_ov32$345 - connect \dive_abs_ov64$26 \pipe_middle_9_dive_abs_ov64$346 - connect \div_by_zero$27 \pipe_middle_9_div_by_zero$347 - connect \divisor_radicand$28 \pipe_middle_9_divisor_radicand$348 - connect \operation$29 \pipe_middle_9_operation$349 - connect \quotient_root$30 \pipe_middle_9_quotient_root$350 - connect \root_times_radicand$31 \pipe_middle_9_root_times_radicand$351 - connect \compare_lhs$32 \pipe_middle_9_compare_lhs$352 - connect \compare_rhs$33 \pipe_middle_9_compare_rhs$353 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_10_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_10_p_ready_o + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 31 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 32 \remainder + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_10_muxid + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -175139,7 +51969,9 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_10_logical_op__insn_type + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -175153,310 +51985,119 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_10_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_10_logical_op__imm_data__imm + wire width 11 output 37 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__imm_data__imm_ok + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__rc__rc + wire width 64 output 38 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__rc__rc_ok + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__oe__oe + wire width 1 output 39 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__oe__oe_ok + wire width 1 \logical_op__imm_data__imm_ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__invert_in + wire width 1 output 40 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_10_logical_op__input_carry + wire width 1 output 41 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__invert_out + wire width 1 \logical_op__rc__rc_ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__write_cr0 + wire width 1 output 42 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__output_carry + wire width 1 \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__is_32bit + wire width 1 output 43 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__is_signed + wire width 1 \logical_op__oe__oe_ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_10_logical_op__data_len + wire width 1 output 44 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_10_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_10_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_10_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_10_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_10_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_10_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_10_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_10_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_10_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_10_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_10_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_10_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_10_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_10_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_10_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_10_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_10_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_10_muxid$354 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 1 \logical_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_10_logical_op__insn_type$355 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 1 output 45 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_10_logical_op__fn_unit$356 + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_10_logical_op__imm_data__imm$357 + wire width 2 output 46 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__imm_data__imm_ok$358 + wire width 2 \logical_op__input_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__rc__rc$359 + wire width 1 output 47 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__rc__rc_ok$360 + wire width 1 \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__oe__oe$361 + wire width 1 output 48 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__oe__oe_ok$362 + wire width 1 \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__invert_in$363 + wire width 1 output 49 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__zero_a$364 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 1 \logical_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_10_logical_op__input_carry$365 + wire width 1 output 50 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__invert_out$366 + wire width 1 \logical_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__write_cr0$367 + wire width 1 output 51 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__output_carry$368 + wire width 1 \logical_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__is_32bit$369 + wire width 4 output 52 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_10_logical_op__is_signed$370 + wire width 4 \logical_op__data_len$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_10_logical_op__data_len$371 + wire width 32 output 53 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_10_logical_op__insn$372 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_10_ra$373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_10_rb$374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_10_xer_so$375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_10_divisor_neg$376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_10_dividend_neg$377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_10_dive_abs_ov32$378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_10_dive_abs_ov64$379 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_10_div_by_zero$380 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_10_divisor_radicand$381 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_10_operation$382 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_10_quotient_root$383 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_10_root_times_radicand$384 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_10_compare_lhs$385 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_10_compare_rhs$386 - cell \pipe_middle_10 \pipe_middle_10 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_10_p_valid_i - connect \p_ready_o \pipe_middle_10_p_ready_o - connect \muxid \pipe_middle_10_muxid - connect \logical_op__insn_type \pipe_middle_10_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_10_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_10_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_10_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_10_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_10_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_10_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_10_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_10_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_10_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_10_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_10_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_10_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_10_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_10_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_10_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_10_logical_op__data_len - connect \logical_op__insn \pipe_middle_10_logical_op__insn - connect \ra \pipe_middle_10_ra - connect \rb \pipe_middle_10_rb - connect \xer_so \pipe_middle_10_xer_so - connect \divisor_neg \pipe_middle_10_divisor_neg - connect \dividend_neg \pipe_middle_10_dividend_neg - connect \dive_abs_ov32 \pipe_middle_10_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_10_dive_abs_ov64 - connect \div_by_zero \pipe_middle_10_div_by_zero - connect \divisor_radicand \pipe_middle_10_divisor_radicand - connect \operation \pipe_middle_10_operation - connect \quotient_root \pipe_middle_10_quotient_root - connect \root_times_radicand \pipe_middle_10_root_times_radicand - connect \compare_lhs \pipe_middle_10_compare_lhs - connect \compare_rhs \pipe_middle_10_compare_rhs - connect \n_valid_o \pipe_middle_10_n_valid_o - connect \n_ready_i \pipe_middle_10_n_ready_i - connect \muxid$1 \pipe_middle_10_muxid$354 - connect \logical_op__insn_type$2 \pipe_middle_10_logical_op__insn_type$355 - connect \logical_op__fn_unit$3 \pipe_middle_10_logical_op__fn_unit$356 - connect \logical_op__imm_data__imm$4 \pipe_middle_10_logical_op__imm_data__imm$357 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_10_logical_op__imm_data__imm_ok$358 - connect \logical_op__rc__rc$6 \pipe_middle_10_logical_op__rc__rc$359 - connect \logical_op__rc__rc_ok$7 \pipe_middle_10_logical_op__rc__rc_ok$360 - connect \logical_op__oe__oe$8 \pipe_middle_10_logical_op__oe__oe$361 - connect \logical_op__oe__oe_ok$9 \pipe_middle_10_logical_op__oe__oe_ok$362 - connect \logical_op__invert_in$10 \pipe_middle_10_logical_op__invert_in$363 - connect \logical_op__zero_a$11 \pipe_middle_10_logical_op__zero_a$364 - connect \logical_op__input_carry$12 \pipe_middle_10_logical_op__input_carry$365 - connect \logical_op__invert_out$13 \pipe_middle_10_logical_op__invert_out$366 - connect \logical_op__write_cr0$14 \pipe_middle_10_logical_op__write_cr0$367 - connect \logical_op__output_carry$15 \pipe_middle_10_logical_op__output_carry$368 - connect \logical_op__is_32bit$16 \pipe_middle_10_logical_op__is_32bit$369 - connect \logical_op__is_signed$17 \pipe_middle_10_logical_op__is_signed$370 - connect \logical_op__data_len$18 \pipe_middle_10_logical_op__data_len$371 - connect \logical_op__insn$19 \pipe_middle_10_logical_op__insn$372 - connect \ra$20 \pipe_middle_10_ra$373 - connect \rb$21 \pipe_middle_10_rb$374 - connect \xer_so$22 \pipe_middle_10_xer_so$375 - connect \divisor_neg$23 \pipe_middle_10_divisor_neg$376 - connect \dividend_neg$24 \pipe_middle_10_dividend_neg$377 - connect \dive_abs_ov32$25 \pipe_middle_10_dive_abs_ov32$378 - connect \dive_abs_ov64$26 \pipe_middle_10_dive_abs_ov64$379 - connect \div_by_zero$27 \pipe_middle_10_div_by_zero$380 - connect \divisor_radicand$28 \pipe_middle_10_divisor_radicand$381 - connect \operation$29 \pipe_middle_10_operation$382 - connect \quotient_root$30 \pipe_middle_10_quotient_root$383 - connect \root_times_radicand$31 \pipe_middle_10_root_times_radicand$384 - connect \compare_lhs$32 \pipe_middle_10_compare_lhs$385 - connect \compare_rhs$33 \pipe_middle_10_compare_rhs$386 + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 59 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 60 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$next + cell \p$78 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$79 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_11_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_11_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_11_muxid + wire width 2 \output_stage_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -175531,7 +52172,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_11_logical_op__insn_type + wire width 7 \output_stage_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -175545,77 +52186,61 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_11_logical_op__fn_unit + wire width 11 \output_stage_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_11_logical_op__imm_data__imm + wire width 64 \output_stage_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__imm_data__imm_ok + wire width 1 \output_stage_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__rc__rc + wire width 1 \output_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__rc__rc_ok + wire width 1 \output_stage_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__oe__oe + wire width 1 \output_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__oe__oe_ok + wire width 1 \output_stage_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__invert_in + wire width 1 \output_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__zero_a + wire width 1 \output_stage_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_11_logical_op__input_carry + wire width 2 \output_stage_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__invert_out + wire width 1 \output_stage_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__write_cr0 + wire width 1 \output_stage_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__output_carry + wire width 1 \output_stage_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__is_32bit + wire width 1 \output_stage_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__is_signed + wire width 1 \output_stage_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_11_logical_op__data_len + wire width 4 \output_stage_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_11_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_11_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_11_rb + wire width 32 \output_stage_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_11_xer_so + wire width 1 \output_stage_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_11_divisor_neg + wire width 1 \output_stage_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_11_dividend_neg + wire width 1 \output_stage_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_11_dive_abs_ov32 + wire width 1 \output_stage_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_11_dive_abs_ov64 + wire width 1 \output_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_11_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_11_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_11_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_11_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_11_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_11_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_11_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_11_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_11_n_ready_i + wire width 1 \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \output_stage_remainder attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_11_muxid$387 + wire width 2 \output_stage_muxid$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -175690,7 +52315,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_11_logical_op__insn_type$388 + wire width 7 \output_stage_logical_op__insn_type$22 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -175704,151 +52329,108 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_11_logical_op__fn_unit$389 + wire width 11 \output_stage_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_11_logical_op__imm_data__imm$390 + wire width 64 \output_stage_logical_op__imm_data__imm$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__imm_data__imm_ok$391 + wire width 1 \output_stage_logical_op__imm_data__imm_ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__rc__rc$392 + wire width 1 \output_stage_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__rc__rc_ok$393 + wire width 1 \output_stage_logical_op__rc__rc_ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__oe__oe$394 + wire width 1 \output_stage_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__oe__oe_ok$395 + wire width 1 \output_stage_logical_op__oe__oe_ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__invert_in$396 + wire width 1 \output_stage_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__zero_a$397 + wire width 1 \output_stage_logical_op__zero_a$31 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_11_logical_op__input_carry$398 + wire width 2 \output_stage_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__invert_out$399 + wire width 1 \output_stage_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__write_cr0$400 + wire width 1 \output_stage_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__output_carry$401 + wire width 1 \output_stage_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__is_32bit$402 + wire width 1 \output_stage_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_11_logical_op__is_signed$403 + wire width 1 \output_stage_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_11_logical_op__data_len$404 + wire width 4 \output_stage_logical_op__data_len$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_11_logical_op__insn$405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_11_ra$406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_11_rb$407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_11_xer_so$408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_11_divisor_neg$409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_11_dividend_neg$410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_11_dive_abs_ov32$411 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_11_dive_abs_ov64$412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_11_div_by_zero$413 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_11_divisor_radicand$414 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_11_operation$415 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_11_quotient_root$416 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_11_root_times_radicand$417 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_11_compare_lhs$418 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_11_compare_rhs$419 - cell \pipe_middle_11 \pipe_middle_11 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_11_p_valid_i - connect \p_ready_o \pipe_middle_11_p_ready_o - connect \muxid \pipe_middle_11_muxid - connect \logical_op__insn_type \pipe_middle_11_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_11_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_11_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_11_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_11_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_11_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_11_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_11_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_11_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_11_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_11_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_11_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_11_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_11_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_11_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_11_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_11_logical_op__data_len - connect \logical_op__insn \pipe_middle_11_logical_op__insn - connect \ra \pipe_middle_11_ra - connect \rb \pipe_middle_11_rb - connect \xer_so \pipe_middle_11_xer_so - connect \divisor_neg \pipe_middle_11_divisor_neg - connect \dividend_neg \pipe_middle_11_dividend_neg - connect \dive_abs_ov32 \pipe_middle_11_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_11_dive_abs_ov64 - connect \div_by_zero \pipe_middle_11_div_by_zero - connect \divisor_radicand \pipe_middle_11_divisor_radicand - connect \operation \pipe_middle_11_operation - connect \quotient_root \pipe_middle_11_quotient_root - connect \root_times_radicand \pipe_middle_11_root_times_radicand - connect \compare_lhs \pipe_middle_11_compare_lhs - connect \compare_rhs \pipe_middle_11_compare_rhs - connect \n_valid_o \pipe_middle_11_n_valid_o - connect \n_ready_i \pipe_middle_11_n_ready_i - connect \muxid$1 \pipe_middle_11_muxid$387 - connect \logical_op__insn_type$2 \pipe_middle_11_logical_op__insn_type$388 - connect \logical_op__fn_unit$3 \pipe_middle_11_logical_op__fn_unit$389 - connect \logical_op__imm_data__imm$4 \pipe_middle_11_logical_op__imm_data__imm$390 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_11_logical_op__imm_data__imm_ok$391 - connect \logical_op__rc__rc$6 \pipe_middle_11_logical_op__rc__rc$392 - connect \logical_op__rc__rc_ok$7 \pipe_middle_11_logical_op__rc__rc_ok$393 - connect \logical_op__oe__oe$8 \pipe_middle_11_logical_op__oe__oe$394 - connect \logical_op__oe__oe_ok$9 \pipe_middle_11_logical_op__oe__oe_ok$395 - connect \logical_op__invert_in$10 \pipe_middle_11_logical_op__invert_in$396 - connect \logical_op__zero_a$11 \pipe_middle_11_logical_op__zero_a$397 - connect \logical_op__input_carry$12 \pipe_middle_11_logical_op__input_carry$398 - connect \logical_op__invert_out$13 \pipe_middle_11_logical_op__invert_out$399 - connect \logical_op__write_cr0$14 \pipe_middle_11_logical_op__write_cr0$400 - connect \logical_op__output_carry$15 \pipe_middle_11_logical_op__output_carry$401 - connect \logical_op__is_32bit$16 \pipe_middle_11_logical_op__is_32bit$402 - connect \logical_op__is_signed$17 \pipe_middle_11_logical_op__is_signed$403 - connect \logical_op__data_len$18 \pipe_middle_11_logical_op__data_len$404 - connect \logical_op__insn$19 \pipe_middle_11_logical_op__insn$405 - connect \ra$20 \pipe_middle_11_ra$406 - connect \rb$21 \pipe_middle_11_rb$407 - connect \xer_so$22 \pipe_middle_11_xer_so$408 - connect \divisor_neg$23 \pipe_middle_11_divisor_neg$409 - connect \dividend_neg$24 \pipe_middle_11_dividend_neg$410 - connect \dive_abs_ov32$25 \pipe_middle_11_dive_abs_ov32$411 - connect \dive_abs_ov64$26 \pipe_middle_11_dive_abs_ov64$412 - connect \div_by_zero$27 \pipe_middle_11_div_by_zero$413 - connect \divisor_radicand$28 \pipe_middle_11_divisor_radicand$414 - connect \operation$29 \pipe_middle_11_operation$415 - connect \quotient_root$30 \pipe_middle_11_quotient_root$416 - connect \root_times_radicand$31 \pipe_middle_11_root_times_radicand$417 - connect \compare_lhs$32 \pipe_middle_11_compare_lhs$418 - connect \compare_rhs$33 \pipe_middle_11_compare_rhs$419 + wire width 32 \output_stage_logical_op__insn$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_xer_so$40 + cell \output_stage \output_stage + connect \muxid \output_stage_muxid + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__imm_data__imm \output_stage_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc_ok \output_stage_logical_op__rc__rc_ok + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe_ok \output_stage_logical_op__oe__oe_ok + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__insn \output_stage_logical_op__insn + connect \xer_so \output_stage_xer_so + connect \divisor_neg \output_stage_divisor_neg + connect \dividend_neg \output_stage_dividend_neg + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \div_by_zero \output_stage_div_by_zero + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \muxid$1 \output_stage_muxid$21 + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__imm$4 \output_stage_logical_op__imm_data__imm$24 + connect \logical_op__imm_data__imm_ok$5 \output_stage_logical_op__imm_data__imm_ok$25 + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__rc__rc_ok$7 \output_stage_logical_op__rc__rc_ok$27 + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__oe_ok$9 \output_stage_logical_op__oe__oe_ok$29 + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so$20 \output_stage_xer_so$40 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_12_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_12_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_12_muxid + wire width 2 \output_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -175923,7 +52505,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_12_logical_op__insn_type + wire width 7 \output_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -175937,77 +52519,55 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_12_logical_op__fn_unit + wire width 11 \output_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_12_logical_op__imm_data__imm + wire width 64 \output_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__imm_data__imm_ok + wire width 1 \output_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__rc__rc + wire width 1 \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__rc__rc_ok + wire width 1 \output_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__oe__oe + wire width 1 \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__oe__oe_ok + wire width 1 \output_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__invert_in + wire width 1 \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__zero_a + wire width 1 \output_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_12_logical_op__input_carry + wire width 2 \output_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__invert_out + wire width 1 \output_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__write_cr0 + wire width 1 \output_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__output_carry + wire width 1 \output_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__is_32bit + wire width 1 \output_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__is_signed + wire width 1 \output_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_12_logical_op__data_len + wire width 4 \output_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_12_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_12_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_12_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_12_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_12_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_12_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_12_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_12_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_12_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_12_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_12_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_12_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_12_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_12_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_12_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_12_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_12_n_ready_i + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_12_muxid$420 + wire width 2 \output_muxid$41 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176082,7 +52642,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_12_logical_op__insn_type$421 + wire width 7 \output_logical_op__insn_type$42 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -176096,151 +52656,297 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_12_logical_op__fn_unit$422 + wire width 11 \output_logical_op__fn_unit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_12_logical_op__imm_data__imm$423 + wire width 64 \output_logical_op__imm_data__imm$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__imm_data__imm_ok$424 + wire width 1 \output_logical_op__imm_data__imm_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__rc__rc$425 + wire width 1 \output_logical_op__rc__rc$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__rc__rc_ok$426 + wire width 1 \output_logical_op__rc__rc_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__oe__oe$427 + wire width 1 \output_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__oe__oe_ok$428 + wire width 1 \output_logical_op__oe__oe_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__invert_in$429 + wire width 1 \output_logical_op__invert_in$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__zero_a$430 + wire width 1 \output_logical_op__zero_a$51 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_12_logical_op__input_carry$431 + wire width 2 \output_logical_op__input_carry$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__invert_out$432 + wire width 1 \output_logical_op__invert_out$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__write_cr0$433 + wire width 1 \output_logical_op__write_cr0$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__output_carry$434 + wire width 1 \output_logical_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__is_32bit$435 + wire width 1 \output_logical_op__is_32bit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_12_logical_op__is_signed$436 + wire width 1 \output_logical_op__is_signed$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_12_logical_op__data_len$437 + wire width 4 \output_logical_op__data_len$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_12_logical_op__insn$438 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_12_ra$439 + wire width 32 \output_logical_op__insn$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so_ok + cell \output$80 \output + connect \muxid \output_muxid + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__insn \output_logical_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ov \output_xer_ov + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$41 + connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 + connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$44 + connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$45 + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 + connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$47 + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 + connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$49 + connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 + connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 + connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 + connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 + connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 + connect \logical_op__data_len$18 \output_logical_op__data_len$58 + connect \logical_op__insn$19 \output_logical_op__insn$59 + connect \o$20 \output_o$60 + connect \o_ok$21 \output_o_ok$61 + connect \cr_a$22 \output_cr_a$62 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok + end + process $group_0 + assign \output_stage_muxid 2'00 + assign \output_stage_muxid \muxid + sync init + end + process $group_1 + assign \output_stage_logical_op__insn_type 7'0000000 + assign \output_stage_logical_op__fn_unit 11'00000000000 + assign \output_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_logical_op__imm_data__imm_ok 1'0 + assign \output_stage_logical_op__rc__rc 1'0 + assign \output_stage_logical_op__rc__rc_ok 1'0 + assign \output_stage_logical_op__oe__oe 1'0 + assign \output_stage_logical_op__oe__oe_ok 1'0 + assign \output_stage_logical_op__invert_in 1'0 + assign \output_stage_logical_op__zero_a 1'0 + assign \output_stage_logical_op__input_carry 2'00 + assign \output_stage_logical_op__invert_out 1'0 + assign \output_stage_logical_op__write_cr0 1'0 + assign \output_stage_logical_op__output_carry 1'0 + assign \output_stage_logical_op__is_32bit 1'0 + assign \output_stage_logical_op__is_signed 1'0 + assign \output_stage_logical_op__data_len 4'0000 + assign \output_stage_logical_op__insn 32'00000000000000000000000000000000 + assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in { \output_stage_logical_op__oe__oe_ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__rc_ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_12_rb$440 + wire width 64 \ra$65 + process $group_19 + assign \ra$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$65 \ra + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_12_xer_so$441 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_12_divisor_neg$442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_12_dividend_neg$443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_12_dive_abs_ov32$444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_12_dive_abs_ov64$445 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_12_div_by_zero$446 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_12_divisor_radicand$447 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_12_operation$448 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_12_quotient_root$449 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_12_root_times_radicand$450 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_12_compare_lhs$451 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_12_compare_rhs$452 - cell \pipe_middle_12 \pipe_middle_12 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_12_p_valid_i - connect \p_ready_o \pipe_middle_12_p_ready_o - connect \muxid \pipe_middle_12_muxid - connect \logical_op__insn_type \pipe_middle_12_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_12_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_12_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_12_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_12_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_12_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_12_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_12_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_12_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_12_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_12_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_12_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_12_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_12_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_12_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_12_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_12_logical_op__data_len - connect \logical_op__insn \pipe_middle_12_logical_op__insn - connect \ra \pipe_middle_12_ra - connect \rb \pipe_middle_12_rb - connect \xer_so \pipe_middle_12_xer_so - connect \divisor_neg \pipe_middle_12_divisor_neg - connect \dividend_neg \pipe_middle_12_dividend_neg - connect \dive_abs_ov32 \pipe_middle_12_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_12_dive_abs_ov64 - connect \div_by_zero \pipe_middle_12_div_by_zero - connect \divisor_radicand \pipe_middle_12_divisor_radicand - connect \operation \pipe_middle_12_operation - connect \quotient_root \pipe_middle_12_quotient_root - connect \root_times_radicand \pipe_middle_12_root_times_radicand - connect \compare_lhs \pipe_middle_12_compare_lhs - connect \compare_rhs \pipe_middle_12_compare_rhs - connect \n_valid_o \pipe_middle_12_n_valid_o - connect \n_ready_i \pipe_middle_12_n_ready_i - connect \muxid$1 \pipe_middle_12_muxid$420 - connect \logical_op__insn_type$2 \pipe_middle_12_logical_op__insn_type$421 - connect \logical_op__fn_unit$3 \pipe_middle_12_logical_op__fn_unit$422 - connect \logical_op__imm_data__imm$4 \pipe_middle_12_logical_op__imm_data__imm$423 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_12_logical_op__imm_data__imm_ok$424 - connect \logical_op__rc__rc$6 \pipe_middle_12_logical_op__rc__rc$425 - connect \logical_op__rc__rc_ok$7 \pipe_middle_12_logical_op__rc__rc_ok$426 - connect \logical_op__oe__oe$8 \pipe_middle_12_logical_op__oe__oe$427 - connect \logical_op__oe__oe_ok$9 \pipe_middle_12_logical_op__oe__oe_ok$428 - connect \logical_op__invert_in$10 \pipe_middle_12_logical_op__invert_in$429 - connect \logical_op__zero_a$11 \pipe_middle_12_logical_op__zero_a$430 - connect \logical_op__input_carry$12 \pipe_middle_12_logical_op__input_carry$431 - connect \logical_op__invert_out$13 \pipe_middle_12_logical_op__invert_out$432 - connect \logical_op__write_cr0$14 \pipe_middle_12_logical_op__write_cr0$433 - connect \logical_op__output_carry$15 \pipe_middle_12_logical_op__output_carry$434 - connect \logical_op__is_32bit$16 \pipe_middle_12_logical_op__is_32bit$435 - connect \logical_op__is_signed$17 \pipe_middle_12_logical_op__is_signed$436 - connect \logical_op__data_len$18 \pipe_middle_12_logical_op__data_len$437 - connect \logical_op__insn$19 \pipe_middle_12_logical_op__insn$438 - connect \ra$20 \pipe_middle_12_ra$439 - connect \rb$21 \pipe_middle_12_rb$440 - connect \xer_so$22 \pipe_middle_12_xer_so$441 - connect \divisor_neg$23 \pipe_middle_12_divisor_neg$442 - connect \dividend_neg$24 \pipe_middle_12_dividend_neg$443 - connect \dive_abs_ov32$25 \pipe_middle_12_dive_abs_ov32$444 - connect \dive_abs_ov64$26 \pipe_middle_12_dive_abs_ov64$445 - connect \div_by_zero$27 \pipe_middle_12_div_by_zero$446 - connect \divisor_radicand$28 \pipe_middle_12_divisor_radicand$447 - connect \operation$29 \pipe_middle_12_operation$448 - connect \quotient_root$30 \pipe_middle_12_quotient_root$449 - connect \root_times_radicand$31 \pipe_middle_12_root_times_radicand$450 - connect \compare_lhs$32 \pipe_middle_12_compare_lhs$451 - connect \compare_rhs$33 \pipe_middle_12_compare_rhs$452 + wire width 64 \rb$66 + process $group_20 + assign \rb$66 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$66 \rb + sync init + end + process $group_21 + assign \output_stage_xer_so 1'0 + assign \output_stage_xer_so \xer_so + sync init + end + process $group_22 + assign \output_stage_divisor_neg 1'0 + assign \output_stage_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \output_stage_dividend_neg 1'0 + assign \output_stage_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \output_stage_dive_abs_ov32 1'0 + assign \output_stage_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \output_stage_dive_abs_ov64 1'0 + assign \output_stage_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \output_stage_div_by_zero 1'0 + assign \output_stage_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \output_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_quotient_root \quotient_root + sync init + end + process $group_28 + assign \output_stage_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_remainder \remainder + sync init + end + process $group_29 + assign \output_muxid 2'00 + assign \output_muxid \output_stage_muxid$21 + sync init + end + process $group_30 + assign \output_logical_op__insn_type 7'0000000 + assign \output_logical_op__fn_unit 11'00000000000 + assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_logical_op__imm_data__imm_ok 1'0 + assign \output_logical_op__rc__rc 1'0 + assign \output_logical_op__rc__rc_ok 1'0 + assign \output_logical_op__oe__oe 1'0 + assign \output_logical_op__oe__oe_ok 1'0 + assign \output_logical_op__invert_in 1'0 + assign \output_logical_op__zero_a 1'0 + assign \output_logical_op__input_carry 2'00 + assign \output_logical_op__invert_out 1'0 + assign \output_logical_op__write_cr0 1'0 + assign \output_logical_op__output_carry 1'0 + assign \output_logical_op__is_32bit 1'0 + assign \output_logical_op__is_signed 1'0 + assign \output_logical_op__data_len 4'0000 + assign \output_logical_op__insn 32'00000000000000000000000000000000 + assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 { \output_stage_logical_op__oe__oe_ok$29 \output_stage_logical_op__oe__oe$28 } { \output_stage_logical_op__rc__rc_ok$27 \output_stage_logical_op__rc__rc$26 } { \output_stage_logical_op__imm_data__imm_ok$25 \output_stage_logical_op__imm_data__imm$24 } \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + sync init + end + process $group_48 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$69 + process $group_50 + assign \output_cr_a 4'0000 + assign \cr_a_ok$67 1'0 + assign { \cr_a_ok$67 \output_cr_a } { \cr_a_ok$69 \cr_a$68 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$70 + process $group_52 + assign \output_xer_ov 2'00 + assign \xer_ov_ok$70 1'0 + assign { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$72 + process $group_54 + assign \output_xer_so 1'0 + assign \xer_so_ok$71 1'0 + assign { \xer_so_ok$71 \output_xer_so } { \xer_so_ok$72 \output_stage_xer_so$40 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$73 + process $group_56 + assign \p_valid_i$73 1'0 + assign \p_valid_i$73 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_57 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$73 + connect \B \p_ready_o + connect \Y $74 + end + process $group_58 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $74 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_13_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_13_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_13_muxid + wire width 2 \muxid$76 + process $group_59 + assign \muxid$76 2'00 + assign \muxid$76 \output_muxid$41 + sync init + end attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176315,7 +53021,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_13_logical_op__insn_type + wire width 7 \logical_op__insn_type$77 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -176329,77 +53035,352 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_13_logical_op__fn_unit + wire width 11 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_13_logical_op__imm_data__imm + wire width 64 \logical_op__imm_data__imm$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__imm_data__imm_ok + wire width 1 \logical_op__imm_data__imm_ok$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__rc__rc + wire width 1 \logical_op__rc__rc$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__rc__rc_ok + wire width 1 \logical_op__rc__rc_ok$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__oe__oe + wire width 1 \logical_op__oe__oe$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__oe__oe_ok + wire width 1 \logical_op__oe__oe_ok$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__invert_in + wire width 1 \logical_op__invert_in$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__zero_a + wire width 1 \logical_op__zero_a$86 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_13_logical_op__input_carry + wire width 2 \logical_op__input_carry$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__invert_out + wire width 1 \logical_op__invert_out$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__write_cr0 + wire width 1 \logical_op__write_cr0$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__output_carry + wire width 1 \logical_op__output_carry$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__is_32bit + wire width 1 \logical_op__is_32bit$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__is_signed + wire width 1 \logical_op__is_signed$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_13_logical_op__data_len + wire width 4 \logical_op__data_len$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_13_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_13_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_13_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_13_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_13_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_13_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_13_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_13_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_13_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_13_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_13_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_13_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_13_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_13_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_13_compare_rhs + wire width 32 \logical_op__insn$94 + process $group_60 + assign \logical_op__insn_type$77 7'0000000 + assign \logical_op__fn_unit$78 11'00000000000 + assign \logical_op__imm_data__imm$79 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$80 1'0 + assign \logical_op__rc__rc$81 1'0 + assign \logical_op__rc__rc_ok$82 1'0 + assign \logical_op__oe__oe$83 1'0 + assign \logical_op__oe__oe_ok$84 1'0 + assign \logical_op__invert_in$85 1'0 + assign \logical_op__zero_a$86 1'0 + assign \logical_op__input_carry$87 2'00 + assign \logical_op__invert_out$88 1'0 + assign \logical_op__write_cr0$89 1'0 + assign \logical_op__output_carry$90 1'0 + assign \logical_op__is_32bit$91 1'0 + assign \logical_op__is_signed$92 1'0 + assign \logical_op__data_len$93 4'0000 + assign \logical_op__insn$94 32'00000000000000000000000000000000 + assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 { \output_logical_op__oe__oe_ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__rc_ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__imm_ok$45 \output_logical_op__imm_data__imm$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$96 + process $group_78 + assign \o$95 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$96 1'0 + assign { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$98 + process $group_80 + assign \cr_a$97 4'0000 + assign \cr_a_ok$98 1'0 + assign { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$100 + process $group_82 + assign \xer_ov$99 2'00 + assign \xer_ov_ok$100 1'0 + assign { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$102 + process $group_84 + assign \xer_so$101 1'0 + assign \xer_so_ok$102 1'0 + assign { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_86 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_87 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$76 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_88 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_106 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next + end + process $group_108 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 + end + sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next + end + process $group_110 + assign \xer_ov$next \xer_ov + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ov_ok$next 1'0 + end + sync init + update \xer_ov 2'00 + update \xer_ov_ok 1'0 + sync posedge \coresync_clk + update \xer_ov \xer_ov$next + update \xer_ov_ok \xer_ov_ok$next + end + process $group_112 + assign \xer_so$20$next \xer_so$20 + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so$20 1'0 + update \xer_so_ok 1'0 + sync posedge \coresync_clk + update \xer_so$20 \xer_so$20$next + update \xer_so_ok \xer_so_ok$next + end + process $group_114 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_115 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" +module \alu_div0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \xer_so_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 5 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_13_n_valid_o + wire width 1 output 6 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_13_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_13_muxid$453 + wire width 1 input 7 \n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176474,7 +53455,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_13_logical_op__insn_type$454 + wire width 7 input 8 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -176488,151 +53469,75 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_13_logical_op__fn_unit$455 + wire width 11 input 9 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_13_logical_op__imm_data__imm$456 + wire width 64 input 10 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__imm_data__imm_ok$457 + wire width 1 input 11 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__rc__rc$458 + wire width 1 input 12 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__rc__rc_ok$459 + wire width 1 input 13 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__oe__oe$460 + wire width 1 input 14 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__oe__oe_ok$461 + wire width 1 input 15 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__invert_in$462 + wire width 1 input 16 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__zero_a$463 + wire width 1 input 17 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_13_logical_op__input_carry$464 + wire width 2 input 18 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__invert_out$465 + wire width 1 input 19 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__write_cr0$466 + wire width 1 input 20 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__output_carry$467 + wire width 1 input 21 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__is_32bit$468 + wire width 1 input 22 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_13_logical_op__is_signed$469 + wire width 1 input 23 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_13_logical_op__data_len$470 + wire width 4 input 24 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_13_logical_op__insn$471 + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_13_ra$472 + wire width 64 input 30 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_13_rb$473 + wire width 64 input 31 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_13_xer_so$474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_13_divisor_neg$475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_13_dividend_neg$476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_13_dive_abs_ov32$477 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_13_dive_abs_ov64$478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_13_div_by_zero$479 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_13_divisor_radicand$480 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_13_operation$481 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_13_quotient_root$482 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_13_root_times_radicand$483 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_13_compare_lhs$484 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_13_compare_rhs$485 - cell \pipe_middle_13 \pipe_middle_13 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_13_p_valid_i - connect \p_ready_o \pipe_middle_13_p_ready_o - connect \muxid \pipe_middle_13_muxid - connect \logical_op__insn_type \pipe_middle_13_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_13_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_13_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_13_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_13_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_13_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_13_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_13_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_13_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_13_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_13_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_13_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_13_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_13_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_13_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_13_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_13_logical_op__data_len - connect \logical_op__insn \pipe_middle_13_logical_op__insn - connect \ra \pipe_middle_13_ra - connect \rb \pipe_middle_13_rb - connect \xer_so \pipe_middle_13_xer_so - connect \divisor_neg \pipe_middle_13_divisor_neg - connect \dividend_neg \pipe_middle_13_dividend_neg - connect \dive_abs_ov32 \pipe_middle_13_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_13_dive_abs_ov64 - connect \div_by_zero \pipe_middle_13_div_by_zero - connect \divisor_radicand \pipe_middle_13_divisor_radicand - connect \operation \pipe_middle_13_operation - connect \quotient_root \pipe_middle_13_quotient_root - connect \root_times_radicand \pipe_middle_13_root_times_radicand - connect \compare_lhs \pipe_middle_13_compare_lhs - connect \compare_rhs \pipe_middle_13_compare_rhs - connect \n_valid_o \pipe_middle_13_n_valid_o - connect \n_ready_i \pipe_middle_13_n_ready_i - connect \muxid$1 \pipe_middle_13_muxid$453 - connect \logical_op__insn_type$2 \pipe_middle_13_logical_op__insn_type$454 - connect \logical_op__fn_unit$3 \pipe_middle_13_logical_op__fn_unit$455 - connect \logical_op__imm_data__imm$4 \pipe_middle_13_logical_op__imm_data__imm$456 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_13_logical_op__imm_data__imm_ok$457 - connect \logical_op__rc__rc$6 \pipe_middle_13_logical_op__rc__rc$458 - connect \logical_op__rc__rc_ok$7 \pipe_middle_13_logical_op__rc__rc_ok$459 - connect \logical_op__oe__oe$8 \pipe_middle_13_logical_op__oe__oe$460 - connect \logical_op__oe__oe_ok$9 \pipe_middle_13_logical_op__oe__oe_ok$461 - connect \logical_op__invert_in$10 \pipe_middle_13_logical_op__invert_in$462 - connect \logical_op__zero_a$11 \pipe_middle_13_logical_op__zero_a$463 - connect \logical_op__input_carry$12 \pipe_middle_13_logical_op__input_carry$464 - connect \logical_op__invert_out$13 \pipe_middle_13_logical_op__invert_out$465 - connect \logical_op__write_cr0$14 \pipe_middle_13_logical_op__write_cr0$466 - connect \logical_op__output_carry$15 \pipe_middle_13_logical_op__output_carry$467 - connect \logical_op__is_32bit$16 \pipe_middle_13_logical_op__is_32bit$468 - connect \logical_op__is_signed$17 \pipe_middle_13_logical_op__is_signed$469 - connect \logical_op__data_len$18 \pipe_middle_13_logical_op__data_len$470 - connect \logical_op__insn$19 \pipe_middle_13_logical_op__insn$471 - connect \ra$20 \pipe_middle_13_ra$472 - connect \rb$21 \pipe_middle_13_rb$473 - connect \xer_so$22 \pipe_middle_13_xer_so$474 - connect \divisor_neg$23 \pipe_middle_13_divisor_neg$475 - connect \dividend_neg$24 \pipe_middle_13_dividend_neg$476 - connect \dive_abs_ov32$25 \pipe_middle_13_dive_abs_ov32$477 - connect \dive_abs_ov64$26 \pipe_middle_13_dive_abs_ov64$478 - connect \div_by_zero$27 \pipe_middle_13_div_by_zero$479 - connect \divisor_radicand$28 \pipe_middle_13_divisor_radicand$480 - connect \operation$29 \pipe_middle_13_operation$481 - connect \quotient_root$30 \pipe_middle_13_quotient_root$482 - connect \root_times_radicand$31 \pipe_middle_13_root_times_radicand$483 - connect \compare_lhs$32 \pipe_middle_13_compare_lhs$484 - connect \compare_rhs$33 \pipe_middle_13_compare_rhs$485 - end + wire width 1 input 32 \xer_so$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_14_p_valid_i + wire width 1 input 33 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_14_p_ready_o + wire width 1 output 34 \p_ready_o + cell \p$71 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$72 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_start_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_14_muxid + wire width 2 \pipe_start_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176707,7 +53612,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_14_logical_op__insn_type + wire width 7 \pipe_start_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -176721,77 +53626,71 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_14_logical_op__fn_unit + wire width 11 \pipe_start_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_14_logical_op__imm_data__imm + wire width 64 \pipe_start_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__imm_data__imm_ok + wire width 1 \pipe_start_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__rc__rc + wire width 1 \pipe_start_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__rc__rc_ok + wire width 1 \pipe_start_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__oe__oe + wire width 1 \pipe_start_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__oe__oe_ok + wire width 1 \pipe_start_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__invert_in + wire width 1 \pipe_start_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__zero_a + wire width 1 \pipe_start_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_14_logical_op__input_carry + wire width 2 \pipe_start_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__invert_out + wire width 1 \pipe_start_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__write_cr0 + wire width 1 \pipe_start_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__output_carry + wire width 1 \pipe_start_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__is_32bit + wire width 1 \pipe_start_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__is_signed + wire width 1 \pipe_start_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_14_logical_op__data_len + wire width 4 \pipe_start_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_14_logical_op__insn + wire width 32 \pipe_start_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_14_ra + wire width 64 \pipe_start_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_14_rb + wire width 64 \pipe_start_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_14_xer_so + wire width 1 \pipe_start_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_14_divisor_neg + wire width 1 \pipe_start_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_14_dividend_neg + wire width 1 \pipe_start_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_14_dive_abs_ov32 + wire width 1 \pipe_start_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_14_dive_abs_ov64 + wire width 1 \pipe_start_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_14_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_14_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_14_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_14_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_14_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_14_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_14_compare_rhs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_14_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_14_n_ready_i + wire width 1 \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_start_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_14_muxid$486 + wire width 2 \pipe_start_muxid$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -176866,7 +53765,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_14_logical_op__insn_type$487 + wire width 7 \pipe_start_logical_op__insn_type$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -176880,151 +53779,115 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_14_logical_op__fn_unit$488 + wire width 11 \pipe_start_logical_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_14_logical_op__imm_data__imm$489 + wire width 64 \pipe_start_logical_op__imm_data__imm$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__imm_data__imm_ok$490 + wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__rc__rc$491 + wire width 1 \pipe_start_logical_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__rc__rc_ok$492 + wire width 1 \pipe_start_logical_op__rc__rc_ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__oe__oe$493 + wire width 1 \pipe_start_logical_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__oe__oe_ok$494 + wire width 1 \pipe_start_logical_op__oe__oe_ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__invert_in$495 + wire width 1 \pipe_start_logical_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__zero_a$496 + wire width 1 \pipe_start_logical_op__zero_a$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_14_logical_op__input_carry$497 + wire width 2 \pipe_start_logical_op__input_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__invert_out$498 + wire width 1 \pipe_start_logical_op__invert_out$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__write_cr0$499 + wire width 1 \pipe_start_logical_op__write_cr0$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__output_carry$500 + wire width 1 \pipe_start_logical_op__output_carry$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__is_32bit$501 + wire width 1 \pipe_start_logical_op__is_32bit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_14_logical_op__is_signed$502 + wire width 1 \pipe_start_logical_op__is_signed$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_14_logical_op__data_len$503 + wire width 4 \pipe_start_logical_op__data_len$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_14_logical_op__insn$504 + wire width 32 \pipe_start_logical_op__insn$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_14_ra$505 + wire width 64 \pipe_start_ra$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_14_rb$506 + wire width 64 \pipe_start_rb$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_14_xer_so$507 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_14_divisor_neg$508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_14_dividend_neg$509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_14_dive_abs_ov32$510 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_14_dive_abs_ov64$511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_14_div_by_zero$512 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_14_divisor_radicand$513 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_14_operation$514 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_14_quotient_root$515 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_14_root_times_radicand$516 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_14_compare_lhs$517 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_14_compare_rhs$518 - cell \pipe_middle_14 \pipe_middle_14 + wire width 1 \pipe_start_xer_so$23 + cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_14_p_valid_i - connect \p_ready_o \pipe_middle_14_p_ready_o - connect \muxid \pipe_middle_14_muxid - connect \logical_op__insn_type \pipe_middle_14_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_14_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_14_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_14_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_14_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_14_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_14_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_14_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_14_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_14_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_14_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_14_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_14_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_14_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_14_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_14_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_14_logical_op__data_len - connect \logical_op__insn \pipe_middle_14_logical_op__insn - connect \ra \pipe_middle_14_ra - connect \rb \pipe_middle_14_rb - connect \xer_so \pipe_middle_14_xer_so - connect \divisor_neg \pipe_middle_14_divisor_neg - connect \dividend_neg \pipe_middle_14_dividend_neg - connect \dive_abs_ov32 \pipe_middle_14_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_14_dive_abs_ov64 - connect \div_by_zero \pipe_middle_14_div_by_zero - connect \divisor_radicand \pipe_middle_14_divisor_radicand - connect \operation \pipe_middle_14_operation - connect \quotient_root \pipe_middle_14_quotient_root - connect \root_times_radicand \pipe_middle_14_root_times_radicand - connect \compare_lhs \pipe_middle_14_compare_lhs - connect \compare_rhs \pipe_middle_14_compare_rhs - connect \n_valid_o \pipe_middle_14_n_valid_o - connect \n_ready_i \pipe_middle_14_n_ready_i - connect \muxid$1 \pipe_middle_14_muxid$486 - connect \logical_op__insn_type$2 \pipe_middle_14_logical_op__insn_type$487 - connect \logical_op__fn_unit$3 \pipe_middle_14_logical_op__fn_unit$488 - connect \logical_op__imm_data__imm$4 \pipe_middle_14_logical_op__imm_data__imm$489 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_14_logical_op__imm_data__imm_ok$490 - connect \logical_op__rc__rc$6 \pipe_middle_14_logical_op__rc__rc$491 - connect \logical_op__rc__rc_ok$7 \pipe_middle_14_logical_op__rc__rc_ok$492 - connect \logical_op__oe__oe$8 \pipe_middle_14_logical_op__oe__oe$493 - connect \logical_op__oe__oe_ok$9 \pipe_middle_14_logical_op__oe__oe_ok$494 - connect \logical_op__invert_in$10 \pipe_middle_14_logical_op__invert_in$495 - connect \logical_op__zero_a$11 \pipe_middle_14_logical_op__zero_a$496 - connect \logical_op__input_carry$12 \pipe_middle_14_logical_op__input_carry$497 - connect \logical_op__invert_out$13 \pipe_middle_14_logical_op__invert_out$498 - connect \logical_op__write_cr0$14 \pipe_middle_14_logical_op__write_cr0$499 - connect \logical_op__output_carry$15 \pipe_middle_14_logical_op__output_carry$500 - connect \logical_op__is_32bit$16 \pipe_middle_14_logical_op__is_32bit$501 - connect \logical_op__is_signed$17 \pipe_middle_14_logical_op__is_signed$502 - connect \logical_op__data_len$18 \pipe_middle_14_logical_op__data_len$503 - connect \logical_op__insn$19 \pipe_middle_14_logical_op__insn$504 - connect \ra$20 \pipe_middle_14_ra$505 - connect \rb$21 \pipe_middle_14_rb$506 - connect \xer_so$22 \pipe_middle_14_xer_so$507 - connect \divisor_neg$23 \pipe_middle_14_divisor_neg$508 - connect \dividend_neg$24 \pipe_middle_14_dividend_neg$509 - connect \dive_abs_ov32$25 \pipe_middle_14_dive_abs_ov32$510 - connect \dive_abs_ov64$26 \pipe_middle_14_dive_abs_ov64$511 - connect \div_by_zero$27 \pipe_middle_14_div_by_zero$512 - connect \divisor_radicand$28 \pipe_middle_14_divisor_radicand$513 - connect \operation$29 \pipe_middle_14_operation$514 - connect \quotient_root$30 \pipe_middle_14_quotient_root$515 - connect \root_times_radicand$31 \pipe_middle_14_root_times_radicand$516 - connect \compare_lhs$32 \pipe_middle_14_compare_lhs$517 - connect \compare_rhs$33 \pipe_middle_14_compare_rhs$518 + connect \n_valid_o \pipe_start_n_valid_o + connect \n_ready_i \pipe_start_n_ready_i + connect \muxid \pipe_start_muxid + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__insn \pipe_start_logical_op__insn + connect \ra \pipe_start_ra + connect \rb \pipe_start_rb + connect \xer_so \pipe_start_xer_so + connect \divisor_neg \pipe_start_divisor_neg + connect \dividend_neg \pipe_start_dividend_neg + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \div_by_zero \pipe_start_div_by_zero + connect \dividend \pipe_start_dividend + connect \divisor_radicand \pipe_start_divisor_radicand + connect \operation \pipe_start_operation + connect \p_valid_i \pipe_start_p_valid_i + connect \p_ready_o \pipe_start_p_ready_o + connect \muxid$1 \pipe_start_muxid$2 + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5 + connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6 + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8 + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10 + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \ra$20 \pipe_start_ra$21 + connect \rb$21 \pipe_start_rb$22 + connect \xer_so$22 \pipe_start_xer_so$23 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_15_p_valid_i + wire width 1 \pipe_middle_0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_15_p_ready_o + wire width 1 \pipe_middle_0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_15_muxid + wire width 2 \pipe_middle_0_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -177099,7 +53962,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_15_logical_op__insn_type + wire width 7 \pipe_middle_0_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -177113,77 +53976,71 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_15_logical_op__fn_unit + wire width 11 \pipe_middle_0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_15_logical_op__imm_data__imm + wire width 64 \pipe_middle_0_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__imm_data__imm_ok + wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__rc__rc + wire width 1 \pipe_middle_0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__rc__rc_ok + wire width 1 \pipe_middle_0_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__oe__oe + wire width 1 \pipe_middle_0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__oe__oe_ok + wire width 1 \pipe_middle_0_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__invert_in + wire width 1 \pipe_middle_0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__zero_a + wire width 1 \pipe_middle_0_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_15_logical_op__input_carry + wire width 2 \pipe_middle_0_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__invert_out + wire width 1 \pipe_middle_0_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__write_cr0 + wire width 1 \pipe_middle_0_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__output_carry + wire width 1 \pipe_middle_0_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__is_32bit + wire width 1 \pipe_middle_0_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__is_signed + wire width 1 \pipe_middle_0_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_15_logical_op__data_len + wire width 4 \pipe_middle_0_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_15_logical_op__insn + wire width 32 \pipe_middle_0_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_15_ra + wire width 64 \pipe_middle_0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_15_rb + wire width 64 \pipe_middle_0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_15_xer_so + wire width 1 \pipe_middle_0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_15_divisor_neg + wire width 1 \pipe_middle_0_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_15_dividend_neg + wire width 1 \pipe_middle_0_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_15_dive_abs_ov32 + wire width 1 \pipe_middle_0_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_15_dive_abs_ov64 + wire width 1 \pipe_middle_0_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_15_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_15_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_15_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_15_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_15_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_15_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_15_compare_rhs + wire width 1 \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_15_n_valid_o + wire width 1 \pipe_middle_0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_15_n_ready_i + wire width 1 \pipe_middle_0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_15_muxid$519 + wire width 2 \pipe_middle_0_muxid$24 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -177258,7 +54115,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_15_logical_op__insn_type$520 + wire width 7 \pipe_middle_0_logical_op__insn_type$25 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -177272,144 +54129,129 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_15_logical_op__fn_unit$521 + wire width 11 \pipe_middle_0_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_15_logical_op__imm_data__imm$522 + wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__imm_data__imm_ok$523 + wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__rc__rc$524 + wire width 1 \pipe_middle_0_logical_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__rc__rc_ok$525 + wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__oe__oe$526 + wire width 1 \pipe_middle_0_logical_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__oe__oe_ok$527 + wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__invert_in$528 + wire width 1 \pipe_middle_0_logical_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__zero_a$529 + wire width 1 \pipe_middle_0_logical_op__zero_a$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_15_logical_op__input_carry$530 + wire width 2 \pipe_middle_0_logical_op__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__invert_out$531 + wire width 1 \pipe_middle_0_logical_op__invert_out$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__write_cr0$532 + wire width 1 \pipe_middle_0_logical_op__write_cr0$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__output_carry$533 + wire width 1 \pipe_middle_0_logical_op__output_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__is_32bit$534 + wire width 1 \pipe_middle_0_logical_op__is_32bit$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_15_logical_op__is_signed$535 + wire width 1 \pipe_middle_0_logical_op__is_signed$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_15_logical_op__data_len$536 + wire width 4 \pipe_middle_0_logical_op__data_len$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_15_logical_op__insn$537 + wire width 32 \pipe_middle_0_logical_op__insn$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_15_ra$538 + wire width 64 \pipe_middle_0_ra$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_15_rb$539 + wire width 64 \pipe_middle_0_rb$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_15_xer_so$540 + wire width 1 \pipe_middle_0_xer_so$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_15_divisor_neg$541 + wire width 1 \pipe_middle_0_divisor_neg$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_15_dividend_neg$542 + wire width 1 \pipe_middle_0_dividend_neg$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_15_dive_abs_ov32$543 + wire width 1 \pipe_middle_0_dive_abs_ov32$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_15_dive_abs_ov64$544 + wire width 1 \pipe_middle_0_dive_abs_ov64$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_15_div_by_zero$545 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_middle_15_divisor_radicand$546 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_middle_15_operation$547 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" - wire width 64 \pipe_middle_15_quotient_root$548 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_middle_15_root_times_radicand$549 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_middle_15_compare_lhs$550 - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_middle_15_compare_rhs$551 - cell \pipe_middle_15 \pipe_middle_15 + wire width 1 \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_15_p_valid_i - connect \p_ready_o \pipe_middle_15_p_ready_o - connect \muxid \pipe_middle_15_muxid - connect \logical_op__insn_type \pipe_middle_15_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_15_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_15_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_15_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_15_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_15_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_15_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_15_logical_op__oe__oe_ok - connect \logical_op__invert_in \pipe_middle_15_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_15_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_15_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_15_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_15_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_15_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_15_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_15_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_15_logical_op__data_len - connect \logical_op__insn \pipe_middle_15_logical_op__insn - connect \ra \pipe_middle_15_ra - connect \rb \pipe_middle_15_rb - connect \xer_so \pipe_middle_15_xer_so - connect \divisor_neg \pipe_middle_15_divisor_neg - connect \dividend_neg \pipe_middle_15_dividend_neg - connect \dive_abs_ov32 \pipe_middle_15_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_15_dive_abs_ov64 - connect \div_by_zero \pipe_middle_15_div_by_zero - connect \divisor_radicand \pipe_middle_15_divisor_radicand - connect \operation \pipe_middle_15_operation - connect \quotient_root \pipe_middle_15_quotient_root - connect \root_times_radicand \pipe_middle_15_root_times_radicand - connect \compare_lhs \pipe_middle_15_compare_lhs - connect \compare_rhs \pipe_middle_15_compare_rhs - connect \n_valid_o \pipe_middle_15_n_valid_o - connect \n_ready_i \pipe_middle_15_n_ready_i - connect \muxid$1 \pipe_middle_15_muxid$519 - connect \logical_op__insn_type$2 \pipe_middle_15_logical_op__insn_type$520 - connect \logical_op__fn_unit$3 \pipe_middle_15_logical_op__fn_unit$521 - connect \logical_op__imm_data__imm$4 \pipe_middle_15_logical_op__imm_data__imm$522 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_15_logical_op__imm_data__imm_ok$523 - connect \logical_op__rc__rc$6 \pipe_middle_15_logical_op__rc__rc$524 - connect \logical_op__rc__rc_ok$7 \pipe_middle_15_logical_op__rc__rc_ok$525 - connect \logical_op__oe__oe$8 \pipe_middle_15_logical_op__oe__oe$526 - connect \logical_op__oe__oe_ok$9 \pipe_middle_15_logical_op__oe__oe_ok$527 - connect \logical_op__invert_in$10 \pipe_middle_15_logical_op__invert_in$528 - connect \logical_op__zero_a$11 \pipe_middle_15_logical_op__zero_a$529 - connect \logical_op__input_carry$12 \pipe_middle_15_logical_op__input_carry$530 - connect \logical_op__invert_out$13 \pipe_middle_15_logical_op__invert_out$531 - connect \logical_op__write_cr0$14 \pipe_middle_15_logical_op__write_cr0$532 - connect \logical_op__output_carry$15 \pipe_middle_15_logical_op__output_carry$533 - connect \logical_op__is_32bit$16 \pipe_middle_15_logical_op__is_32bit$534 - connect \logical_op__is_signed$17 \pipe_middle_15_logical_op__is_signed$535 - connect \logical_op__data_len$18 \pipe_middle_15_logical_op__data_len$536 - connect \logical_op__insn$19 \pipe_middle_15_logical_op__insn$537 - connect \ra$20 \pipe_middle_15_ra$538 - connect \rb$21 \pipe_middle_15_rb$539 - connect \xer_so$22 \pipe_middle_15_xer_so$540 - connect \divisor_neg$23 \pipe_middle_15_divisor_neg$541 - connect \dividend_neg$24 \pipe_middle_15_dividend_neg$542 - connect \dive_abs_ov32$25 \pipe_middle_15_dive_abs_ov32$543 - connect \dive_abs_ov64$26 \pipe_middle_15_dive_abs_ov64$544 - connect \div_by_zero$27 \pipe_middle_15_div_by_zero$545 - connect \divisor_radicand$28 \pipe_middle_15_divisor_radicand$546 - connect \operation$29 \pipe_middle_15_operation$547 - connect \quotient_root$30 \pipe_middle_15_quotient_root$548 - connect \root_times_radicand$31 \pipe_middle_15_root_times_radicand$549 - connect \compare_lhs$32 \pipe_middle_15_compare_lhs$550 - connect \compare_rhs$33 \pipe_middle_15_compare_rhs$551 + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \muxid \pipe_middle_0_muxid + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \ra \pipe_middle_0_ra + connect \rb \pipe_middle_0_rb + connect \xer_so \pipe_middle_0_xer_so + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \dividend \pipe_middle_0_dividend + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \operation \pipe_middle_0_operation + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30 + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32 + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb$21 \pipe_middle_0_rb$44 + connect \xer_so$22 \pipe_middle_0_xer_so$45 + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \quotient_root \pipe_middle_0_quotient_root + connect \remainder \pipe_middle_0_remainder end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 \pipe_end_p_valid_i @@ -177558,24 +54400,16 @@ module \alu_div0 wire width 1 \pipe_end_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire width 1 \pipe_end_div_by_zero - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" - wire width 64 \pipe_end_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" - wire width 2 \pipe_end_operation - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \pipe_end_quotient_root - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" - wire width 128 \pipe_end_root_times_radicand - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" - wire width 192 \pipe_end_compare_lhs - attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" - wire width 192 \pipe_end_compare_rhs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \pipe_end_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire width 1 \pipe_end_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_end_muxid$552 + wire width 2 \pipe_end_muxid$51 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -177650,7 +54484,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_end_logical_op__insn_type$553 + wire width 7 \pipe_end_logical_op__insn_type$52 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -177664,43 +54498,43 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_end_logical_op__fn_unit$554 + wire width 11 \pipe_end_logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__imm$555 + wire width 64 \pipe_end_logical_op__imm_data__imm$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__imm_ok$556 + wire width 1 \pipe_end_logical_op__imm_data__imm_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc$557 + wire width 1 \pipe_end_logical_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc_ok$558 + wire width 1 \pipe_end_logical_op__rc__rc_ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe$559 + wire width 1 \pipe_end_logical_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe_ok$560 + wire width 1 \pipe_end_logical_op__oe__oe_ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_in$561 + wire width 1 \pipe_end_logical_op__invert_in$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__zero_a$562 + wire width 1 \pipe_end_logical_op__zero_a$61 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry$563 + wire width 2 \pipe_end_logical_op__input_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_out$564 + wire width 1 \pipe_end_logical_op__invert_out$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__write_cr0$565 + wire width 1 \pipe_end_logical_op__write_cr0$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__output_carry$566 + wire width 1 \pipe_end_logical_op__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_32bit$567 + wire width 1 \pipe_end_logical_op__is_32bit$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_signed$568 + wire width 1 \pipe_end_logical_op__is_signed$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len$569 + wire width 4 \pipe_end_logical_op__data_len$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn$570 + wire width 32 \pipe_end_logical_op__insn$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \pipe_end_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" @@ -177714,7 +54548,7 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_end_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_so$571 + wire width 1 \pipe_end_xer_so$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_end_xer_so_ok cell \pipe_end \pipe_end @@ -177749,40 +54583,36 @@ module \alu_div0 connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 connect \div_by_zero \pipe_end_div_by_zero - connect \divisor_radicand \pipe_end_divisor_radicand - connect \operation \pipe_end_operation connect \quotient_root \pipe_end_quotient_root - connect \root_times_radicand \pipe_end_root_times_radicand - connect \compare_lhs \pipe_end_compare_lhs - connect \compare_rhs \pipe_end_compare_rhs + connect \remainder \pipe_end_remainder connect \n_valid_o \pipe_end_n_valid_o connect \n_ready_i \pipe_end_n_ready_i - connect \muxid$1 \pipe_end_muxid$552 - connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$553 - connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$554 - connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$555 - connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$556 - connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$557 - connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$558 - connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$559 - connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$560 - connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$561 - connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$562 - connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$563 - connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$564 - connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$565 - connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$566 - connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$567 - connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$568 - connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$569 - connect \logical_op__insn$19 \pipe_end_logical_op__insn$570 + connect \muxid$1 \pipe_end_muxid$51 + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$54 + connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$55 + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$57 + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$59 + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 connect \o \pipe_end_o connect \o_ok \pipe_end_o_ok connect \cr_a \pipe_end_cr_a connect \cr_a_ok \pipe_end_cr_a_ok connect \xer_ov \pipe_end_xer_ov connect \xer_ov_ok \pipe_end_xer_ov_ok - connect \xer_so$20 \pipe_end_xer_so$571 + connect \xer_so$20 \pipe_end_xer_so$70 connect \xer_so_ok \pipe_end_xer_so_ok end process $group_0 @@ -177863,1656 +54693,36 @@ module \alu_div0 sync init end process $group_29 - assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + assign \pipe_middle_0_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_dividend \pipe_start_dividend sync init end process $group_30 - assign \pipe_middle_0_operation 2'00 - assign \pipe_middle_0_operation \pipe_start_operation + assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand sync init end process $group_31 - assign \pipe_middle_0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_quotient_root \pipe_start_quotient_root + assign \pipe_middle_0_operation 2'00 + assign \pipe_middle_0_operation \pipe_start_operation sync init end process $group_32 - assign \pipe_middle_0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_root_times_radicand \pipe_start_root_times_radicand + assign \pipe_end_p_valid_i 1'0 + assign \pipe_end_p_valid_i \pipe_middle_0_n_valid_o sync init end process $group_33 - assign \pipe_middle_0_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_compare_lhs \pipe_start_compare_lhs - sync init - end - process $group_34 - assign \pipe_middle_0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_compare_rhs \pipe_start_compare_rhs - sync init - end - process $group_35 - assign \pipe_middle_1_p_valid_i 1'0 - assign \pipe_middle_1_p_valid_i \pipe_middle_0_n_valid_o - sync init - end - process $group_36 assign \pipe_middle_0_n_ready_i 1'0 - assign \pipe_middle_0_n_ready_i \pipe_middle_1_p_ready_o - sync init - end - process $group_37 - assign \pipe_middle_1_muxid 2'00 - assign \pipe_middle_1_muxid \pipe_middle_0_muxid$24 - sync init - end - process $group_38 - assign \pipe_middle_1_logical_op__insn_type 7'0000000 - assign \pipe_middle_1_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_1_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_1_logical_op__rc__rc 1'0 - assign \pipe_middle_1_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_1_logical_op__oe__oe 1'0 - assign \pipe_middle_1_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_1_logical_op__invert_in 1'0 - assign \pipe_middle_1_logical_op__zero_a 1'0 - assign \pipe_middle_1_logical_op__input_carry 2'00 - assign \pipe_middle_1_logical_op__invert_out 1'0 - assign \pipe_middle_1_logical_op__write_cr0 1'0 - assign \pipe_middle_1_logical_op__output_carry 1'0 - assign \pipe_middle_1_logical_op__is_32bit 1'0 - assign \pipe_middle_1_logical_op__is_signed 1'0 - assign \pipe_middle_1_logical_op__data_len 4'0000 - assign \pipe_middle_1_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_1_logical_op__insn \pipe_middle_1_logical_op__data_len \pipe_middle_1_logical_op__is_signed \pipe_middle_1_logical_op__is_32bit \pipe_middle_1_logical_op__output_carry \pipe_middle_1_logical_op__write_cr0 \pipe_middle_1_logical_op__invert_out \pipe_middle_1_logical_op__input_carry \pipe_middle_1_logical_op__zero_a \pipe_middle_1_logical_op__invert_in { \pipe_middle_1_logical_op__oe__oe_ok \pipe_middle_1_logical_op__oe__oe } { \pipe_middle_1_logical_op__rc__rc_ok \pipe_middle_1_logical_op__rc__rc } { \pipe_middle_1_logical_op__imm_data__imm_ok \pipe_middle_1_logical_op__imm_data__imm } \pipe_middle_1_logical_op__fn_unit \pipe_middle_1_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } - sync init - end - process $group_56 - assign \pipe_middle_1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_ra \pipe_middle_0_ra$43 - sync init - end - process $group_57 - assign \pipe_middle_1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_rb \pipe_middle_0_rb$44 - sync init - end - process $group_58 - assign \pipe_middle_1_xer_so 1'0 - assign \pipe_middle_1_xer_so \pipe_middle_0_xer_so$45 - sync init - end - process $group_59 - assign \pipe_middle_1_divisor_neg 1'0 - assign \pipe_middle_1_divisor_neg \pipe_middle_0_divisor_neg$46 - sync init - end - process $group_60 - assign \pipe_middle_1_dividend_neg 1'0 - assign \pipe_middle_1_dividend_neg \pipe_middle_0_dividend_neg$47 - sync init - end - process $group_61 - assign \pipe_middle_1_dive_abs_ov32 1'0 - assign \pipe_middle_1_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 - sync init - end - process $group_62 - assign \pipe_middle_1_dive_abs_ov64 1'0 - assign \pipe_middle_1_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 - sync init - end - process $group_63 - assign \pipe_middle_1_div_by_zero 1'0 - assign \pipe_middle_1_div_by_zero \pipe_middle_0_div_by_zero$50 - sync init - end - process $group_64 - assign \pipe_middle_1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_divisor_radicand \pipe_middle_0_divisor_radicand$51 - sync init - end - process $group_65 - assign \pipe_middle_1_operation 2'00 - assign \pipe_middle_1_operation \pipe_middle_0_operation$52 - sync init - end - process $group_66 - assign \pipe_middle_1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_quotient_root \pipe_middle_0_quotient_root$53 - sync init - end - process $group_67 - assign \pipe_middle_1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_root_times_radicand \pipe_middle_0_root_times_radicand$54 - sync init - end - process $group_68 - assign \pipe_middle_1_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_compare_lhs \pipe_middle_0_compare_lhs$55 - sync init - end - process $group_69 - assign \pipe_middle_1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_1_compare_rhs \pipe_middle_0_compare_rhs$56 - sync init - end - process $group_70 - assign \pipe_middle_2_p_valid_i 1'0 - assign \pipe_middle_2_p_valid_i \pipe_middle_1_n_valid_o - sync init - end - process $group_71 - assign \pipe_middle_1_n_ready_i 1'0 - assign \pipe_middle_1_n_ready_i \pipe_middle_2_p_ready_o - sync init - end - process $group_72 - assign \pipe_middle_2_muxid 2'00 - assign \pipe_middle_2_muxid \pipe_middle_1_muxid$57 - sync init - end - process $group_73 - assign \pipe_middle_2_logical_op__insn_type 7'0000000 - assign \pipe_middle_2_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_2_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_2_logical_op__rc__rc 1'0 - assign \pipe_middle_2_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_2_logical_op__oe__oe 1'0 - assign \pipe_middle_2_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_2_logical_op__invert_in 1'0 - assign \pipe_middle_2_logical_op__zero_a 1'0 - assign \pipe_middle_2_logical_op__input_carry 2'00 - assign \pipe_middle_2_logical_op__invert_out 1'0 - assign \pipe_middle_2_logical_op__write_cr0 1'0 - assign \pipe_middle_2_logical_op__output_carry 1'0 - assign \pipe_middle_2_logical_op__is_32bit 1'0 - assign \pipe_middle_2_logical_op__is_signed 1'0 - assign \pipe_middle_2_logical_op__data_len 4'0000 - assign \pipe_middle_2_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_2_logical_op__insn \pipe_middle_2_logical_op__data_len \pipe_middle_2_logical_op__is_signed \pipe_middle_2_logical_op__is_32bit \pipe_middle_2_logical_op__output_carry \pipe_middle_2_logical_op__write_cr0 \pipe_middle_2_logical_op__invert_out \pipe_middle_2_logical_op__input_carry \pipe_middle_2_logical_op__zero_a \pipe_middle_2_logical_op__invert_in { \pipe_middle_2_logical_op__oe__oe_ok \pipe_middle_2_logical_op__oe__oe } { \pipe_middle_2_logical_op__rc__rc_ok \pipe_middle_2_logical_op__rc__rc } { \pipe_middle_2_logical_op__imm_data__imm_ok \pipe_middle_2_logical_op__imm_data__imm } \pipe_middle_2_logical_op__fn_unit \pipe_middle_2_logical_op__insn_type } { \pipe_middle_1_logical_op__insn$75 \pipe_middle_1_logical_op__data_len$74 \pipe_middle_1_logical_op__is_signed$73 \pipe_middle_1_logical_op__is_32bit$72 \pipe_middle_1_logical_op__output_carry$71 \pipe_middle_1_logical_op__write_cr0$70 \pipe_middle_1_logical_op__invert_out$69 \pipe_middle_1_logical_op__input_carry$68 \pipe_middle_1_logical_op__zero_a$67 \pipe_middle_1_logical_op__invert_in$66 { \pipe_middle_1_logical_op__oe__oe_ok$65 \pipe_middle_1_logical_op__oe__oe$64 } { \pipe_middle_1_logical_op__rc__rc_ok$63 \pipe_middle_1_logical_op__rc__rc$62 } { \pipe_middle_1_logical_op__imm_data__imm_ok$61 \pipe_middle_1_logical_op__imm_data__imm$60 } \pipe_middle_1_logical_op__fn_unit$59 \pipe_middle_1_logical_op__insn_type$58 } - sync init - end - process $group_91 - assign \pipe_middle_2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_ra \pipe_middle_1_ra$76 - sync init - end - process $group_92 - assign \pipe_middle_2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_rb \pipe_middle_1_rb$77 - sync init - end - process $group_93 - assign \pipe_middle_2_xer_so 1'0 - assign \pipe_middle_2_xer_so \pipe_middle_1_xer_so$78 - sync init - end - process $group_94 - assign \pipe_middle_2_divisor_neg 1'0 - assign \pipe_middle_2_divisor_neg \pipe_middle_1_divisor_neg$79 - sync init - end - process $group_95 - assign \pipe_middle_2_dividend_neg 1'0 - assign \pipe_middle_2_dividend_neg \pipe_middle_1_dividend_neg$80 - sync init - end - process $group_96 - assign \pipe_middle_2_dive_abs_ov32 1'0 - assign \pipe_middle_2_dive_abs_ov32 \pipe_middle_1_dive_abs_ov32$81 - sync init - end - process $group_97 - assign \pipe_middle_2_dive_abs_ov64 1'0 - assign \pipe_middle_2_dive_abs_ov64 \pipe_middle_1_dive_abs_ov64$82 - sync init - end - process $group_98 - assign \pipe_middle_2_div_by_zero 1'0 - assign \pipe_middle_2_div_by_zero \pipe_middle_1_div_by_zero$83 - sync init - end - process $group_99 - assign \pipe_middle_2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_divisor_radicand \pipe_middle_1_divisor_radicand$84 - sync init - end - process $group_100 - assign \pipe_middle_2_operation 2'00 - assign \pipe_middle_2_operation \pipe_middle_1_operation$85 - sync init - end - process $group_101 - assign \pipe_middle_2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_quotient_root \pipe_middle_1_quotient_root$86 - sync init - end - process $group_102 - assign \pipe_middle_2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_root_times_radicand \pipe_middle_1_root_times_radicand$87 - sync init - end - process $group_103 - assign \pipe_middle_2_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_compare_lhs \pipe_middle_1_compare_lhs$88 - sync init - end - process $group_104 - assign \pipe_middle_2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_2_compare_rhs \pipe_middle_1_compare_rhs$89 - sync init - end - process $group_105 - assign \pipe_middle_3_p_valid_i 1'0 - assign \pipe_middle_3_p_valid_i \pipe_middle_2_n_valid_o - sync init - end - process $group_106 - assign \pipe_middle_2_n_ready_i 1'0 - assign \pipe_middle_2_n_ready_i \pipe_middle_3_p_ready_o - sync init - end - process $group_107 - assign \pipe_middle_3_muxid 2'00 - assign \pipe_middle_3_muxid \pipe_middle_2_muxid$90 - sync init - end - process $group_108 - assign \pipe_middle_3_logical_op__insn_type 7'0000000 - assign \pipe_middle_3_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_3_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_3_logical_op__rc__rc 1'0 - assign \pipe_middle_3_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_3_logical_op__oe__oe 1'0 - assign \pipe_middle_3_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_3_logical_op__invert_in 1'0 - assign \pipe_middle_3_logical_op__zero_a 1'0 - assign \pipe_middle_3_logical_op__input_carry 2'00 - assign \pipe_middle_3_logical_op__invert_out 1'0 - assign \pipe_middle_3_logical_op__write_cr0 1'0 - assign \pipe_middle_3_logical_op__output_carry 1'0 - assign \pipe_middle_3_logical_op__is_32bit 1'0 - assign \pipe_middle_3_logical_op__is_signed 1'0 - assign \pipe_middle_3_logical_op__data_len 4'0000 - assign \pipe_middle_3_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_3_logical_op__insn \pipe_middle_3_logical_op__data_len \pipe_middle_3_logical_op__is_signed \pipe_middle_3_logical_op__is_32bit \pipe_middle_3_logical_op__output_carry \pipe_middle_3_logical_op__write_cr0 \pipe_middle_3_logical_op__invert_out \pipe_middle_3_logical_op__input_carry \pipe_middle_3_logical_op__zero_a \pipe_middle_3_logical_op__invert_in { \pipe_middle_3_logical_op__oe__oe_ok \pipe_middle_3_logical_op__oe__oe } { \pipe_middle_3_logical_op__rc__rc_ok \pipe_middle_3_logical_op__rc__rc } { \pipe_middle_3_logical_op__imm_data__imm_ok \pipe_middle_3_logical_op__imm_data__imm } \pipe_middle_3_logical_op__fn_unit \pipe_middle_3_logical_op__insn_type } { \pipe_middle_2_logical_op__insn$108 \pipe_middle_2_logical_op__data_len$107 \pipe_middle_2_logical_op__is_signed$106 \pipe_middle_2_logical_op__is_32bit$105 \pipe_middle_2_logical_op__output_carry$104 \pipe_middle_2_logical_op__write_cr0$103 \pipe_middle_2_logical_op__invert_out$102 \pipe_middle_2_logical_op__input_carry$101 \pipe_middle_2_logical_op__zero_a$100 \pipe_middle_2_logical_op__invert_in$99 { \pipe_middle_2_logical_op__oe__oe_ok$98 \pipe_middle_2_logical_op__oe__oe$97 } { \pipe_middle_2_logical_op__rc__rc_ok$96 \pipe_middle_2_logical_op__rc__rc$95 } { \pipe_middle_2_logical_op__imm_data__imm_ok$94 \pipe_middle_2_logical_op__imm_data__imm$93 } \pipe_middle_2_logical_op__fn_unit$92 \pipe_middle_2_logical_op__insn_type$91 } - sync init - end - process $group_126 - assign \pipe_middle_3_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_ra \pipe_middle_2_ra$109 - sync init - end - process $group_127 - assign \pipe_middle_3_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_rb \pipe_middle_2_rb$110 - sync init - end - process $group_128 - assign \pipe_middle_3_xer_so 1'0 - assign \pipe_middle_3_xer_so \pipe_middle_2_xer_so$111 - sync init - end - process $group_129 - assign \pipe_middle_3_divisor_neg 1'0 - assign \pipe_middle_3_divisor_neg \pipe_middle_2_divisor_neg$112 - sync init - end - process $group_130 - assign \pipe_middle_3_dividend_neg 1'0 - assign \pipe_middle_3_dividend_neg \pipe_middle_2_dividend_neg$113 - sync init - end - process $group_131 - assign \pipe_middle_3_dive_abs_ov32 1'0 - assign \pipe_middle_3_dive_abs_ov32 \pipe_middle_2_dive_abs_ov32$114 - sync init - end - process $group_132 - assign \pipe_middle_3_dive_abs_ov64 1'0 - assign \pipe_middle_3_dive_abs_ov64 \pipe_middle_2_dive_abs_ov64$115 - sync init - end - process $group_133 - assign \pipe_middle_3_div_by_zero 1'0 - assign \pipe_middle_3_div_by_zero \pipe_middle_2_div_by_zero$116 - sync init - end - process $group_134 - assign \pipe_middle_3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_divisor_radicand \pipe_middle_2_divisor_radicand$117 - sync init - end - process $group_135 - assign \pipe_middle_3_operation 2'00 - assign \pipe_middle_3_operation \pipe_middle_2_operation$118 - sync init - end - process $group_136 - assign \pipe_middle_3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_quotient_root \pipe_middle_2_quotient_root$119 - sync init - end - process $group_137 - assign \pipe_middle_3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_root_times_radicand \pipe_middle_2_root_times_radicand$120 - sync init - end - process $group_138 - assign \pipe_middle_3_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_compare_lhs \pipe_middle_2_compare_lhs$121 - sync init - end - process $group_139 - assign \pipe_middle_3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_3_compare_rhs \pipe_middle_2_compare_rhs$122 - sync init - end - process $group_140 - assign \pipe_middle_4_p_valid_i 1'0 - assign \pipe_middle_4_p_valid_i \pipe_middle_3_n_valid_o - sync init - end - process $group_141 - assign \pipe_middle_3_n_ready_i 1'0 - assign \pipe_middle_3_n_ready_i \pipe_middle_4_p_ready_o - sync init - end - process $group_142 - assign \pipe_middle_4_muxid 2'00 - assign \pipe_middle_4_muxid \pipe_middle_3_muxid$123 - sync init - end - process $group_143 - assign \pipe_middle_4_logical_op__insn_type 7'0000000 - assign \pipe_middle_4_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_4_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_4_logical_op__rc__rc 1'0 - assign \pipe_middle_4_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_4_logical_op__oe__oe 1'0 - assign \pipe_middle_4_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_4_logical_op__invert_in 1'0 - assign \pipe_middle_4_logical_op__zero_a 1'0 - assign \pipe_middle_4_logical_op__input_carry 2'00 - assign \pipe_middle_4_logical_op__invert_out 1'0 - assign \pipe_middle_4_logical_op__write_cr0 1'0 - assign \pipe_middle_4_logical_op__output_carry 1'0 - assign \pipe_middle_4_logical_op__is_32bit 1'0 - assign \pipe_middle_4_logical_op__is_signed 1'0 - assign \pipe_middle_4_logical_op__data_len 4'0000 - assign \pipe_middle_4_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_4_logical_op__insn \pipe_middle_4_logical_op__data_len \pipe_middle_4_logical_op__is_signed \pipe_middle_4_logical_op__is_32bit \pipe_middle_4_logical_op__output_carry \pipe_middle_4_logical_op__write_cr0 \pipe_middle_4_logical_op__invert_out \pipe_middle_4_logical_op__input_carry \pipe_middle_4_logical_op__zero_a \pipe_middle_4_logical_op__invert_in { \pipe_middle_4_logical_op__oe__oe_ok \pipe_middle_4_logical_op__oe__oe } { \pipe_middle_4_logical_op__rc__rc_ok \pipe_middle_4_logical_op__rc__rc } { \pipe_middle_4_logical_op__imm_data__imm_ok \pipe_middle_4_logical_op__imm_data__imm } \pipe_middle_4_logical_op__fn_unit \pipe_middle_4_logical_op__insn_type } { \pipe_middle_3_logical_op__insn$141 \pipe_middle_3_logical_op__data_len$140 \pipe_middle_3_logical_op__is_signed$139 \pipe_middle_3_logical_op__is_32bit$138 \pipe_middle_3_logical_op__output_carry$137 \pipe_middle_3_logical_op__write_cr0$136 \pipe_middle_3_logical_op__invert_out$135 \pipe_middle_3_logical_op__input_carry$134 \pipe_middle_3_logical_op__zero_a$133 \pipe_middle_3_logical_op__invert_in$132 { \pipe_middle_3_logical_op__oe__oe_ok$131 \pipe_middle_3_logical_op__oe__oe$130 } { \pipe_middle_3_logical_op__rc__rc_ok$129 \pipe_middle_3_logical_op__rc__rc$128 } { \pipe_middle_3_logical_op__imm_data__imm_ok$127 \pipe_middle_3_logical_op__imm_data__imm$126 } \pipe_middle_3_logical_op__fn_unit$125 \pipe_middle_3_logical_op__insn_type$124 } - sync init - end - process $group_161 - assign \pipe_middle_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_ra \pipe_middle_3_ra$142 - sync init - end - process $group_162 - assign \pipe_middle_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_rb \pipe_middle_3_rb$143 - sync init - end - process $group_163 - assign \pipe_middle_4_xer_so 1'0 - assign \pipe_middle_4_xer_so \pipe_middle_3_xer_so$144 - sync init - end - process $group_164 - assign \pipe_middle_4_divisor_neg 1'0 - assign \pipe_middle_4_divisor_neg \pipe_middle_3_divisor_neg$145 - sync init - end - process $group_165 - assign \pipe_middle_4_dividend_neg 1'0 - assign \pipe_middle_4_dividend_neg \pipe_middle_3_dividend_neg$146 - sync init - end - process $group_166 - assign \pipe_middle_4_dive_abs_ov32 1'0 - assign \pipe_middle_4_dive_abs_ov32 \pipe_middle_3_dive_abs_ov32$147 - sync init - end - process $group_167 - assign \pipe_middle_4_dive_abs_ov64 1'0 - assign \pipe_middle_4_dive_abs_ov64 \pipe_middle_3_dive_abs_ov64$148 - sync init - end - process $group_168 - assign \pipe_middle_4_div_by_zero 1'0 - assign \pipe_middle_4_div_by_zero \pipe_middle_3_div_by_zero$149 - sync init - end - process $group_169 - assign \pipe_middle_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_divisor_radicand \pipe_middle_3_divisor_radicand$150 - sync init - end - process $group_170 - assign \pipe_middle_4_operation 2'00 - assign \pipe_middle_4_operation \pipe_middle_3_operation$151 - sync init - end - process $group_171 - assign \pipe_middle_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_quotient_root \pipe_middle_3_quotient_root$152 - sync init - end - process $group_172 - assign \pipe_middle_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_root_times_radicand \pipe_middle_3_root_times_radicand$153 - sync init - end - process $group_173 - assign \pipe_middle_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_compare_lhs \pipe_middle_3_compare_lhs$154 - sync init - end - process $group_174 - assign \pipe_middle_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_4_compare_rhs \pipe_middle_3_compare_rhs$155 - sync init - end - process $group_175 - assign \pipe_middle_5_p_valid_i 1'0 - assign \pipe_middle_5_p_valid_i \pipe_middle_4_n_valid_o - sync init - end - process $group_176 - assign \pipe_middle_4_n_ready_i 1'0 - assign \pipe_middle_4_n_ready_i \pipe_middle_5_p_ready_o - sync init - end - process $group_177 - assign \pipe_middle_5_muxid 2'00 - assign \pipe_middle_5_muxid \pipe_middle_4_muxid$156 - sync init - end - process $group_178 - assign \pipe_middle_5_logical_op__insn_type 7'0000000 - assign \pipe_middle_5_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_5_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_5_logical_op__rc__rc 1'0 - assign \pipe_middle_5_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_5_logical_op__oe__oe 1'0 - assign \pipe_middle_5_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_5_logical_op__invert_in 1'0 - assign \pipe_middle_5_logical_op__zero_a 1'0 - assign \pipe_middle_5_logical_op__input_carry 2'00 - assign \pipe_middle_5_logical_op__invert_out 1'0 - assign \pipe_middle_5_logical_op__write_cr0 1'0 - assign \pipe_middle_5_logical_op__output_carry 1'0 - assign \pipe_middle_5_logical_op__is_32bit 1'0 - assign \pipe_middle_5_logical_op__is_signed 1'0 - assign \pipe_middle_5_logical_op__data_len 4'0000 - assign \pipe_middle_5_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_5_logical_op__insn \pipe_middle_5_logical_op__data_len \pipe_middle_5_logical_op__is_signed \pipe_middle_5_logical_op__is_32bit \pipe_middle_5_logical_op__output_carry \pipe_middle_5_logical_op__write_cr0 \pipe_middle_5_logical_op__invert_out \pipe_middle_5_logical_op__input_carry \pipe_middle_5_logical_op__zero_a \pipe_middle_5_logical_op__invert_in { \pipe_middle_5_logical_op__oe__oe_ok \pipe_middle_5_logical_op__oe__oe } { \pipe_middle_5_logical_op__rc__rc_ok \pipe_middle_5_logical_op__rc__rc } { \pipe_middle_5_logical_op__imm_data__imm_ok \pipe_middle_5_logical_op__imm_data__imm } \pipe_middle_5_logical_op__fn_unit \pipe_middle_5_logical_op__insn_type } { \pipe_middle_4_logical_op__insn$174 \pipe_middle_4_logical_op__data_len$173 \pipe_middle_4_logical_op__is_signed$172 \pipe_middle_4_logical_op__is_32bit$171 \pipe_middle_4_logical_op__output_carry$170 \pipe_middle_4_logical_op__write_cr0$169 \pipe_middle_4_logical_op__invert_out$168 \pipe_middle_4_logical_op__input_carry$167 \pipe_middle_4_logical_op__zero_a$166 \pipe_middle_4_logical_op__invert_in$165 { \pipe_middle_4_logical_op__oe__oe_ok$164 \pipe_middle_4_logical_op__oe__oe$163 } { \pipe_middle_4_logical_op__rc__rc_ok$162 \pipe_middle_4_logical_op__rc__rc$161 } { \pipe_middle_4_logical_op__imm_data__imm_ok$160 \pipe_middle_4_logical_op__imm_data__imm$159 } \pipe_middle_4_logical_op__fn_unit$158 \pipe_middle_4_logical_op__insn_type$157 } - sync init - end - process $group_196 - assign \pipe_middle_5_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_ra \pipe_middle_4_ra$175 - sync init - end - process $group_197 - assign \pipe_middle_5_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_rb \pipe_middle_4_rb$176 - sync init - end - process $group_198 - assign \pipe_middle_5_xer_so 1'0 - assign \pipe_middle_5_xer_so \pipe_middle_4_xer_so$177 - sync init - end - process $group_199 - assign \pipe_middle_5_divisor_neg 1'0 - assign \pipe_middle_5_divisor_neg \pipe_middle_4_divisor_neg$178 - sync init - end - process $group_200 - assign \pipe_middle_5_dividend_neg 1'0 - assign \pipe_middle_5_dividend_neg \pipe_middle_4_dividend_neg$179 - sync init - end - process $group_201 - assign \pipe_middle_5_dive_abs_ov32 1'0 - assign \pipe_middle_5_dive_abs_ov32 \pipe_middle_4_dive_abs_ov32$180 - sync init - end - process $group_202 - assign \pipe_middle_5_dive_abs_ov64 1'0 - assign \pipe_middle_5_dive_abs_ov64 \pipe_middle_4_dive_abs_ov64$181 - sync init - end - process $group_203 - assign \pipe_middle_5_div_by_zero 1'0 - assign \pipe_middle_5_div_by_zero \pipe_middle_4_div_by_zero$182 - sync init - end - process $group_204 - assign \pipe_middle_5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_divisor_radicand \pipe_middle_4_divisor_radicand$183 - sync init - end - process $group_205 - assign \pipe_middle_5_operation 2'00 - assign \pipe_middle_5_operation \pipe_middle_4_operation$184 - sync init - end - process $group_206 - assign \pipe_middle_5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_quotient_root \pipe_middle_4_quotient_root$185 - sync init - end - process $group_207 - assign \pipe_middle_5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_root_times_radicand \pipe_middle_4_root_times_radicand$186 - sync init - end - process $group_208 - assign \pipe_middle_5_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_compare_lhs \pipe_middle_4_compare_lhs$187 - sync init - end - process $group_209 - assign \pipe_middle_5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_5_compare_rhs \pipe_middle_4_compare_rhs$188 - sync init - end - process $group_210 - assign \pipe_middle_6_p_valid_i 1'0 - assign \pipe_middle_6_p_valid_i \pipe_middle_5_n_valid_o - sync init - end - process $group_211 - assign \pipe_middle_5_n_ready_i 1'0 - assign \pipe_middle_5_n_ready_i \pipe_middle_6_p_ready_o - sync init - end - process $group_212 - assign \pipe_middle_6_muxid 2'00 - assign \pipe_middle_6_muxid \pipe_middle_5_muxid$189 - sync init - end - process $group_213 - assign \pipe_middle_6_logical_op__insn_type 7'0000000 - assign \pipe_middle_6_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_6_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_6_logical_op__rc__rc 1'0 - assign \pipe_middle_6_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_6_logical_op__oe__oe 1'0 - assign \pipe_middle_6_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_6_logical_op__invert_in 1'0 - assign \pipe_middle_6_logical_op__zero_a 1'0 - assign \pipe_middle_6_logical_op__input_carry 2'00 - assign \pipe_middle_6_logical_op__invert_out 1'0 - assign \pipe_middle_6_logical_op__write_cr0 1'0 - assign \pipe_middle_6_logical_op__output_carry 1'0 - assign \pipe_middle_6_logical_op__is_32bit 1'0 - assign \pipe_middle_6_logical_op__is_signed 1'0 - assign \pipe_middle_6_logical_op__data_len 4'0000 - assign \pipe_middle_6_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_6_logical_op__insn \pipe_middle_6_logical_op__data_len \pipe_middle_6_logical_op__is_signed \pipe_middle_6_logical_op__is_32bit \pipe_middle_6_logical_op__output_carry \pipe_middle_6_logical_op__write_cr0 \pipe_middle_6_logical_op__invert_out \pipe_middle_6_logical_op__input_carry \pipe_middle_6_logical_op__zero_a \pipe_middle_6_logical_op__invert_in { \pipe_middle_6_logical_op__oe__oe_ok \pipe_middle_6_logical_op__oe__oe } { \pipe_middle_6_logical_op__rc__rc_ok \pipe_middle_6_logical_op__rc__rc } { \pipe_middle_6_logical_op__imm_data__imm_ok \pipe_middle_6_logical_op__imm_data__imm } \pipe_middle_6_logical_op__fn_unit \pipe_middle_6_logical_op__insn_type } { \pipe_middle_5_logical_op__insn$207 \pipe_middle_5_logical_op__data_len$206 \pipe_middle_5_logical_op__is_signed$205 \pipe_middle_5_logical_op__is_32bit$204 \pipe_middle_5_logical_op__output_carry$203 \pipe_middle_5_logical_op__write_cr0$202 \pipe_middle_5_logical_op__invert_out$201 \pipe_middle_5_logical_op__input_carry$200 \pipe_middle_5_logical_op__zero_a$199 \pipe_middle_5_logical_op__invert_in$198 { \pipe_middle_5_logical_op__oe__oe_ok$197 \pipe_middle_5_logical_op__oe__oe$196 } { \pipe_middle_5_logical_op__rc__rc_ok$195 \pipe_middle_5_logical_op__rc__rc$194 } { \pipe_middle_5_logical_op__imm_data__imm_ok$193 \pipe_middle_5_logical_op__imm_data__imm$192 } \pipe_middle_5_logical_op__fn_unit$191 \pipe_middle_5_logical_op__insn_type$190 } - sync init - end - process $group_231 - assign \pipe_middle_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_ra \pipe_middle_5_ra$208 - sync init - end - process $group_232 - assign \pipe_middle_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_rb \pipe_middle_5_rb$209 - sync init - end - process $group_233 - assign \pipe_middle_6_xer_so 1'0 - assign \pipe_middle_6_xer_so \pipe_middle_5_xer_so$210 - sync init - end - process $group_234 - assign \pipe_middle_6_divisor_neg 1'0 - assign \pipe_middle_6_divisor_neg \pipe_middle_5_divisor_neg$211 - sync init - end - process $group_235 - assign \pipe_middle_6_dividend_neg 1'0 - assign \pipe_middle_6_dividend_neg \pipe_middle_5_dividend_neg$212 - sync init - end - process $group_236 - assign \pipe_middle_6_dive_abs_ov32 1'0 - assign \pipe_middle_6_dive_abs_ov32 \pipe_middle_5_dive_abs_ov32$213 - sync init - end - process $group_237 - assign \pipe_middle_6_dive_abs_ov64 1'0 - assign \pipe_middle_6_dive_abs_ov64 \pipe_middle_5_dive_abs_ov64$214 - sync init - end - process $group_238 - assign \pipe_middle_6_div_by_zero 1'0 - assign \pipe_middle_6_div_by_zero \pipe_middle_5_div_by_zero$215 - sync init - end - process $group_239 - assign \pipe_middle_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_divisor_radicand \pipe_middle_5_divisor_radicand$216 - sync init - end - process $group_240 - assign \pipe_middle_6_operation 2'00 - assign \pipe_middle_6_operation \pipe_middle_5_operation$217 - sync init - end - process $group_241 - assign \pipe_middle_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_quotient_root \pipe_middle_5_quotient_root$218 - sync init - end - process $group_242 - assign \pipe_middle_6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_root_times_radicand \pipe_middle_5_root_times_radicand$219 - sync init - end - process $group_243 - assign \pipe_middle_6_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_compare_lhs \pipe_middle_5_compare_lhs$220 - sync init - end - process $group_244 - assign \pipe_middle_6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_6_compare_rhs \pipe_middle_5_compare_rhs$221 - sync init - end - process $group_245 - assign \pipe_middle_7_p_valid_i 1'0 - assign \pipe_middle_7_p_valid_i \pipe_middle_6_n_valid_o - sync init - end - process $group_246 - assign \pipe_middle_6_n_ready_i 1'0 - assign \pipe_middle_6_n_ready_i \pipe_middle_7_p_ready_o - sync init - end - process $group_247 - assign \pipe_middle_7_muxid 2'00 - assign \pipe_middle_7_muxid \pipe_middle_6_muxid$222 - sync init - end - process $group_248 - assign \pipe_middle_7_logical_op__insn_type 7'0000000 - assign \pipe_middle_7_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_7_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_7_logical_op__rc__rc 1'0 - assign \pipe_middle_7_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_7_logical_op__oe__oe 1'0 - assign \pipe_middle_7_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_7_logical_op__invert_in 1'0 - assign \pipe_middle_7_logical_op__zero_a 1'0 - assign \pipe_middle_7_logical_op__input_carry 2'00 - assign \pipe_middle_7_logical_op__invert_out 1'0 - assign \pipe_middle_7_logical_op__write_cr0 1'0 - assign \pipe_middle_7_logical_op__output_carry 1'0 - assign \pipe_middle_7_logical_op__is_32bit 1'0 - assign \pipe_middle_7_logical_op__is_signed 1'0 - assign \pipe_middle_7_logical_op__data_len 4'0000 - assign \pipe_middle_7_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_7_logical_op__insn \pipe_middle_7_logical_op__data_len \pipe_middle_7_logical_op__is_signed \pipe_middle_7_logical_op__is_32bit \pipe_middle_7_logical_op__output_carry \pipe_middle_7_logical_op__write_cr0 \pipe_middle_7_logical_op__invert_out \pipe_middle_7_logical_op__input_carry \pipe_middle_7_logical_op__zero_a \pipe_middle_7_logical_op__invert_in { \pipe_middle_7_logical_op__oe__oe_ok \pipe_middle_7_logical_op__oe__oe } { \pipe_middle_7_logical_op__rc__rc_ok \pipe_middle_7_logical_op__rc__rc } { \pipe_middle_7_logical_op__imm_data__imm_ok \pipe_middle_7_logical_op__imm_data__imm } \pipe_middle_7_logical_op__fn_unit \pipe_middle_7_logical_op__insn_type } { \pipe_middle_6_logical_op__insn$240 \pipe_middle_6_logical_op__data_len$239 \pipe_middle_6_logical_op__is_signed$238 \pipe_middle_6_logical_op__is_32bit$237 \pipe_middle_6_logical_op__output_carry$236 \pipe_middle_6_logical_op__write_cr0$235 \pipe_middle_6_logical_op__invert_out$234 \pipe_middle_6_logical_op__input_carry$233 \pipe_middle_6_logical_op__zero_a$232 \pipe_middle_6_logical_op__invert_in$231 { \pipe_middle_6_logical_op__oe__oe_ok$230 \pipe_middle_6_logical_op__oe__oe$229 } { \pipe_middle_6_logical_op__rc__rc_ok$228 \pipe_middle_6_logical_op__rc__rc$227 } { \pipe_middle_6_logical_op__imm_data__imm_ok$226 \pipe_middle_6_logical_op__imm_data__imm$225 } \pipe_middle_6_logical_op__fn_unit$224 \pipe_middle_6_logical_op__insn_type$223 } - sync init - end - process $group_266 - assign \pipe_middle_7_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_ra \pipe_middle_6_ra$241 - sync init - end - process $group_267 - assign \pipe_middle_7_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_rb \pipe_middle_6_rb$242 - sync init - end - process $group_268 - assign \pipe_middle_7_xer_so 1'0 - assign \pipe_middle_7_xer_so \pipe_middle_6_xer_so$243 - sync init - end - process $group_269 - assign \pipe_middle_7_divisor_neg 1'0 - assign \pipe_middle_7_divisor_neg \pipe_middle_6_divisor_neg$244 - sync init - end - process $group_270 - assign \pipe_middle_7_dividend_neg 1'0 - assign \pipe_middle_7_dividend_neg \pipe_middle_6_dividend_neg$245 - sync init - end - process $group_271 - assign \pipe_middle_7_dive_abs_ov32 1'0 - assign \pipe_middle_7_dive_abs_ov32 \pipe_middle_6_dive_abs_ov32$246 - sync init - end - process $group_272 - assign \pipe_middle_7_dive_abs_ov64 1'0 - assign \pipe_middle_7_dive_abs_ov64 \pipe_middle_6_dive_abs_ov64$247 - sync init - end - process $group_273 - assign \pipe_middle_7_div_by_zero 1'0 - assign \pipe_middle_7_div_by_zero \pipe_middle_6_div_by_zero$248 - sync init - end - process $group_274 - assign \pipe_middle_7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_divisor_radicand \pipe_middle_6_divisor_radicand$249 - sync init - end - process $group_275 - assign \pipe_middle_7_operation 2'00 - assign \pipe_middle_7_operation \pipe_middle_6_operation$250 - sync init - end - process $group_276 - assign \pipe_middle_7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_quotient_root \pipe_middle_6_quotient_root$251 - sync init - end - process $group_277 - assign \pipe_middle_7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_root_times_radicand \pipe_middle_6_root_times_radicand$252 - sync init - end - process $group_278 - assign \pipe_middle_7_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_compare_lhs \pipe_middle_6_compare_lhs$253 - sync init - end - process $group_279 - assign \pipe_middle_7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_7_compare_rhs \pipe_middle_6_compare_rhs$254 - sync init - end - process $group_280 - assign \pipe_middle_8_p_valid_i 1'0 - assign \pipe_middle_8_p_valid_i \pipe_middle_7_n_valid_o - sync init - end - process $group_281 - assign \pipe_middle_7_n_ready_i 1'0 - assign \pipe_middle_7_n_ready_i \pipe_middle_8_p_ready_o - sync init - end - process $group_282 - assign \pipe_middle_8_muxid 2'00 - assign \pipe_middle_8_muxid \pipe_middle_7_muxid$255 - sync init - end - process $group_283 - assign \pipe_middle_8_logical_op__insn_type 7'0000000 - assign \pipe_middle_8_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_8_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_8_logical_op__rc__rc 1'0 - assign \pipe_middle_8_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_8_logical_op__oe__oe 1'0 - assign \pipe_middle_8_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_8_logical_op__invert_in 1'0 - assign \pipe_middle_8_logical_op__zero_a 1'0 - assign \pipe_middle_8_logical_op__input_carry 2'00 - assign \pipe_middle_8_logical_op__invert_out 1'0 - assign \pipe_middle_8_logical_op__write_cr0 1'0 - assign \pipe_middle_8_logical_op__output_carry 1'0 - assign \pipe_middle_8_logical_op__is_32bit 1'0 - assign \pipe_middle_8_logical_op__is_signed 1'0 - assign \pipe_middle_8_logical_op__data_len 4'0000 - assign \pipe_middle_8_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_8_logical_op__insn \pipe_middle_8_logical_op__data_len \pipe_middle_8_logical_op__is_signed \pipe_middle_8_logical_op__is_32bit \pipe_middle_8_logical_op__output_carry \pipe_middle_8_logical_op__write_cr0 \pipe_middle_8_logical_op__invert_out \pipe_middle_8_logical_op__input_carry \pipe_middle_8_logical_op__zero_a \pipe_middle_8_logical_op__invert_in { \pipe_middle_8_logical_op__oe__oe_ok \pipe_middle_8_logical_op__oe__oe } { \pipe_middle_8_logical_op__rc__rc_ok \pipe_middle_8_logical_op__rc__rc } { \pipe_middle_8_logical_op__imm_data__imm_ok \pipe_middle_8_logical_op__imm_data__imm } \pipe_middle_8_logical_op__fn_unit \pipe_middle_8_logical_op__insn_type } { \pipe_middle_7_logical_op__insn$273 \pipe_middle_7_logical_op__data_len$272 \pipe_middle_7_logical_op__is_signed$271 \pipe_middle_7_logical_op__is_32bit$270 \pipe_middle_7_logical_op__output_carry$269 \pipe_middle_7_logical_op__write_cr0$268 \pipe_middle_7_logical_op__invert_out$267 \pipe_middle_7_logical_op__input_carry$266 \pipe_middle_7_logical_op__zero_a$265 \pipe_middle_7_logical_op__invert_in$264 { \pipe_middle_7_logical_op__oe__oe_ok$263 \pipe_middle_7_logical_op__oe__oe$262 } { \pipe_middle_7_logical_op__rc__rc_ok$261 \pipe_middle_7_logical_op__rc__rc$260 } { \pipe_middle_7_logical_op__imm_data__imm_ok$259 \pipe_middle_7_logical_op__imm_data__imm$258 } \pipe_middle_7_logical_op__fn_unit$257 \pipe_middle_7_logical_op__insn_type$256 } - sync init - end - process $group_301 - assign \pipe_middle_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_ra \pipe_middle_7_ra$274 - sync init - end - process $group_302 - assign \pipe_middle_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_rb \pipe_middle_7_rb$275 - sync init - end - process $group_303 - assign \pipe_middle_8_xer_so 1'0 - assign \pipe_middle_8_xer_so \pipe_middle_7_xer_so$276 - sync init - end - process $group_304 - assign \pipe_middle_8_divisor_neg 1'0 - assign \pipe_middle_8_divisor_neg \pipe_middle_7_divisor_neg$277 - sync init - end - process $group_305 - assign \pipe_middle_8_dividend_neg 1'0 - assign \pipe_middle_8_dividend_neg \pipe_middle_7_dividend_neg$278 - sync init - end - process $group_306 - assign \pipe_middle_8_dive_abs_ov32 1'0 - assign \pipe_middle_8_dive_abs_ov32 \pipe_middle_7_dive_abs_ov32$279 - sync init - end - process $group_307 - assign \pipe_middle_8_dive_abs_ov64 1'0 - assign \pipe_middle_8_dive_abs_ov64 \pipe_middle_7_dive_abs_ov64$280 - sync init - end - process $group_308 - assign \pipe_middle_8_div_by_zero 1'0 - assign \pipe_middle_8_div_by_zero \pipe_middle_7_div_by_zero$281 - sync init - end - process $group_309 - assign \pipe_middle_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_divisor_radicand \pipe_middle_7_divisor_radicand$282 - sync init - end - process $group_310 - assign \pipe_middle_8_operation 2'00 - assign \pipe_middle_8_operation \pipe_middle_7_operation$283 - sync init - end - process $group_311 - assign \pipe_middle_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_quotient_root \pipe_middle_7_quotient_root$284 - sync init - end - process $group_312 - assign \pipe_middle_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_root_times_radicand \pipe_middle_7_root_times_radicand$285 - sync init - end - process $group_313 - assign \pipe_middle_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_compare_lhs \pipe_middle_7_compare_lhs$286 - sync init - end - process $group_314 - assign \pipe_middle_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_8_compare_rhs \pipe_middle_7_compare_rhs$287 - sync init - end - process $group_315 - assign \pipe_middle_9_p_valid_i 1'0 - assign \pipe_middle_9_p_valid_i \pipe_middle_8_n_valid_o - sync init - end - process $group_316 - assign \pipe_middle_8_n_ready_i 1'0 - assign \pipe_middle_8_n_ready_i \pipe_middle_9_p_ready_o - sync init - end - process $group_317 - assign \pipe_middle_9_muxid 2'00 - assign \pipe_middle_9_muxid \pipe_middle_8_muxid$288 - sync init - end - process $group_318 - assign \pipe_middle_9_logical_op__insn_type 7'0000000 - assign \pipe_middle_9_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_9_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_9_logical_op__rc__rc 1'0 - assign \pipe_middle_9_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_9_logical_op__oe__oe 1'0 - assign \pipe_middle_9_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_9_logical_op__invert_in 1'0 - assign \pipe_middle_9_logical_op__zero_a 1'0 - assign \pipe_middle_9_logical_op__input_carry 2'00 - assign \pipe_middle_9_logical_op__invert_out 1'0 - assign \pipe_middle_9_logical_op__write_cr0 1'0 - assign \pipe_middle_9_logical_op__output_carry 1'0 - assign \pipe_middle_9_logical_op__is_32bit 1'0 - assign \pipe_middle_9_logical_op__is_signed 1'0 - assign \pipe_middle_9_logical_op__data_len 4'0000 - assign \pipe_middle_9_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_9_logical_op__insn \pipe_middle_9_logical_op__data_len \pipe_middle_9_logical_op__is_signed \pipe_middle_9_logical_op__is_32bit \pipe_middle_9_logical_op__output_carry \pipe_middle_9_logical_op__write_cr0 \pipe_middle_9_logical_op__invert_out \pipe_middle_9_logical_op__input_carry \pipe_middle_9_logical_op__zero_a \pipe_middle_9_logical_op__invert_in { \pipe_middle_9_logical_op__oe__oe_ok \pipe_middle_9_logical_op__oe__oe } { \pipe_middle_9_logical_op__rc__rc_ok \pipe_middle_9_logical_op__rc__rc } { \pipe_middle_9_logical_op__imm_data__imm_ok \pipe_middle_9_logical_op__imm_data__imm } \pipe_middle_9_logical_op__fn_unit \pipe_middle_9_logical_op__insn_type } { \pipe_middle_8_logical_op__insn$306 \pipe_middle_8_logical_op__data_len$305 \pipe_middle_8_logical_op__is_signed$304 \pipe_middle_8_logical_op__is_32bit$303 \pipe_middle_8_logical_op__output_carry$302 \pipe_middle_8_logical_op__write_cr0$301 \pipe_middle_8_logical_op__invert_out$300 \pipe_middle_8_logical_op__input_carry$299 \pipe_middle_8_logical_op__zero_a$298 \pipe_middle_8_logical_op__invert_in$297 { \pipe_middle_8_logical_op__oe__oe_ok$296 \pipe_middle_8_logical_op__oe__oe$295 } { \pipe_middle_8_logical_op__rc__rc_ok$294 \pipe_middle_8_logical_op__rc__rc$293 } { \pipe_middle_8_logical_op__imm_data__imm_ok$292 \pipe_middle_8_logical_op__imm_data__imm$291 } \pipe_middle_8_logical_op__fn_unit$290 \pipe_middle_8_logical_op__insn_type$289 } - sync init - end - process $group_336 - assign \pipe_middle_9_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_ra \pipe_middle_8_ra$307 - sync init - end - process $group_337 - assign \pipe_middle_9_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_rb \pipe_middle_8_rb$308 - sync init - end - process $group_338 - assign \pipe_middle_9_xer_so 1'0 - assign \pipe_middle_9_xer_so \pipe_middle_8_xer_so$309 - sync init - end - process $group_339 - assign \pipe_middle_9_divisor_neg 1'0 - assign \pipe_middle_9_divisor_neg \pipe_middle_8_divisor_neg$310 - sync init - end - process $group_340 - assign \pipe_middle_9_dividend_neg 1'0 - assign \pipe_middle_9_dividend_neg \pipe_middle_8_dividend_neg$311 - sync init - end - process $group_341 - assign \pipe_middle_9_dive_abs_ov32 1'0 - assign \pipe_middle_9_dive_abs_ov32 \pipe_middle_8_dive_abs_ov32$312 - sync init - end - process $group_342 - assign \pipe_middle_9_dive_abs_ov64 1'0 - assign \pipe_middle_9_dive_abs_ov64 \pipe_middle_8_dive_abs_ov64$313 - sync init - end - process $group_343 - assign \pipe_middle_9_div_by_zero 1'0 - assign \pipe_middle_9_div_by_zero \pipe_middle_8_div_by_zero$314 - sync init - end - process $group_344 - assign \pipe_middle_9_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_divisor_radicand \pipe_middle_8_divisor_radicand$315 - sync init - end - process $group_345 - assign \pipe_middle_9_operation 2'00 - assign \pipe_middle_9_operation \pipe_middle_8_operation$316 - sync init - end - process $group_346 - assign \pipe_middle_9_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_quotient_root \pipe_middle_8_quotient_root$317 - sync init - end - process $group_347 - assign \pipe_middle_9_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_root_times_radicand \pipe_middle_8_root_times_radicand$318 - sync init - end - process $group_348 - assign \pipe_middle_9_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_compare_lhs \pipe_middle_8_compare_lhs$319 - sync init - end - process $group_349 - assign \pipe_middle_9_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_9_compare_rhs \pipe_middle_8_compare_rhs$320 - sync init - end - process $group_350 - assign \pipe_middle_10_p_valid_i 1'0 - assign \pipe_middle_10_p_valid_i \pipe_middle_9_n_valid_o - sync init - end - process $group_351 - assign \pipe_middle_9_n_ready_i 1'0 - assign \pipe_middle_9_n_ready_i \pipe_middle_10_p_ready_o - sync init - end - process $group_352 - assign \pipe_middle_10_muxid 2'00 - assign \pipe_middle_10_muxid \pipe_middle_9_muxid$321 - sync init - end - process $group_353 - assign \pipe_middle_10_logical_op__insn_type 7'0000000 - assign \pipe_middle_10_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_10_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_10_logical_op__rc__rc 1'0 - assign \pipe_middle_10_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_10_logical_op__oe__oe 1'0 - assign \pipe_middle_10_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_10_logical_op__invert_in 1'0 - assign \pipe_middle_10_logical_op__zero_a 1'0 - assign \pipe_middle_10_logical_op__input_carry 2'00 - assign \pipe_middle_10_logical_op__invert_out 1'0 - assign \pipe_middle_10_logical_op__write_cr0 1'0 - assign \pipe_middle_10_logical_op__output_carry 1'0 - assign \pipe_middle_10_logical_op__is_32bit 1'0 - assign \pipe_middle_10_logical_op__is_signed 1'0 - assign \pipe_middle_10_logical_op__data_len 4'0000 - assign \pipe_middle_10_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_10_logical_op__insn \pipe_middle_10_logical_op__data_len \pipe_middle_10_logical_op__is_signed \pipe_middle_10_logical_op__is_32bit \pipe_middle_10_logical_op__output_carry \pipe_middle_10_logical_op__write_cr0 \pipe_middle_10_logical_op__invert_out \pipe_middle_10_logical_op__input_carry \pipe_middle_10_logical_op__zero_a \pipe_middle_10_logical_op__invert_in { \pipe_middle_10_logical_op__oe__oe_ok \pipe_middle_10_logical_op__oe__oe } { \pipe_middle_10_logical_op__rc__rc_ok \pipe_middle_10_logical_op__rc__rc } { \pipe_middle_10_logical_op__imm_data__imm_ok \pipe_middle_10_logical_op__imm_data__imm } \pipe_middle_10_logical_op__fn_unit \pipe_middle_10_logical_op__insn_type } { \pipe_middle_9_logical_op__insn$339 \pipe_middle_9_logical_op__data_len$338 \pipe_middle_9_logical_op__is_signed$337 \pipe_middle_9_logical_op__is_32bit$336 \pipe_middle_9_logical_op__output_carry$335 \pipe_middle_9_logical_op__write_cr0$334 \pipe_middle_9_logical_op__invert_out$333 \pipe_middle_9_logical_op__input_carry$332 \pipe_middle_9_logical_op__zero_a$331 \pipe_middle_9_logical_op__invert_in$330 { \pipe_middle_9_logical_op__oe__oe_ok$329 \pipe_middle_9_logical_op__oe__oe$328 } { \pipe_middle_9_logical_op__rc__rc_ok$327 \pipe_middle_9_logical_op__rc__rc$326 } { \pipe_middle_9_logical_op__imm_data__imm_ok$325 \pipe_middle_9_logical_op__imm_data__imm$324 } \pipe_middle_9_logical_op__fn_unit$323 \pipe_middle_9_logical_op__insn_type$322 } - sync init - end - process $group_371 - assign \pipe_middle_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_ra \pipe_middle_9_ra$340 - sync init - end - process $group_372 - assign \pipe_middle_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_rb \pipe_middle_9_rb$341 - sync init - end - process $group_373 - assign \pipe_middle_10_xer_so 1'0 - assign \pipe_middle_10_xer_so \pipe_middle_9_xer_so$342 - sync init - end - process $group_374 - assign \pipe_middle_10_divisor_neg 1'0 - assign \pipe_middle_10_divisor_neg \pipe_middle_9_divisor_neg$343 - sync init - end - process $group_375 - assign \pipe_middle_10_dividend_neg 1'0 - assign \pipe_middle_10_dividend_neg \pipe_middle_9_dividend_neg$344 - sync init - end - process $group_376 - assign \pipe_middle_10_dive_abs_ov32 1'0 - assign \pipe_middle_10_dive_abs_ov32 \pipe_middle_9_dive_abs_ov32$345 - sync init - end - process $group_377 - assign \pipe_middle_10_dive_abs_ov64 1'0 - assign \pipe_middle_10_dive_abs_ov64 \pipe_middle_9_dive_abs_ov64$346 - sync init - end - process $group_378 - assign \pipe_middle_10_div_by_zero 1'0 - assign \pipe_middle_10_div_by_zero \pipe_middle_9_div_by_zero$347 - sync init - end - process $group_379 - assign \pipe_middle_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_divisor_radicand \pipe_middle_9_divisor_radicand$348 - sync init - end - process $group_380 - assign \pipe_middle_10_operation 2'00 - assign \pipe_middle_10_operation \pipe_middle_9_operation$349 - sync init - end - process $group_381 - assign \pipe_middle_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_quotient_root \pipe_middle_9_quotient_root$350 - sync init - end - process $group_382 - assign \pipe_middle_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_root_times_radicand \pipe_middle_9_root_times_radicand$351 - sync init - end - process $group_383 - assign \pipe_middle_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_compare_lhs \pipe_middle_9_compare_lhs$352 - sync init - end - process $group_384 - assign \pipe_middle_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_10_compare_rhs \pipe_middle_9_compare_rhs$353 - sync init - end - process $group_385 - assign \pipe_middle_11_p_valid_i 1'0 - assign \pipe_middle_11_p_valid_i \pipe_middle_10_n_valid_o - sync init - end - process $group_386 - assign \pipe_middle_10_n_ready_i 1'0 - assign \pipe_middle_10_n_ready_i \pipe_middle_11_p_ready_o - sync init - end - process $group_387 - assign \pipe_middle_11_muxid 2'00 - assign \pipe_middle_11_muxid \pipe_middle_10_muxid$354 - sync init - end - process $group_388 - assign \pipe_middle_11_logical_op__insn_type 7'0000000 - assign \pipe_middle_11_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_11_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_11_logical_op__rc__rc 1'0 - assign \pipe_middle_11_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_11_logical_op__oe__oe 1'0 - assign \pipe_middle_11_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_11_logical_op__invert_in 1'0 - assign \pipe_middle_11_logical_op__zero_a 1'0 - assign \pipe_middle_11_logical_op__input_carry 2'00 - assign \pipe_middle_11_logical_op__invert_out 1'0 - assign \pipe_middle_11_logical_op__write_cr0 1'0 - assign \pipe_middle_11_logical_op__output_carry 1'0 - assign \pipe_middle_11_logical_op__is_32bit 1'0 - assign \pipe_middle_11_logical_op__is_signed 1'0 - assign \pipe_middle_11_logical_op__data_len 4'0000 - assign \pipe_middle_11_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_11_logical_op__insn \pipe_middle_11_logical_op__data_len \pipe_middle_11_logical_op__is_signed \pipe_middle_11_logical_op__is_32bit \pipe_middle_11_logical_op__output_carry \pipe_middle_11_logical_op__write_cr0 \pipe_middle_11_logical_op__invert_out \pipe_middle_11_logical_op__input_carry \pipe_middle_11_logical_op__zero_a \pipe_middle_11_logical_op__invert_in { \pipe_middle_11_logical_op__oe__oe_ok \pipe_middle_11_logical_op__oe__oe } { \pipe_middle_11_logical_op__rc__rc_ok \pipe_middle_11_logical_op__rc__rc } { \pipe_middle_11_logical_op__imm_data__imm_ok \pipe_middle_11_logical_op__imm_data__imm } \pipe_middle_11_logical_op__fn_unit \pipe_middle_11_logical_op__insn_type } { \pipe_middle_10_logical_op__insn$372 \pipe_middle_10_logical_op__data_len$371 \pipe_middle_10_logical_op__is_signed$370 \pipe_middle_10_logical_op__is_32bit$369 \pipe_middle_10_logical_op__output_carry$368 \pipe_middle_10_logical_op__write_cr0$367 \pipe_middle_10_logical_op__invert_out$366 \pipe_middle_10_logical_op__input_carry$365 \pipe_middle_10_logical_op__zero_a$364 \pipe_middle_10_logical_op__invert_in$363 { \pipe_middle_10_logical_op__oe__oe_ok$362 \pipe_middle_10_logical_op__oe__oe$361 } { \pipe_middle_10_logical_op__rc__rc_ok$360 \pipe_middle_10_logical_op__rc__rc$359 } { \pipe_middle_10_logical_op__imm_data__imm_ok$358 \pipe_middle_10_logical_op__imm_data__imm$357 } \pipe_middle_10_logical_op__fn_unit$356 \pipe_middle_10_logical_op__insn_type$355 } - sync init - end - process $group_406 - assign \pipe_middle_11_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_ra \pipe_middle_10_ra$373 - sync init - end - process $group_407 - assign \pipe_middle_11_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_rb \pipe_middle_10_rb$374 - sync init - end - process $group_408 - assign \pipe_middle_11_xer_so 1'0 - assign \pipe_middle_11_xer_so \pipe_middle_10_xer_so$375 - sync init - end - process $group_409 - assign \pipe_middle_11_divisor_neg 1'0 - assign \pipe_middle_11_divisor_neg \pipe_middle_10_divisor_neg$376 - sync init - end - process $group_410 - assign \pipe_middle_11_dividend_neg 1'0 - assign \pipe_middle_11_dividend_neg \pipe_middle_10_dividend_neg$377 - sync init - end - process $group_411 - assign \pipe_middle_11_dive_abs_ov32 1'0 - assign \pipe_middle_11_dive_abs_ov32 \pipe_middle_10_dive_abs_ov32$378 - sync init - end - process $group_412 - assign \pipe_middle_11_dive_abs_ov64 1'0 - assign \pipe_middle_11_dive_abs_ov64 \pipe_middle_10_dive_abs_ov64$379 - sync init - end - process $group_413 - assign \pipe_middle_11_div_by_zero 1'0 - assign \pipe_middle_11_div_by_zero \pipe_middle_10_div_by_zero$380 - sync init - end - process $group_414 - assign \pipe_middle_11_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_divisor_radicand \pipe_middle_10_divisor_radicand$381 - sync init - end - process $group_415 - assign \pipe_middle_11_operation 2'00 - assign \pipe_middle_11_operation \pipe_middle_10_operation$382 - sync init - end - process $group_416 - assign \pipe_middle_11_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_quotient_root \pipe_middle_10_quotient_root$383 - sync init - end - process $group_417 - assign \pipe_middle_11_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_root_times_radicand \pipe_middle_10_root_times_radicand$384 - sync init - end - process $group_418 - assign \pipe_middle_11_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_compare_lhs \pipe_middle_10_compare_lhs$385 - sync init - end - process $group_419 - assign \pipe_middle_11_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_11_compare_rhs \pipe_middle_10_compare_rhs$386 - sync init - end - process $group_420 - assign \pipe_middle_12_p_valid_i 1'0 - assign \pipe_middle_12_p_valid_i \pipe_middle_11_n_valid_o - sync init - end - process $group_421 - assign \pipe_middle_11_n_ready_i 1'0 - assign \pipe_middle_11_n_ready_i \pipe_middle_12_p_ready_o - sync init - end - process $group_422 - assign \pipe_middle_12_muxid 2'00 - assign \pipe_middle_12_muxid \pipe_middle_11_muxid$387 - sync init - end - process $group_423 - assign \pipe_middle_12_logical_op__insn_type 7'0000000 - assign \pipe_middle_12_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_12_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_12_logical_op__rc__rc 1'0 - assign \pipe_middle_12_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_12_logical_op__oe__oe 1'0 - assign \pipe_middle_12_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_12_logical_op__invert_in 1'0 - assign \pipe_middle_12_logical_op__zero_a 1'0 - assign \pipe_middle_12_logical_op__input_carry 2'00 - assign \pipe_middle_12_logical_op__invert_out 1'0 - assign \pipe_middle_12_logical_op__write_cr0 1'0 - assign \pipe_middle_12_logical_op__output_carry 1'0 - assign \pipe_middle_12_logical_op__is_32bit 1'0 - assign \pipe_middle_12_logical_op__is_signed 1'0 - assign \pipe_middle_12_logical_op__data_len 4'0000 - assign \pipe_middle_12_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_12_logical_op__insn \pipe_middle_12_logical_op__data_len \pipe_middle_12_logical_op__is_signed \pipe_middle_12_logical_op__is_32bit \pipe_middle_12_logical_op__output_carry \pipe_middle_12_logical_op__write_cr0 \pipe_middle_12_logical_op__invert_out \pipe_middle_12_logical_op__input_carry \pipe_middle_12_logical_op__zero_a \pipe_middle_12_logical_op__invert_in { \pipe_middle_12_logical_op__oe__oe_ok \pipe_middle_12_logical_op__oe__oe } { \pipe_middle_12_logical_op__rc__rc_ok \pipe_middle_12_logical_op__rc__rc } { \pipe_middle_12_logical_op__imm_data__imm_ok \pipe_middle_12_logical_op__imm_data__imm } \pipe_middle_12_logical_op__fn_unit \pipe_middle_12_logical_op__insn_type } { \pipe_middle_11_logical_op__insn$405 \pipe_middle_11_logical_op__data_len$404 \pipe_middle_11_logical_op__is_signed$403 \pipe_middle_11_logical_op__is_32bit$402 \pipe_middle_11_logical_op__output_carry$401 \pipe_middle_11_logical_op__write_cr0$400 \pipe_middle_11_logical_op__invert_out$399 \pipe_middle_11_logical_op__input_carry$398 \pipe_middle_11_logical_op__zero_a$397 \pipe_middle_11_logical_op__invert_in$396 { \pipe_middle_11_logical_op__oe__oe_ok$395 \pipe_middle_11_logical_op__oe__oe$394 } { \pipe_middle_11_logical_op__rc__rc_ok$393 \pipe_middle_11_logical_op__rc__rc$392 } { \pipe_middle_11_logical_op__imm_data__imm_ok$391 \pipe_middle_11_logical_op__imm_data__imm$390 } \pipe_middle_11_logical_op__fn_unit$389 \pipe_middle_11_logical_op__insn_type$388 } - sync init - end - process $group_441 - assign \pipe_middle_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_ra \pipe_middle_11_ra$406 - sync init - end - process $group_442 - assign \pipe_middle_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_rb \pipe_middle_11_rb$407 - sync init - end - process $group_443 - assign \pipe_middle_12_xer_so 1'0 - assign \pipe_middle_12_xer_so \pipe_middle_11_xer_so$408 - sync init - end - process $group_444 - assign \pipe_middle_12_divisor_neg 1'0 - assign \pipe_middle_12_divisor_neg \pipe_middle_11_divisor_neg$409 - sync init - end - process $group_445 - assign \pipe_middle_12_dividend_neg 1'0 - assign \pipe_middle_12_dividend_neg \pipe_middle_11_dividend_neg$410 - sync init - end - process $group_446 - assign \pipe_middle_12_dive_abs_ov32 1'0 - assign \pipe_middle_12_dive_abs_ov32 \pipe_middle_11_dive_abs_ov32$411 - sync init - end - process $group_447 - assign \pipe_middle_12_dive_abs_ov64 1'0 - assign \pipe_middle_12_dive_abs_ov64 \pipe_middle_11_dive_abs_ov64$412 + assign \pipe_middle_0_n_ready_i \pipe_end_p_ready_o sync init end - process $group_448 - assign \pipe_middle_12_div_by_zero 1'0 - assign \pipe_middle_12_div_by_zero \pipe_middle_11_div_by_zero$413 - sync init - end - process $group_449 - assign \pipe_middle_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_divisor_radicand \pipe_middle_11_divisor_radicand$414 - sync init - end - process $group_450 - assign \pipe_middle_12_operation 2'00 - assign \pipe_middle_12_operation \pipe_middle_11_operation$415 - sync init - end - process $group_451 - assign \pipe_middle_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_quotient_root \pipe_middle_11_quotient_root$416 - sync init - end - process $group_452 - assign \pipe_middle_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_root_times_radicand \pipe_middle_11_root_times_radicand$417 - sync init - end - process $group_453 - assign \pipe_middle_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_compare_lhs \pipe_middle_11_compare_lhs$418 - sync init - end - process $group_454 - assign \pipe_middle_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_12_compare_rhs \pipe_middle_11_compare_rhs$419 - sync init - end - process $group_455 - assign \pipe_middle_13_p_valid_i 1'0 - assign \pipe_middle_13_p_valid_i \pipe_middle_12_n_valid_o - sync init - end - process $group_456 - assign \pipe_middle_12_n_ready_i 1'0 - assign \pipe_middle_12_n_ready_i \pipe_middle_13_p_ready_o - sync init - end - process $group_457 - assign \pipe_middle_13_muxid 2'00 - assign \pipe_middle_13_muxid \pipe_middle_12_muxid$420 - sync init - end - process $group_458 - assign \pipe_middle_13_logical_op__insn_type 7'0000000 - assign \pipe_middle_13_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_13_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_13_logical_op__rc__rc 1'0 - assign \pipe_middle_13_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_13_logical_op__oe__oe 1'0 - assign \pipe_middle_13_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_13_logical_op__invert_in 1'0 - assign \pipe_middle_13_logical_op__zero_a 1'0 - assign \pipe_middle_13_logical_op__input_carry 2'00 - assign \pipe_middle_13_logical_op__invert_out 1'0 - assign \pipe_middle_13_logical_op__write_cr0 1'0 - assign \pipe_middle_13_logical_op__output_carry 1'0 - assign \pipe_middle_13_logical_op__is_32bit 1'0 - assign \pipe_middle_13_logical_op__is_signed 1'0 - assign \pipe_middle_13_logical_op__data_len 4'0000 - assign \pipe_middle_13_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_13_logical_op__insn \pipe_middle_13_logical_op__data_len \pipe_middle_13_logical_op__is_signed \pipe_middle_13_logical_op__is_32bit \pipe_middle_13_logical_op__output_carry \pipe_middle_13_logical_op__write_cr0 \pipe_middle_13_logical_op__invert_out \pipe_middle_13_logical_op__input_carry \pipe_middle_13_logical_op__zero_a \pipe_middle_13_logical_op__invert_in { \pipe_middle_13_logical_op__oe__oe_ok \pipe_middle_13_logical_op__oe__oe } { \pipe_middle_13_logical_op__rc__rc_ok \pipe_middle_13_logical_op__rc__rc } { \pipe_middle_13_logical_op__imm_data__imm_ok \pipe_middle_13_logical_op__imm_data__imm } \pipe_middle_13_logical_op__fn_unit \pipe_middle_13_logical_op__insn_type } { \pipe_middle_12_logical_op__insn$438 \pipe_middle_12_logical_op__data_len$437 \pipe_middle_12_logical_op__is_signed$436 \pipe_middle_12_logical_op__is_32bit$435 \pipe_middle_12_logical_op__output_carry$434 \pipe_middle_12_logical_op__write_cr0$433 \pipe_middle_12_logical_op__invert_out$432 \pipe_middle_12_logical_op__input_carry$431 \pipe_middle_12_logical_op__zero_a$430 \pipe_middle_12_logical_op__invert_in$429 { \pipe_middle_12_logical_op__oe__oe_ok$428 \pipe_middle_12_logical_op__oe__oe$427 } { \pipe_middle_12_logical_op__rc__rc_ok$426 \pipe_middle_12_logical_op__rc__rc$425 } { \pipe_middle_12_logical_op__imm_data__imm_ok$424 \pipe_middle_12_logical_op__imm_data__imm$423 } \pipe_middle_12_logical_op__fn_unit$422 \pipe_middle_12_logical_op__insn_type$421 } - sync init - end - process $group_476 - assign \pipe_middle_13_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_ra \pipe_middle_12_ra$439 - sync init - end - process $group_477 - assign \pipe_middle_13_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_rb \pipe_middle_12_rb$440 - sync init - end - process $group_478 - assign \pipe_middle_13_xer_so 1'0 - assign \pipe_middle_13_xer_so \pipe_middle_12_xer_so$441 - sync init - end - process $group_479 - assign \pipe_middle_13_divisor_neg 1'0 - assign \pipe_middle_13_divisor_neg \pipe_middle_12_divisor_neg$442 - sync init - end - process $group_480 - assign \pipe_middle_13_dividend_neg 1'0 - assign \pipe_middle_13_dividend_neg \pipe_middle_12_dividend_neg$443 - sync init - end - process $group_481 - assign \pipe_middle_13_dive_abs_ov32 1'0 - assign \pipe_middle_13_dive_abs_ov32 \pipe_middle_12_dive_abs_ov32$444 - sync init - end - process $group_482 - assign \pipe_middle_13_dive_abs_ov64 1'0 - assign \pipe_middle_13_dive_abs_ov64 \pipe_middle_12_dive_abs_ov64$445 - sync init - end - process $group_483 - assign \pipe_middle_13_div_by_zero 1'0 - assign \pipe_middle_13_div_by_zero \pipe_middle_12_div_by_zero$446 - sync init - end - process $group_484 - assign \pipe_middle_13_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_divisor_radicand \pipe_middle_12_divisor_radicand$447 - sync init - end - process $group_485 - assign \pipe_middle_13_operation 2'00 - assign \pipe_middle_13_operation \pipe_middle_12_operation$448 - sync init - end - process $group_486 - assign \pipe_middle_13_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_quotient_root \pipe_middle_12_quotient_root$449 - sync init - end - process $group_487 - assign \pipe_middle_13_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_root_times_radicand \pipe_middle_12_root_times_radicand$450 - sync init - end - process $group_488 - assign \pipe_middle_13_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_compare_lhs \pipe_middle_12_compare_lhs$451 - sync init - end - process $group_489 - assign \pipe_middle_13_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_13_compare_rhs \pipe_middle_12_compare_rhs$452 - sync init - end - process $group_490 - assign \pipe_middle_14_p_valid_i 1'0 - assign \pipe_middle_14_p_valid_i \pipe_middle_13_n_valid_o - sync init - end - process $group_491 - assign \pipe_middle_13_n_ready_i 1'0 - assign \pipe_middle_13_n_ready_i \pipe_middle_14_p_ready_o - sync init - end - process $group_492 - assign \pipe_middle_14_muxid 2'00 - assign \pipe_middle_14_muxid \pipe_middle_13_muxid$453 - sync init - end - process $group_493 - assign \pipe_middle_14_logical_op__insn_type 7'0000000 - assign \pipe_middle_14_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_14_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_14_logical_op__rc__rc 1'0 - assign \pipe_middle_14_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_14_logical_op__oe__oe 1'0 - assign \pipe_middle_14_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_14_logical_op__invert_in 1'0 - assign \pipe_middle_14_logical_op__zero_a 1'0 - assign \pipe_middle_14_logical_op__input_carry 2'00 - assign \pipe_middle_14_logical_op__invert_out 1'0 - assign \pipe_middle_14_logical_op__write_cr0 1'0 - assign \pipe_middle_14_logical_op__output_carry 1'0 - assign \pipe_middle_14_logical_op__is_32bit 1'0 - assign \pipe_middle_14_logical_op__is_signed 1'0 - assign \pipe_middle_14_logical_op__data_len 4'0000 - assign \pipe_middle_14_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_14_logical_op__insn \pipe_middle_14_logical_op__data_len \pipe_middle_14_logical_op__is_signed \pipe_middle_14_logical_op__is_32bit \pipe_middle_14_logical_op__output_carry \pipe_middle_14_logical_op__write_cr0 \pipe_middle_14_logical_op__invert_out \pipe_middle_14_logical_op__input_carry \pipe_middle_14_logical_op__zero_a \pipe_middle_14_logical_op__invert_in { \pipe_middle_14_logical_op__oe__oe_ok \pipe_middle_14_logical_op__oe__oe } { \pipe_middle_14_logical_op__rc__rc_ok \pipe_middle_14_logical_op__rc__rc } { \pipe_middle_14_logical_op__imm_data__imm_ok \pipe_middle_14_logical_op__imm_data__imm } \pipe_middle_14_logical_op__fn_unit \pipe_middle_14_logical_op__insn_type } { \pipe_middle_13_logical_op__insn$471 \pipe_middle_13_logical_op__data_len$470 \pipe_middle_13_logical_op__is_signed$469 \pipe_middle_13_logical_op__is_32bit$468 \pipe_middle_13_logical_op__output_carry$467 \pipe_middle_13_logical_op__write_cr0$466 \pipe_middle_13_logical_op__invert_out$465 \pipe_middle_13_logical_op__input_carry$464 \pipe_middle_13_logical_op__zero_a$463 \pipe_middle_13_logical_op__invert_in$462 { \pipe_middle_13_logical_op__oe__oe_ok$461 \pipe_middle_13_logical_op__oe__oe$460 } { \pipe_middle_13_logical_op__rc__rc_ok$459 \pipe_middle_13_logical_op__rc__rc$458 } { \pipe_middle_13_logical_op__imm_data__imm_ok$457 \pipe_middle_13_logical_op__imm_data__imm$456 } \pipe_middle_13_logical_op__fn_unit$455 \pipe_middle_13_logical_op__insn_type$454 } - sync init - end - process $group_511 - assign \pipe_middle_14_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_ra \pipe_middle_13_ra$472 - sync init - end - process $group_512 - assign \pipe_middle_14_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_rb \pipe_middle_13_rb$473 - sync init - end - process $group_513 - assign \pipe_middle_14_xer_so 1'0 - assign \pipe_middle_14_xer_so \pipe_middle_13_xer_so$474 - sync init - end - process $group_514 - assign \pipe_middle_14_divisor_neg 1'0 - assign \pipe_middle_14_divisor_neg \pipe_middle_13_divisor_neg$475 - sync init - end - process $group_515 - assign \pipe_middle_14_dividend_neg 1'0 - assign \pipe_middle_14_dividend_neg \pipe_middle_13_dividend_neg$476 - sync init - end - process $group_516 - assign \pipe_middle_14_dive_abs_ov32 1'0 - assign \pipe_middle_14_dive_abs_ov32 \pipe_middle_13_dive_abs_ov32$477 - sync init - end - process $group_517 - assign \pipe_middle_14_dive_abs_ov64 1'0 - assign \pipe_middle_14_dive_abs_ov64 \pipe_middle_13_dive_abs_ov64$478 - sync init - end - process $group_518 - assign \pipe_middle_14_div_by_zero 1'0 - assign \pipe_middle_14_div_by_zero \pipe_middle_13_div_by_zero$479 - sync init - end - process $group_519 - assign \pipe_middle_14_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_divisor_radicand \pipe_middle_13_divisor_radicand$480 - sync init - end - process $group_520 - assign \pipe_middle_14_operation 2'00 - assign \pipe_middle_14_operation \pipe_middle_13_operation$481 - sync init - end - process $group_521 - assign \pipe_middle_14_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_quotient_root \pipe_middle_13_quotient_root$482 - sync init - end - process $group_522 - assign \pipe_middle_14_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_root_times_radicand \pipe_middle_13_root_times_radicand$483 - sync init - end - process $group_523 - assign \pipe_middle_14_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_compare_lhs \pipe_middle_13_compare_lhs$484 - sync init - end - process $group_524 - assign \pipe_middle_14_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_14_compare_rhs \pipe_middle_13_compare_rhs$485 - sync init - end - process $group_525 - assign \pipe_middle_15_p_valid_i 1'0 - assign \pipe_middle_15_p_valid_i \pipe_middle_14_n_valid_o - sync init - end - process $group_526 - assign \pipe_middle_14_n_ready_i 1'0 - assign \pipe_middle_14_n_ready_i \pipe_middle_15_p_ready_o - sync init - end - process $group_527 - assign \pipe_middle_15_muxid 2'00 - assign \pipe_middle_15_muxid \pipe_middle_14_muxid$486 - sync init - end - process $group_528 - assign \pipe_middle_15_logical_op__insn_type 7'0000000 - assign \pipe_middle_15_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_15_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_15_logical_op__rc__rc 1'0 - assign \pipe_middle_15_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_15_logical_op__oe__oe 1'0 - assign \pipe_middle_15_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_15_logical_op__invert_in 1'0 - assign \pipe_middle_15_logical_op__zero_a 1'0 - assign \pipe_middle_15_logical_op__input_carry 2'00 - assign \pipe_middle_15_logical_op__invert_out 1'0 - assign \pipe_middle_15_logical_op__write_cr0 1'0 - assign \pipe_middle_15_logical_op__output_carry 1'0 - assign \pipe_middle_15_logical_op__is_32bit 1'0 - assign \pipe_middle_15_logical_op__is_signed 1'0 - assign \pipe_middle_15_logical_op__data_len 4'0000 - assign \pipe_middle_15_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_15_logical_op__insn \pipe_middle_15_logical_op__data_len \pipe_middle_15_logical_op__is_signed \pipe_middle_15_logical_op__is_32bit \pipe_middle_15_logical_op__output_carry \pipe_middle_15_logical_op__write_cr0 \pipe_middle_15_logical_op__invert_out \pipe_middle_15_logical_op__input_carry \pipe_middle_15_logical_op__zero_a \pipe_middle_15_logical_op__invert_in { \pipe_middle_15_logical_op__oe__oe_ok \pipe_middle_15_logical_op__oe__oe } { \pipe_middle_15_logical_op__rc__rc_ok \pipe_middle_15_logical_op__rc__rc } { \pipe_middle_15_logical_op__imm_data__imm_ok \pipe_middle_15_logical_op__imm_data__imm } \pipe_middle_15_logical_op__fn_unit \pipe_middle_15_logical_op__insn_type } { \pipe_middle_14_logical_op__insn$504 \pipe_middle_14_logical_op__data_len$503 \pipe_middle_14_logical_op__is_signed$502 \pipe_middle_14_logical_op__is_32bit$501 \pipe_middle_14_logical_op__output_carry$500 \pipe_middle_14_logical_op__write_cr0$499 \pipe_middle_14_logical_op__invert_out$498 \pipe_middle_14_logical_op__input_carry$497 \pipe_middle_14_logical_op__zero_a$496 \pipe_middle_14_logical_op__invert_in$495 { \pipe_middle_14_logical_op__oe__oe_ok$494 \pipe_middle_14_logical_op__oe__oe$493 } { \pipe_middle_14_logical_op__rc__rc_ok$492 \pipe_middle_14_logical_op__rc__rc$491 } { \pipe_middle_14_logical_op__imm_data__imm_ok$490 \pipe_middle_14_logical_op__imm_data__imm$489 } \pipe_middle_14_logical_op__fn_unit$488 \pipe_middle_14_logical_op__insn_type$487 } - sync init - end - process $group_546 - assign \pipe_middle_15_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_ra \pipe_middle_14_ra$505 - sync init - end - process $group_547 - assign \pipe_middle_15_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_rb \pipe_middle_14_rb$506 - sync init - end - process $group_548 - assign \pipe_middle_15_xer_so 1'0 - assign \pipe_middle_15_xer_so \pipe_middle_14_xer_so$507 - sync init - end - process $group_549 - assign \pipe_middle_15_divisor_neg 1'0 - assign \pipe_middle_15_divisor_neg \pipe_middle_14_divisor_neg$508 - sync init - end - process $group_550 - assign \pipe_middle_15_dividend_neg 1'0 - assign \pipe_middle_15_dividend_neg \pipe_middle_14_dividend_neg$509 - sync init - end - process $group_551 - assign \pipe_middle_15_dive_abs_ov32 1'0 - assign \pipe_middle_15_dive_abs_ov32 \pipe_middle_14_dive_abs_ov32$510 - sync init - end - process $group_552 - assign \pipe_middle_15_dive_abs_ov64 1'0 - assign \pipe_middle_15_dive_abs_ov64 \pipe_middle_14_dive_abs_ov64$511 - sync init - end - process $group_553 - assign \pipe_middle_15_div_by_zero 1'0 - assign \pipe_middle_15_div_by_zero \pipe_middle_14_div_by_zero$512 - sync init - end - process $group_554 - assign \pipe_middle_15_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_divisor_radicand \pipe_middle_14_divisor_radicand$513 - sync init - end - process $group_555 - assign \pipe_middle_15_operation 2'00 - assign \pipe_middle_15_operation \pipe_middle_14_operation$514 - sync init - end - process $group_556 - assign \pipe_middle_15_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_quotient_root \pipe_middle_14_quotient_root$515 - sync init - end - process $group_557 - assign \pipe_middle_15_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_root_times_radicand \pipe_middle_14_root_times_radicand$516 - sync init - end - process $group_558 - assign \pipe_middle_15_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_compare_lhs \pipe_middle_14_compare_lhs$517 - sync init - end - process $group_559 - assign \pipe_middle_15_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_15_compare_rhs \pipe_middle_14_compare_rhs$518 - sync init - end - process $group_560 - assign \pipe_end_p_valid_i 1'0 - assign \pipe_end_p_valid_i \pipe_middle_15_n_valid_o - sync init - end - process $group_561 - assign \pipe_middle_15_n_ready_i 1'0 - assign \pipe_middle_15_n_ready_i \pipe_end_p_ready_o - sync init - end - process $group_562 + process $group_34 assign \pipe_end_muxid 2'00 - assign \pipe_end_muxid \pipe_middle_15_muxid$519 + assign \pipe_end_muxid \pipe_middle_0_muxid$24 sync init end - process $group_563 + process $group_35 assign \pipe_end_logical_op__insn_type 7'0000000 assign \pipe_end_logical_op__fn_unit 11'00000000000 assign \pipe_end_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -179531,97 +54741,77 @@ module \alu_div0 assign \pipe_end_logical_op__is_signed 1'0 assign \pipe_end_logical_op__data_len 4'0000 assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_15_logical_op__insn$537 \pipe_middle_15_logical_op__data_len$536 \pipe_middle_15_logical_op__is_signed$535 \pipe_middle_15_logical_op__is_32bit$534 \pipe_middle_15_logical_op__output_carry$533 \pipe_middle_15_logical_op__write_cr0$532 \pipe_middle_15_logical_op__invert_out$531 \pipe_middle_15_logical_op__input_carry$530 \pipe_middle_15_logical_op__zero_a$529 \pipe_middle_15_logical_op__invert_in$528 { \pipe_middle_15_logical_op__oe__oe_ok$527 \pipe_middle_15_logical_op__oe__oe$526 } { \pipe_middle_15_logical_op__rc__rc_ok$525 \pipe_middle_15_logical_op__rc__rc$524 } { \pipe_middle_15_logical_op__imm_data__imm_ok$523 \pipe_middle_15_logical_op__imm_data__imm$522 } \pipe_middle_15_logical_op__fn_unit$521 \pipe_middle_15_logical_op__insn_type$520 } + assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } sync init end - process $group_581 + process $group_53 assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_ra \pipe_middle_15_ra$538 + assign \pipe_end_ra \pipe_middle_0_ra$43 sync init end - process $group_582 + process $group_54 assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_rb \pipe_middle_15_rb$539 + assign \pipe_end_rb \pipe_middle_0_rb$44 sync init end - process $group_583 + process $group_55 assign \pipe_end_xer_so 1'0 - assign \pipe_end_xer_so \pipe_middle_15_xer_so$540 + assign \pipe_end_xer_so \pipe_middle_0_xer_so$45 sync init end - process $group_584 + process $group_56 assign \pipe_end_divisor_neg 1'0 - assign \pipe_end_divisor_neg \pipe_middle_15_divisor_neg$541 + assign \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 sync init end - process $group_585 + process $group_57 assign \pipe_end_dividend_neg 1'0 - assign \pipe_end_dividend_neg \pipe_middle_15_dividend_neg$542 + assign \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 sync init end - process $group_586 + process $group_58 assign \pipe_end_dive_abs_ov32 1'0 - assign \pipe_end_dive_abs_ov32 \pipe_middle_15_dive_abs_ov32$543 + assign \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 sync init end - process $group_587 + process $group_59 assign \pipe_end_dive_abs_ov64 1'0 - assign \pipe_end_dive_abs_ov64 \pipe_middle_15_dive_abs_ov64$544 + assign \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 sync init end - process $group_588 + process $group_60 assign \pipe_end_div_by_zero 1'0 - assign \pipe_end_div_by_zero \pipe_middle_15_div_by_zero$545 - sync init - end - process $group_589 - assign \pipe_end_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_divisor_radicand \pipe_middle_15_divisor_radicand$546 - sync init - end - process $group_590 - assign \pipe_end_operation 2'00 - assign \pipe_end_operation \pipe_middle_15_operation$547 + assign \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 sync init end - process $group_591 + process $group_61 assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_quotient_root \pipe_middle_15_quotient_root$548 - sync init - end - process $group_592 - assign \pipe_end_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_root_times_radicand \pipe_middle_15_root_times_radicand$549 - sync init - end - process $group_593 - assign \pipe_end_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_compare_lhs \pipe_middle_15_compare_lhs$550 + assign \pipe_end_quotient_root \pipe_middle_0_quotient_root sync init end - process $group_594 - assign \pipe_end_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_compare_rhs \pipe_middle_15_compare_rhs$551 + process $group_62 + assign \pipe_end_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_remainder \pipe_middle_0_remainder sync init end - process $group_595 + process $group_63 assign \pipe_start_p_valid_i 1'0 assign \pipe_start_p_valid_i \p_valid_i sync init end - process $group_596 + process $group_64 assign \p_ready_o 1'0 assign \p_ready_o \pipe_start_p_ready_o sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid - process $group_597 + process $group_65 assign \pipe_start_muxid$2 2'00 assign \pipe_start_muxid$2 \muxid sync init end - process $group_598 + process $group_66 assign \pipe_start_logical_op__insn_type$3 7'0000000 assign \pipe_start_logical_op__fn_unit$4 11'00000000000 assign \pipe_start_logical_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -179643,36 +54833,36 @@ module \alu_div0 assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 { \pipe_start_logical_op__oe__oe_ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__rc_ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__imm_ok$6 \pipe_start_logical_op__imm_data__imm$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_616 + process $group_84 assign \pipe_start_ra$21 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_start_ra$21 \ra sync init end - process $group_617 + process $group_85 assign \pipe_start_rb$22 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_start_rb$22 \rb sync init end - process $group_618 + process $group_86 assign \pipe_start_xer_so$23 1'0 assign \pipe_start_xer_so$23 \xer_so$1 sync init end - process $group_619 + process $group_87 assign \n_valid_o 1'0 assign \n_valid_o \pipe_end_n_valid_o sync init end - process $group_620 + process $group_88 assign \pipe_end_n_ready_i 1'0 assign \pipe_end_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$572 - process $group_621 - assign \muxid$572 2'00 - assign \muxid$572 \pipe_end_muxid$552 + wire width 2 \muxid$71 + process $group_89 + assign \muxid$71 2'00 + assign \muxid$71 \pipe_end_muxid$51 sync init end attribute \enum_base_type "MicrOp" @@ -179749,7 +54939,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$573 + wire width 7 \logical_op__insn_type$72 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -179763,94 +54953,94 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$574 + wire width 11 \logical_op__fn_unit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$575 + wire width 64 \logical_op__imm_data__imm$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$576 + wire width 1 \logical_op__imm_data__imm_ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$577 + wire width 1 \logical_op__rc__rc$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$578 + wire width 1 \logical_op__rc__rc_ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$579 + wire width 1 \logical_op__oe__oe$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$580 + wire width 1 \logical_op__oe__oe_ok$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$581 + wire width 1 \logical_op__invert_in$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$582 + wire width 1 \logical_op__zero_a$81 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$583 + wire width 2 \logical_op__input_carry$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$584 + wire width 1 \logical_op__invert_out$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$585 + wire width 1 \logical_op__write_cr0$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$586 + wire width 1 \logical_op__output_carry$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$587 + wire width 1 \logical_op__is_32bit$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$588 + wire width 1 \logical_op__is_signed$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$589 + wire width 4 \logical_op__data_len$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$590 - process $group_622 - assign \logical_op__insn_type$573 7'0000000 - assign \logical_op__fn_unit$574 11'00000000000 - assign \logical_op__imm_data__imm$575 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$576 1'0 - assign \logical_op__rc__rc$577 1'0 - assign \logical_op__rc__rc_ok$578 1'0 - assign \logical_op__oe__oe$579 1'0 - assign \logical_op__oe__oe_ok$580 1'0 - assign \logical_op__invert_in$581 1'0 - assign \logical_op__zero_a$582 1'0 - assign \logical_op__input_carry$583 2'00 - assign \logical_op__invert_out$584 1'0 - assign \logical_op__write_cr0$585 1'0 - assign \logical_op__output_carry$586 1'0 - assign \logical_op__is_32bit$587 1'0 - assign \logical_op__is_signed$588 1'0 - assign \logical_op__data_len$589 4'0000 - assign \logical_op__insn$590 32'00000000000000000000000000000000 - assign { \logical_op__insn$590 \logical_op__data_len$589 \logical_op__is_signed$588 \logical_op__is_32bit$587 \logical_op__output_carry$586 \logical_op__write_cr0$585 \logical_op__invert_out$584 \logical_op__input_carry$583 \logical_op__zero_a$582 \logical_op__invert_in$581 { \logical_op__oe__oe_ok$580 \logical_op__oe__oe$579 } { \logical_op__rc__rc_ok$578 \logical_op__rc__rc$577 } { \logical_op__imm_data__imm_ok$576 \logical_op__imm_data__imm$575 } \logical_op__fn_unit$574 \logical_op__insn_type$573 } { \pipe_end_logical_op__insn$570 \pipe_end_logical_op__data_len$569 \pipe_end_logical_op__is_signed$568 \pipe_end_logical_op__is_32bit$567 \pipe_end_logical_op__output_carry$566 \pipe_end_logical_op__write_cr0$565 \pipe_end_logical_op__invert_out$564 \pipe_end_logical_op__input_carry$563 \pipe_end_logical_op__zero_a$562 \pipe_end_logical_op__invert_in$561 { \pipe_end_logical_op__oe__oe_ok$560 \pipe_end_logical_op__oe__oe$559 } { \pipe_end_logical_op__rc__rc_ok$558 \pipe_end_logical_op__rc__rc$557 } { \pipe_end_logical_op__imm_data__imm_ok$556 \pipe_end_logical_op__imm_data__imm$555 } \pipe_end_logical_op__fn_unit$554 \pipe_end_logical_op__insn_type$553 } + wire width 32 \logical_op__insn$89 + process $group_90 + assign \logical_op__insn_type$72 7'0000000 + assign \logical_op__fn_unit$73 11'00000000000 + assign \logical_op__imm_data__imm$74 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$75 1'0 + assign \logical_op__rc__rc$76 1'0 + assign \logical_op__rc__rc_ok$77 1'0 + assign \logical_op__oe__oe$78 1'0 + assign \logical_op__oe__oe_ok$79 1'0 + assign \logical_op__invert_in$80 1'0 + assign \logical_op__zero_a$81 1'0 + assign \logical_op__input_carry$82 2'00 + assign \logical_op__invert_out$83 1'0 + assign \logical_op__write_cr0$84 1'0 + assign \logical_op__output_carry$85 1'0 + assign \logical_op__is_32bit$86 1'0 + assign \logical_op__is_signed$87 1'0 + assign \logical_op__data_len$88 4'0000 + assign \logical_op__insn$89 32'00000000000000000000000000000000 + assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 { \logical_op__oe__oe_ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__rc_ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__imm_ok$75 \logical_op__imm_data__imm$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 { \pipe_end_logical_op__oe__oe_ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__rc_ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__imm_ok$55 \pipe_end_logical_op__imm_data__imm$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } sync init end - process $group_640 + process $group_108 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } sync init end - process $group_642 + process $group_110 assign \cr_a 4'0000 assign \cr_a_ok 1'0 assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } sync init end - process $group_644 + process $group_112 assign \xer_ov 2'00 assign \xer_ov_ok 1'0 assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } sync init end - process $group_646 + process $group_114 assign \xer_so 1'0 assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$571 } + assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } sync init end connect \muxid 2'00 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" -module \src_l$366 +module \src_l$81 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -179995,7 +55185,7 @@ module \src_l$366 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" -module \opc_l$367 +module \opc_l$82 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -180140,7 +55330,7 @@ module \opc_l$367 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" -module \req_l$368 +module \req_l$83 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -180285,7 +55475,7 @@ module \req_l$368 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" -module \rst_l$369 +module \rst_l$84 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -180430,7 +55620,7 @@ module \rst_l$369 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" -module \rok_l$370 +module \rok_l$85 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -180575,7 +55765,7 @@ module \rok_l$370 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" -module \alui_l$371 +module \alui_l$86 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -180720,7 +55910,7 @@ module \alui_l$371 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" -module \alu_l$372 +module \alu_l$87 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -181261,7 +56451,7 @@ module \div0 wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src - cell \src_l$366 \src_l + cell \src_l$81 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -181278,7 +56468,7 @@ module \div0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$367 \opc_l + cell \opc_l$82 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -181295,7 +56485,7 @@ module \div0 wire width 4 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \req_l_r_req$next - cell \req_l$368 \req_l + cell \req_l$83 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -181310,7 +56500,7 @@ module \div0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst$next - cell \rst_l$369 \rst_l + cell \rst_l$84 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -181326,7 +56516,7 @@ module \div0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$370 \rok_l + cell \rok_l$85 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -181341,7 +56531,7 @@ module \div0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$371 \alui_l + cell \alui_l$86 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -181356,7 +56546,7 @@ module \div0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$372 \alu_l + cell \alu_l$87 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -182822,7 +58012,7 @@ module \div0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" -module \p$373 +module \p$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -182850,7 +58040,7 @@ module \p$373 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" -module \n$374 +module \n$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -182878,7 +58068,7 @@ module \n$374 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" -module \p$375 +module \p$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -182906,7 +58096,7 @@ module \p$375 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" -module \n$376 +module \n$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -182934,7 +58124,7 @@ module \n$376 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" -module \input$377 +module \input$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -184038,11 +59228,11 @@ module \mul_pipe1 wire width 64 input 38 \rb$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 input 39 \xer_so$16 - cell \p$375 \p + cell \p$90 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$376 \n + cell \n$91 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -184280,7 +59470,7 @@ module \mul_pipe1 wire width 64 \input_rb$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 \input_xer_so$32 - cell \input$377 \input + cell \input$92 \input connect \muxid \input_muxid connect \mul_op__insn_type \input_mul_op__insn_type connect \mul_op__fn_unit \input_mul_op__fn_unit @@ -185054,7 +60244,7 @@ module \mul_pipe1 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" -module \p$378 +module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -185082,7 +60272,7 @@ module \p$378 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" -module \n$379 +module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -185705,11 +60895,11 @@ module \mul_pipe2 wire width 1 output 40 \neg_res32$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire width 1 \neg_res32$16$next - cell \p$378 \p + cell \p$93 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$379 \n + cell \n$94 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -186407,7 +61597,7 @@ module \mul_pipe2 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" -module \p$380 +module \p$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -186435,7 +61625,7 @@ module \p$380 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" -module \n$381 +module \n$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -186952,7 +62142,7 @@ module \mul3 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" -module \output$382 +module \output$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -187820,11 +63010,11 @@ module \mul_pipe3 wire width 1 output 43 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \xer_so_ok$next - cell \p$380 \p + cell \p$95 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$381 \n + cell \n$96 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -188350,7 +63540,7 @@ module \mul_pipe3 wire width 1 \output_xer_so$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \output_xer_so_ok - cell \output$382 \output + cell \output$97 \output connect \muxid \output_muxid connect \mul_op__insn_type \output_mul_op__insn_type connect \mul_op__fn_unit \output_mul_op__fn_unit @@ -189053,11 +64243,11 @@ module \alu_mul0 wire width 1 input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire width 1 output 28 \p_ready_o - cell \p$373 \p + cell \p$88 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$374 \n + cell \n$89 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -190265,7 +65455,7 @@ module \alu_mul0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" -module \src_l$383 +module \src_l$98 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -190410,7 +65600,7 @@ module \src_l$383 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" -module \opc_l$384 +module \opc_l$99 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -190555,7 +65745,7 @@ module \opc_l$384 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" -module \req_l$385 +module \req_l$100 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -190700,7 +65890,7 @@ module \req_l$385 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" -module \rst_l$386 +module \rst_l$101 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -190845,7 +66035,7 @@ module \rst_l$386 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" -module \rok_l$387 +module \rok_l$102 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -190990,7 +66180,7 @@ module \rok_l$387 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" -module \alui_l$388 +module \alui_l$103 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -191135,7 +66325,7 @@ module \alui_l$388 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" -module \alu_l$389 +module \alu_l$104 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -191626,7 +66816,7 @@ module \mul0 wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src - cell \src_l$383 \src_l + cell \src_l$98 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -191643,7 +66833,7 @@ module \mul0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$384 \opc_l + cell \opc_l$99 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -191660,7 +66850,7 @@ module \mul0 wire width 4 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \req_l_r_req$next - cell \req_l$385 \req_l + cell \req_l$100 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -191675,7 +66865,7 @@ module \mul0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst$next - cell \rst_l$386 \rst_l + cell \rst_l$101 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -191691,7 +66881,7 @@ module \mul0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$387 \rok_l + cell \rok_l$102 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -191706,7 +66896,7 @@ module \mul0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$388 \alui_l + cell \alui_l$103 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -191721,7 +66911,7 @@ module \mul0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$389 \alu_l + cell \alu_l$104 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -193125,7 +68315,7 @@ module \mul0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" -module \p$390 +module \p$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -193153,7 +68343,7 @@ module \p$390 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" -module \n$391 +module \n$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -193181,7 +68371,7 @@ module \n$391 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" -module \p$393 +module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -193209,7 +68399,7 @@ module \p$393 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" -module \n$394 +module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -193237,7 +68427,7 @@ module \n$394 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" -module \input$395 +module \input$110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -196803,7 +71993,7 @@ module \rotator end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" -module \main$396 +module \main$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -197275,7 +72465,7 @@ module \main$396 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" -module \pipe1$392 +module \pipe1$107 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -197594,11 +72784,11 @@ module \pipe1$392 wire width 64 input 48 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 49 \xer_ca$17 - cell \p$393 \p + cell \p$108 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$394 \n + cell \n$109 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -197860,7 +73050,7 @@ module \pipe1$392 wire width 64 \input_rc$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca$37 - cell \input$395 \input + cell \input$110 \input connect \muxid \input_muxid connect \sr_op__insn_type \input_sr_op__insn_type connect \sr_op__fn_unit \input_sr_op__fn_unit @@ -198156,7 +73346,7 @@ module \pipe1$392 wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 2 \main_xer_ca - cell \main$396 \main + cell \main$111 \main connect \muxid \main_muxid connect \sr_op__insn_type \main_sr_op__insn_type connect \sr_op__fn_unit \main_sr_op__fn_unit @@ -198704,7 +73894,7 @@ module \pipe1$392 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" -module \p$398 +module \p$113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -198732,7 +73922,7 @@ module \p$398 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" -module \n$399 +module \n$114 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -198760,7 +73950,7 @@ module \n$399 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" -module \output$400 +module \output$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -199280,7 +74470,7 @@ module \output$400 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" -module \pipe2$397 +module \pipe2$112 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -199603,11 +74793,11 @@ module \pipe2$397 wire width 1 output 51 \xer_ca_ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \xer_ca_ok$22$next - cell \p$398 \p + cell \p$113 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$399 \n + cell \n$114 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -199873,7 +75063,7 @@ module \pipe2$397 wire width 2 \output_xer_ca$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \output_xer_ca_ok - cell \output$400 \output + cell \output$115 \output connect \muxid \output_muxid connect \sr_op__insn_type \output_sr_op__insn_type connect \sr_op__fn_unit \output_sr_op__fn_unit @@ -200523,11 +75713,11 @@ module \alu_shift_rot0 wire width 1 input 30 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire width 1 output 31 \p_ready_o - cell \p$390 \p + cell \p$105 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$391 \n + cell \n$106 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -200801,7 +75991,7 @@ module \alu_shift_rot0 wire width 64 \pipe1_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$18 - cell \pipe1$392 \pipe1 + cell \pipe1$107 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \n_valid_o \pipe1_n_valid_o @@ -201125,7 +76315,7 @@ module \alu_shift_rot0 wire width 2 \pipe2_xer_ca$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe2_xer_ca_ok$40 - cell \pipe2$397 \pipe2 + cell \pipe2$112 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \p_valid_i \pipe2_p_valid_i @@ -201465,7 +76655,7 @@ module \alu_shift_rot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$401 +module \src_l$116 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -201610,7 +76800,7 @@ module \src_l$401 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$402 +module \opc_l$117 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -201755,7 +76945,7 @@ module \opc_l$402 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$403 +module \req_l$118 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -201900,7 +77090,7 @@ module \req_l$403 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$404 +module \rst_l$119 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -202045,7 +77235,7 @@ module \rst_l$404 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$405 +module \rok_l$120 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -202190,7 +77380,7 @@ module \rok_l$405 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$406 +module \alui_l$121 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -202335,7 +77525,7 @@ module \alui_l$406 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$407 +module \alu_l$122 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -202852,7 +78042,7 @@ module \shiftrot0 wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src - cell \src_l$401 \src_l + cell \src_l$116 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -202869,7 +78059,7 @@ module \shiftrot0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$402 \opc_l + cell \opc_l$117 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -202886,7 +78076,7 @@ module \shiftrot0 wire width 3 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req$next - cell \req_l$403 \req_l + cell \req_l$118 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -202901,7 +78091,7 @@ module \shiftrot0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst$next - cell \rst_l$404 \rst_l + cell \rst_l$119 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -202917,7 +78107,7 @@ module \shiftrot0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$405 \rok_l + cell \rok_l$120 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -202932,7 +78122,7 @@ module \shiftrot0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$406 \alui_l + cell \alui_l$121 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -202947,7 +78137,7 @@ module \shiftrot0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$407 \alu_l + cell \alu_l$122 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -204311,7 +79501,7 @@ module \shiftrot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$408 +module \opc_l$123 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -204456,7 +79646,7 @@ module \opc_l$408 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$409 +module \src_l$124 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -204601,7 +79791,7 @@ module \src_l$409 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$410 +module \alu_l$125 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -205471,7 +80661,7 @@ module \upd_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$411 +module \rst_l$126 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -205942,7 +81132,7 @@ module \ldst0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$408 \opc_l + cell \opc_l$123 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -205959,7 +81149,7 @@ module \ldst0 wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src - cell \src_l$409 \src_l + cell \src_l$124 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -205972,7 +81162,7 @@ module \ldst0 wire width 1 \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - cell \alu_l$410 \alu_l + cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_alu \alu_l_s_alu @@ -206060,7 +81250,7 @@ module \ldst0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rst_l_q_rst - cell \rst_l$411 \rst_l + cell \rst_l$126 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -212567,7 +87757,7 @@ module \idx_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$413 +module \reset_l$128 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -212714,7 +87904,7 @@ module \pick end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$412 +module \l0$127 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -212786,7 +87976,7 @@ module \l0$412 wire width 1 \reset_l_r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \reset_l_q_reset - cell \reset_l$413 \reset_l + cell \reset_l$128 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_reset \reset_l_s_reset @@ -214143,7 +89333,7 @@ module \l0 connect \m_valid_i \pimem_m_valid_i connect \x_valid_i \pimem_x_valid_i end - cell \l0$412 \l0 + cell \l0$127 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \ldst_port0_busy_o \ldst_port0_busy_o @@ -218689,7 +93879,7 @@ module \cr end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$414 +module \reg_0$129 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -219153,7 +94343,7 @@ module \reg_0$414 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$415 +module \reg_1$130 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -219617,7 +94807,7 @@ module \reg_1$415 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$416 +module \reg_2$131 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -220142,7 +95332,7 @@ module \xer wire width 2 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$414 \reg_0 + cell \reg_0$129 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \src10__ren \reg_0_src10__ren @@ -220194,7 +95384,7 @@ module \xer wire width 2 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$415 \reg_1 + cell \reg_1$130 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \src11__ren \reg_1_src11__ren @@ -220246,7 +95436,7 @@ module \xer wire width 2 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$416 \reg_2 + cell \reg_2$131 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \src12__ren \reg_2_src12__ren @@ -220747,7 +95937,7 @@ module \fast end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" -module \reg_0$417 +module \reg_0$132 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -220977,7 +96167,7 @@ module \reg_0$417 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" -module \reg_1$418 +module \reg_1$133 attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "simple/issuer.py:102" @@ -221252,7 +96442,7 @@ module \state wire width 1 \reg_0_d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$417 \reg_0 + cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cia0__ren \reg_0_cia0__ren @@ -221286,7 +96476,7 @@ module \state wire width 1 \reg_1_d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$418 \reg_1 + cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cia1__ren \reg_1_cia1__ren @@ -285200,7 +160390,7 @@ module \dec_c end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" -module \sprmap$419 +module \sprmap$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" wire width 10 input 0 \spr_i attribute \enum_base_type "SPR" @@ -285985,7 +161175,7 @@ module \dec_o attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" wire width 10 \sprmap_spr_o - cell \sprmap$419 \sprmap + cell \sprmap$134 \sprmap connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o end