From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 26 Sep 2015 08:45:13 +0000 (+0800)
Subject: wrap expressions in Specials
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa1e8cd822b02a5e669318c645ae64f5e672624b;p=litex.git

wrap expressions in Specials
---

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index 79a94ab3..ba2c911c 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -41,10 +41,10 @@ class Special(DUID):
 class Tristate(Special):
     def __init__(self, target, o, oe, i=None):
         Special.__init__(self)
-        self.target = target
-        self.o = o
-        self.oe = oe
-        self.i = i
+        self.target = wrap(target)
+        self.o = wrap(o)
+        self.oe = wrap(oe)
+        self.i = wrap(i)
 
     def iter_expressions(self):
         for attr, target_context in [
@@ -84,7 +84,7 @@ class Instance(Special):
             self.name = name
             if expr is None:
                 expr = Signal()
-            self.expr = expr
+            self.expr = wrap(expr)
     class Input(_IO):
         pass
     class Output(_IO):
@@ -94,6 +94,8 @@ class Instance(Special):
     class Parameter:
         def __init__(self, name, value):
             self.name = name
+            if isinstance(value, (int, bool)):
+                value = Constant(value)
             self.value = value
     class PreformattedParam(str):
         pass
@@ -143,7 +145,7 @@ class Instance(Special):
                     r += ",\n"
                 firstp = False
                 r += "\t." + p.name + "("
-                if isinstance(p.value, (int, bool)):
+                if isinstance(p.value, Constant):
                     r += verilog_printexpr(ns, p.value)[0]
                 elif isinstance(p.value, float):
                     r += str(p.value)
diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py
index 667ff3a5..c5342b7b 100644
--- a/migen/genlib/cdc.py
+++ b/migen/genlib/cdc.py
@@ -39,8 +39,8 @@ class MultiRegImpl(Module):
 class MultiReg(Special):
     def __init__(self, i, o, odomain="sys", n=2):
         Special.__init__(self)
-        self.i = i
-        self.o = o
+        self.i = wrap(i)
+        self.o = wrap(o)
         self.odomain = odomain
         self.n = n
 
diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index 12d8b0a1..fc930125 100644
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -6,9 +6,9 @@ from migen.fhdl.specials import Special
 class DifferentialInput(Special):
     def __init__(self, i_p, i_n, o):
         Special.__init__(self)
-        self.i_p = i_p
-        self.i_n = i_n
-        self.o = o
+        self.i_p = wrap(i_p)
+        self.i_n = wrap(i_n)
+        self.o = wrap(o)
 
     def iter_expressions(self):
         yield self, "i_p", SPECIAL_INPUT
@@ -23,9 +23,9 @@ class DifferentialInput(Special):
 class DifferentialOutput(Special):
     def __init__(self, i, o_p, o_n):
         Special.__init__(self)
-        self.i = i
-        self.o_p = o_p
-        self.o_n = o_n
+        self.i = wrap(i)
+        self.o_p = wrap(o_p)
+        self.o_n = wrap(o_n)
 
     def iter_expressions(self):
         yield self, "i", SPECIAL_INPUT
@@ -60,10 +60,10 @@ class CRG(Module):
 class DDRInput(Special):
     def __init__(self, i, o1, o2, clk=ClockSignal()):
         Special.__init__(self)
-        self.i = i
-        self.o1 = o1
-        self.o2 = o2
-        self.clk = clk
+        self.i = wrap(i)
+        self.o1 = wrap(o1)
+        self.o2 = wrap(o2)
+        self.clk = wrap(clk)
 
     def iter_expressions(self):
         yield self, "i", SPECIAL_INPUT
diff --git a/migen/genlib/resetsync.py b/migen/genlib/resetsync.py
index 3d46565c..db936900 100644
--- a/migen/genlib/resetsync.py
+++ b/migen/genlib/resetsync.py
@@ -6,7 +6,7 @@ class AsyncResetSynchronizer(Special):
     def __init__(self, cd, async_reset):
         Special.__init__(self)
         self.cd = cd
-        self.async_reset = async_reset
+        self.async_reset = wrap(async_reset)
 
     def iter_expressions(self):
         yield self.cd, "clk", SPECIAL_INPUT