From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 21 Mar 2013 18:02:04 +0000 (+0100)
Subject: dvisampler/clocking: generate pix reset
X-Git-Tag: 24jan2021_ls180~3014
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa2331e084ba72708ed4b823fed8571f5a09d9ad;p=litex.git

dvisampler/clocking: generate pix reset
---

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
index b20dfd9b..4d258aa7 100644
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@@ -66,18 +66,17 @@ class Clocking(Module, AutoReg):
 		self.specials += MultiReg(locked_async, self.locked, "sys")
 		self.comb += self._r_locked.field.w.eq(self.locked)
 
-		# sychronize pix5x reset
-		# this reset is also sampled in the sys clock domain, also guarantee
-		# a sufficient minimum pulse width.
-		pix5x_rst_n = 1
-		for i in range(5):
-			new_pix5x_rst_n = Signal()
+		# sychronize pix+pix5x reset
+		pix_rst_n = 1
+		for i in range(2):
+			new_pix_rst_n = Signal()
 			self.specials += Instance("FDCE",
-				Instance.Input("D", pix5x_rst_n),
+				Instance.Input("D", pix_rst_n),
 				Instance.Input("CE", 1),
-				Instance.Input("C", ClockSignal("pix5x")),
+				Instance.Input("C", ClockSignal("pix")),
 				Instance.Input("CLR", ~locked_async),
-				Instance.Output("Q", new_pix5x_rst_n)
+				Instance.Output("Q", new_pix_rst_n)
 			)
-			pix5x_rst_n = new_pix5x_rst_n
-		self.comb += self._cd_pix5x.rst.eq(~pix5x_rst_n)
+			pix_rst_n = new_pix_rst_n
+		self.comb += self._cd_pix.rst.eq(~pix_rst_n)
+		self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)