From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 13:12:36 +0000 (+0100)
Subject: move IRQLine out because that makes soc dependent on LambdaSOC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa2b56b63e3cbe1a7b68232e4c9e2a9980cc174e;p=soc.git

move IRQLine out because that makes soc dependent on LambdaSOC
---

diff --git a/src/soc/bus/opencores_ethmac.py b/src/soc/bus/opencores_ethmac.py
index 5720c1ce..cad49194 100644
--- a/src/soc/bus/opencores_ethmac.py
+++ b/src/soc/bus/opencores_ethmac.py
@@ -13,7 +13,6 @@ from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
 
 from nmigen_soc.wishbone.bus import Interface
 from nmigen_soc.memory import MemoryMap
-from lambdasoc.periph.event import IRQLine
 from nmigen.utils import log2_int
 from nmigen.cli import rtlil, verilog
 import os
@@ -55,7 +54,7 @@ class EthMAC(Elaboratable):
         self.master_bus = master_bus
         self.slave_bus = slave_bus
         if irq is None:
-            irq = IRQLine()
+            irq = Signal()
         self.irq = irq
 
         slave_mmap = MemoryMap(addr_width=12+self.dsize,
diff --git a/src/soc/bus/uart_16550.py b/src/soc/bus/uart_16550.py
index bceec5e2..1a900ee6 100644
--- a/src/soc/bus/uart_16550.py
+++ b/src/soc/bus/uart_16550.py
@@ -24,7 +24,7 @@ class UART16550(Elaboratable):
     """
 
     def __init__(self, bus=None, features=None, name=None, data_width=32,
-                       pins=None):
+                       pins=None, irq=None):
         if name is not None:
             # convention: give the name in the format "name_number"
             self.idx = int(name.split("_")[-1])
@@ -47,7 +47,9 @@ class UART16550(Elaboratable):
                         "bus width must be %d" % data_width
 
         # IRQ for data buffer receive/xmit
-        self.irq = Signal() 
+        if irq is None:
+            irq = Signal()
+        self.irq = irq
 
         # 9-pin UART signals (if anyone still remembers those...)
         self.tx_o = Signal() # transmit