From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 05:10:24 +0000 (-0700)
Subject: Fix broken test when ignoring abc9_flop with init == 1'b1
X-Git-Tag: working-ls180~549^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa31e84112c004348fae30e64ca224367b71d187;p=yosys.git

Fix broken test when ignoring abc9_flop with init == 1'b1
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 2794c913a..41a11e9a7 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -213,7 +213,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 							if (init != State::S0) {
 								log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
 								derived_module->set_bool_attribute(ID::abc9_flop, false);
-								goto skip_cell;
 							}
 							break;
 						}
@@ -250,8 +249,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
 
 			cell->type = derived_type;
 			cell->parameters.clear();
-
-skip_cell:		;
 		}
 }