From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 14 Oct 2016 16:34:44 +0000 (+0200)
Subject: Some minor build fixes for Visual C
X-Git-Tag: yosys-0.7~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa535c0b0041621d0128087cd0236cfd5eb36e48;p=yosys.git

Some minor build fixes for Visual C
---

diff --git a/kernel/driver.cc b/kernel/driver.cc
index 5cfc4171d..f8d00c38d 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -510,7 +510,9 @@ int main(int argc, char **argv)
 #endif
 
 	log_flush();
-#ifdef _WIN32
+#if defined(_MSC_VER)
+	_exit(0);
+#elif defined(_WIN32)
 	_Exit(0);
 #endif
 
diff --git a/kernel/log.cc b/kernel/log.cc
index 3f1d88819..abc401f55 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -207,6 +207,8 @@ void logv_error(const char *format, va_list ap)
 #ifdef EMSCRIPTEN
 	log_files = backup_log_files;
 	throw 0;
+#elif defined(_MSC_VER)
+	_exit(1);
 #else
 	_Exit(1);
 #endif
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 2934daadc..ecdc8621c 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -93,8 +93,17 @@ struct Clk2fflogicPass : public Pass {
 							log_signal(clk), log_signal(sig_d), log_signal(sig_q));
 					module->remove(cell);
 
-					SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk},
-							clkpol ? SigSpec({State::S0, State::S1}) : SigSpec({State::S1, State::S0}));
+					SigSpec clock_edge_pattern;
+
+					if (clkpol) {
+						clock_edge_pattern.append_bit(State::S0);
+						clock_edge_pattern.append_bit(State::S1);
+					} else {
+						clock_edge_pattern.append_bit(State::S1);
+						clock_edge_pattern.append_bit(State::S0);
+					}
+
+					SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk}, clock_edge_pattern);
 
 					Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
 					Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));