From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 May 2018 17:04:05 +0000 (+0100)
Subject: more slides
X-Git-Tag: convert-csv-opcode-to-binary~5361
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa57d65a2e2b5f88a68a2d6b1366445f76f39323;p=libreriscv.git

more slides
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 0abd3c444..817e317af 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -87,18 +87,17 @@
 \frametitle{ADD pseudocode (or trap, or actual hardware loop)}
 
 \begin{semiverbatim}
-function op_add(rd, rs1, rs2, predr) \{ # add not PADD!
+function op_add(rd, rs1, rs2, predr) # add not VADD!
   int i, id=0, irs1=0, irs2=0;
   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
     if (ireg[predr] & 1<<i) # predication uses intregs
-       ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-    # now increment idxs: src/dest all vec/scalar
+       ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
     if (reg_is_vectorised[rd]) \{ id += 1; \}
-    if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
-    if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
-\}
+    if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
+    if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
 \end{semiverbatim}
-   \begin{itemize}
+  \begin{itemize}
+   \item SIMD slightly more complex (case above is elwidth = default)  
    \item Scalar-scalar and scalar-vector and vector-vector now all in one
    \item OoO may choose to push ADDs into instr. queue (v. busy!)
   \end{itemize}