From: lkcl <lkcl@web>
Date: Sat, 23 May 2020 18:06:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2598
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa617be7012eda159a65cb78ae1a7e2ccbf8ab8f;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 8f5f04d69..86e69944b 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -83,6 +83,8 @@ Regspecs are defined, in python, as follows:
 | ----         | ----------           | ------------               |
 | INT          | ra                   | 0:3,5                      |
 
+Description of each heading:
+
 * Regfile name: INT corresponds to the INTEGER file, CR to Condition Register etc.
 * CompUnit Record name: in the Input or Output Record there will be a signal by
   name.  This field refers to that record signal, thus providing a sequential