From: cand@51b69dee28eeccfe0f04790433b843689895c6e3 <cand@web>
Date: Sat, 12 Dec 2020 17:15:44 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1383
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa72f11d2429308475a0e2ad12095b1f9e1b3d19;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 0bb8fc2e5..a5f9672ed 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -89,6 +89,9 @@ Some examples on different operation widths:
     u8 * u8 = u16
     255 * 2 = 510 # if we used the smaller width, we'd get 254. Wrong
 
+    u16 + u16 = u8
+    256 + 2 = 2 # this is correct whether we use the larger or smaller width - hw can optimize addition
+
 # Notes about rounding, clamp and saturate
 
 One of the issues with vector ops is that in integer DSP ops for example in Audio the operation must clamp or saturate rather than overflow or ignore the upper bits and become a modulo operation.  This for Audio is extremely important, also to provide an indicator as to whether saturation occurred.  see  [[av_opcodes]].