From: Anthony Green <green@moxielogic.com>
Date: Tue, 30 Dec 2014 23:58:44 +0000 (+0000)
Subject: Fix zero extension for moxie
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa7ac0a25eb3f5d87584a5703e0ffbabb615eefc;p=gcc.git

Fix zero extension for moxie

From-SVN: r219116
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2b89c49d275..60986f99a11 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-12-30  Anthony Green  <green@moxielogic.com>
+
+	* config/moxie/moxie.md (zero_extendqisi2, zero_extendhisi2):
+	Switch from define_insn_and_split to define_insn.  Fix instruction
+	length.
+
 2014-12-30  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.c (ix86_legitimize_address): Declare
diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md
index 32108ff41c8..fe98eaa34d7 100644
--- a/gcc/config/moxie/moxie.md
+++ b/gcc/config/moxie/moxie.md
@@ -268,7 +268,7 @@
    ldo.l  %0, %1"
   [(set_attr "length"	"2,2,6,2,6,2,6,4,4")])
 
-(define_insn_and_split "zero_extendqisi2"
+(define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,W,A,B")))]
   ""
@@ -277,15 +277,9 @@
    ld.b   %0, %1
    lda.b  %0, %1
    ldo.b  %0, %1"
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
-{
-  operands[2] = gen_lowpart (QImode, operands[0]);
-}
-  [(set_attr "length" "2,2,6,6")])
+  [(set_attr "length" "2,2,6,4")])
 
-(define_insn_and_split "zero_extendhisi2"
+(define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,W,A,B")))]
   ""
@@ -294,13 +288,7 @@
    ld.s   %0, %1
    lda.s  %0, %1
    ldo.s  %0, %1"
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
-{
-  operands[2] = gen_lowpart (HImode, operands[0]);
-}
-  [(set_attr "length" "2,2,6,6")])
+  [(set_attr "length" "2,2,6,4")])
 
 (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r")