From: Luke Kenneth Casson Leighton Date: Tue, 17 Apr 2018 18:31:34 +0000 (+0100) Subject: add hyperref X-Git-Tag: convert-csv-opcode-to-binary~5629 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa7b2818d89c4e0a263742f50a5d2efcb76c77fe;p=libreriscv.git add hyperref --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 98791b007..89d4e21e2 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -135,7 +135,7 @@ integer (and floating point) of various sizes is automatically inferred due to "type tagging" that is set with a special instruction. A register will be *specifically* marked as "16-bit Floating-Point" and, if added to an operand that is specifically tagged as "32-bit Integer" an implicit -type-conversion will take placce *without* requiring that type-conversion +type-conversion will take place *without* requiring that type-conversion to be explicitly done with its own separate instruction. However, implicit type-conversion is not only quite burdensome to @@ -935,7 +935,7 @@ This section has been moved to its own page [[p_comparative_analysis]]          irs2 += 1; } -## Retro-fitting Predication into branch-explicit ISA +## Retro-fitting Predication into branch-explicit ISA One of the goals of this parallelism proposal is to avoid instruction duplication. However, with the base ISA having been designed explictly