From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700)
Subject: split out instructions from openpower/isa/fixedarith.mdwn
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa8297f7f781f343f9722fac1dd6db9372548ffb;p=openpower-isa.git

split out instructions from openpower/isa/fixedarith.mdwn
---

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 4044ded9..bf824530 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -2,818 +2,84 @@
 
 <!-- Section 3.3.9 Fixed-point arithmetic instructions. Pages 67 - 83 -->
 
-# Add Immediate
+[[!inline pagenames="openpower/isa/fixedarith/addi" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedarith/addis" raw="yes"]]
 
-* addi RT,RA,SI
+[[!inline pagenames="openpower/isa/fixedarith/addpcis" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/add" raw="yes"]]
 
-    RT <- (RA|0) + EXTS(SI)
+[[!inline pagenames="openpower/isa/fixedarith/subf" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedarith/addic" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedarith/addic." raw="yes"]]
 
-# Add Immediate Shifted
+[[!inline pagenames="openpower/isa/fixedarith/subfic" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedarith/addc" raw="yes"]]
 
-* addis RT,RA,SI
+[[!inline pagenames="openpower/isa/fixedarith/subfc" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/adde" raw="yes"]]
 
-    RT <- (RA|0) + EXTS(SI || [0]*16)
+[[!inline pagenames="openpower/isa/fixedarith/subfe" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedarith/addme" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedarith/subfme" raw="yes"]]
 
-# Add PC Immediate Shifted
+[[!inline pagenames="openpower/isa/fixedarith/addex" raw="yes"]]
 
-DX-Form
+[[!inline pagenames="openpower/isa/fixedarith/subfze" raw="yes"]]
 
-* addpcis RT,D
+[[!inline pagenames="openpower/isa/fixedarith/addze" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/neg" raw="yes"]]
 
-    D <- d0||d1||d2
-    RT <- NIA + EXTS(D || [0]*16)
+[[!inline pagenames="openpower/isa/fixedarith/mulli" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedarith/mulhw" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedarith/mullw" raw="yes"]]
 
-# Add
+[[!inline pagenames="openpower/isa/fixedarith/mulhwu" raw="yes"]]
 
-XO-Form
+[[!inline pagenames="openpower/isa/fixedarith/divw" raw="yes"]]
 
-* add RT,RA,RB (OE=0 Rc=0)
-* add.  RT,RA,RB (OE=0 Rc=1)
-* addo RT,RA,RB (OE=1 Rc=0)
-* addo.  RT,RA,RB (OE=1 Rc=1)
+[[!inline pagenames="openpower/isa/fixedarith/divwu" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/divwe" raw="yes"]]
 
-    RT <- (RA) + (RB)
+[[!inline pagenames="openpower/isa/fixedarith/divweu" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedarith/modsw" raw="yes"]]
 
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
+[[!inline pagenames="openpower/isa/fixedarith/moduw" raw="yes"]]
 
-# Subtract From
+[[!inline pagenames="openpower/isa/fixedarith/darn" raw="yes"]]
 
-XO-Form
+[[!inline pagenames="openpower/isa/fixedarith/mulld" raw="yes"]]
 
-* subf RT,RA,RB (OE=0 Rc=0)
-* subf.  RT,RA,RB (OE=0 Rc=1)
-* subfo RT,RA,RB (OE=1 Rc=0)
-* subfo.  RT,RA,RB (OE=1 Rc=1)
+[[!inline pagenames="openpower/isa/fixedarith/mulhd" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/mulhdu" raw="yes"]]
 
-    RT <- ¬(RA) + (RB) + 1
+[[!inline pagenames="openpower/isa/fixedarith/maddhd" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedarith/maddhdu" raw="yes"]]
 
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
+[[!inline pagenames="openpower/isa/fixedarith/maddld" raw="yes"]]
 
-# Add Immediate Carrying
+[[!inline pagenames="openpower/isa/fixedarith/divd" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedarith/divdu" raw="yes"]]
 
-* addic RT,RA,SI
+[[!inline pagenames="openpower/isa/fixedarith/divde" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedarith/divdeu" raw="yes"]]
 
-    RT <- (RA) + EXTS(SI)
+[[!inline pagenames="openpower/isa/fixedarith/modsd" raw="yes"]]
 
-Special Registers Altered:
-
-    CA CA32
-
-# Add Immediate Carrying and Record
-
-D-Form
-
-* addic. RT,RA,SI
-
-Pseudo-code:
-
-    RT <- (RA) + EXTS(SI)
-
-Special Registers Altered:
-
-    CR0 CA CA32
-
-# Subtract From Immediate Carrying
-
-D-Form
-
-* subfic RT,RA,SI
-
-Pseudo-code:
-
-    RT <- ¬(RA) + EXTS(SI) + 1
-
-Special Registers Altered:
-
-    CA CA32
-
-# Add Carrying
-
-XO-Form
-
-* addc RT,RA,RB (OE=0 Rc=0)
-* addc.  RT,RA,RB (OE=0 Rc=1)
-* addco RT,RA,RB (OE=1 Rc=0)
-* addco.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- (RA) + (RB)
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Subtract From Carrying
-
-XO-Form
-
-* subfc RT,RA,RB (OE=0 Rc=0)
-* subfc.  RT,RA,RB (OE=0 Rc=1)
-* subfco RT,RA,RB (OE=1 Rc=0)
-* subfco.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- ¬(RA) + (RB) + 1
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Add Extended
-
-XO-Form
-
-* adde RT,RA,RB (OE=0 Rc=0)
-* adde.  RT,RA,RB (OE=0 Rc=1)
-* addeo RT,RA,RB (OE=1 Rc=0)
-* addeo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- (RA) + (RB) + CA
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Subtract From Extended
-
-XO-Form
-
-* subfe RT,RA,RB (OE=0 Rc=0)
-* subfe.  RT,RA,RB (OE=0 Rc=1)
-* subfeo RT,RA,RB (OE=1 Rc=0)
-* subfeo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- ¬(RA) + (RB) + CA
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Add to Minus One Extended
-
-XO-Form
-
-* addme RT,RA (OE=0 Rc=0)
-* addme.  RT,RA (OE=0 Rc=1)
-* addmeo RT,RA (OE=1 Rc=0)
-* addmeo.  RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- (RA) + CA - 1
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Subtract From Minus One Extended
-
-XO-Form
-
-* subfme RT,RA (OE=0 Rc=0)
-* subfme.  RT,RA (OE=0 Rc=1)
-* subfmeo RT,RA (OE=1 Rc=0)
-* subfmeo.  RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- ¬(RA) + CA - 1
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Add Extended using alternate carry bit
-
-Z23-Form
-
-* addex RT,RA,RB,CY
-
-Pseudo-code:
-
-    if CY=0 then RT <- (RA) + (RB) + OV
-
-Special Registers Altered:
-
-    OV OV32                (if CY=0 )
-
-# Subtract From Zero Extended
-
-XO-Form
-
-* subfze RT,RA (OE=0 Rc=0)
-* subfze.  RT,RA (OE=0 Rc=1)
-* subfzeo RT,RA (OE=1 Rc=0)
-* subfzeo.  RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- ¬(RA) + CA
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Add to Zero Extended
-
-XO-Form
-
-* addze RT,RA (OE=0 Rc=0)
-* addze.  RT,RA (OE=0 Rc=1)
-* addzeo RT,RA (OE=1 Rc=0)
-* addzeo.  RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- (RA) + CA
-
-Special Registers Altered:
-
-    CA CA32
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Negate
-
-XO-Form
-
-* neg RT,RA (OE=0 Rc=0)
-* neg.  RT,RA (OE=0 Rc=1)
-* nego RT,RA (OE=1 Rc=0)
-* nego.  RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
-    RT <- ¬(RA) + 1
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Multiply Low Immediate
-
-D-Form
-
-* mulli RT,RA,SI
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), EXTS(SI))
-    RT <- prod[XLEN:(XLEN*2)-1]
-
-Special Registers Altered:
-
-    None
-
-# Multiply High Word
-
-XO-Form
-
-* mulhw RT,RA,RB (Rc=0)
-* mulhw.  RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
-    RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
-    RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-
-# Multiply Low Word
-
-XO-Form
-
-* mullw RT,RA,RB (OE=0 Rc=0)
-* mullw.  RT,RA,RB (OE=0 Rc=1)
-* mullwo RT,RA,RB (OE=1 Rc=0)
-* mullwo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
-    RT <- prod
-    overflow <- ((prod[0:XLEN/2] != [0]*((XLEN/2)+1)) &
-                 (prod[0:XLEN/2] != [1]*((XLEN/2)+1)))
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Multiply High Word Unsigned
-
-XO-Form
-
-* mulhwu RT,RA,RB (Rc=0)
-* mulhwu.  RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    prod[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] * (RB)[XLEN/2:XLEN-1]
-    RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
-    RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-
-# Divide Word
-
-XO-Form
-
-* divw RT,RA,RB (OE=0 Rc=0)
-* divw.  RT,RA,RB (OE=0 Rc=1)
-* divwo RT,RA,RB (OE=1 Rc=0)
-* divwo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
-    divisor[0:(XLEN/2)-1] <- (RB) [XLEN/2:XLEN-1]
-    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
-         (divisor = [1]*(XLEN/2))) |
-         (divisor = [0]*(XLEN/2))) then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT[XLEN/2:XLEN-1] <- DIVS(dividend, divisor)
-        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
-        overflow <- 0
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-    SO OV OV32                              (if OE=1)
-
-# Divide Word Unsigned
-
-XO-Form
-
-* divwu RT,RA,RB (OE=0 Rc=0)
-* divwu.  RT,RA,RB (OE=0 Rc=1)
-* divwuo RT,RA,RB (OE=1 Rc=0)
-* divwuo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
-    divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
-    if divisor != 0 then
-        RT[XLEN/2:XLEN-1] <- dividend / divisor
-        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
-        overflow <- 0
-    else
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-    SO OV OV32                              (if OE=1)
-
-# Divide Word Extended
-
-XO-Form
-
-* divwe RT,RA,RB (OE=0 Rc=0)
-* divwe.  RT,RA,RB (OE=0 Rc=1)
-* divweo RT,RA,RB (OE=1 Rc=0)
-* divweo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
-    divisor[0:XLEN-1] <- EXTS64((RB)[XLEN/2:XLEN-1])
-    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
-         (divisor = [1]*XLEN)) |
-         (divisor = [0]*XLEN)) then
-        overflow <- 1
-    else
-        result <- DIVS(dividend, divisor)
-        result_half[0:XLEN-1] <- EXTS64(result[XLEN/2:XLEN-1])
-        if (result_half = result) then
-            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
-            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
-            overflow <- 0
-        else
-            overflow <- 1
-    if overflow = 1 then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-    SO OV OV32                              (if OE=1)
-
-# Divide Word Extended Unsigned
-
-XO-Form
-
-* divweu RT,RA,RB (OE=0 Rc=0)
-* divweu.  RT,RA,RB (OE=0 Rc=1)
-* divweuo RT,RA,RB (OE=1 Rc=0)
-* divweuo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
-    divisor[0:XLEN-1] <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1]
-    if (divisor = [0]*XLEN) then
-        overflow <- 1
-    else
-        result <- dividend / divisor
-        if RA[XLEN/2:XLEN-1] <u RB[XLEN/2:XLEN-1] then
-            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
-            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
-            overflow <- 0
-        else
-            overflow <- 1
-    if overflow = 1 then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-
-Special Registers Altered:
-
-    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-    SO OV OV32                              (if OE=1)
-
-# Modulo Signed Word
-
-X-Form
-
-* modsw RT,RA,RB
-
-Pseudo-code:
-
-    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
-    divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
-    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
-         (divisor = [1]*(XLEN/2))) |
-         (divisor = [0]*(XLEN/2))) then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT[0:XLEN-1] <- EXTS64(MODS(dividend, divisor))
-        RT[0:(XLEN/2)-1] <- undefined(RT[0:(XLEN/2)-1])
-        overflow <- 0
-
-Special Registers Altered:
-
-    None
-
-# Modulo Unsigned Word
-
-X-Form
-
-* moduw RT,RA,RB
-
-Pseudo-code:
-
-    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:63]
-    divisor [0:(XLEN/2)-1] <- (RB)[XLEN/2:63]
-    if divisor = [0]*(XLEN/2) then
-        RT[0:XLEN-1] <- undefined([0]*64)
-        overflow <- 1
-    else
-        RT[XLEN/2:XLEN-1] <- dividend % divisor
-        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
-        overflow <- 0
-
-Special Registers Altered:
-
-    None
-
-# Deliver A Random Number
-
-X-Form
-
-* darn RT,L3
-
-Pseudo-code:
-
-    RT <- random(L3)
-
-Special Registers Altered:
-
-    none
-
-# Multiply Low Doubleword
-
-XO-Form
-
-* mulld RT,RA,RB (OE=0 Rc=0)
-* mulld.  RT,RA,RB (OE=0 Rc=1)
-* mulldo RT,RA,RB (OE=1 Rc=0)
-* mulldo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
-    RT <- prod[XLEN:(XLEN*2)-1]
-    overflow <- ((prod[0:XLEN] != [0]*(XLEN+1)) &
-                 (prod[0:XLEN] != [1]*(XLEN+1)))
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Multiply High Doubleword
-
-XO-Form
-
-* mulhd RT,RA,RB (Rc=0)
-* mulhd.  RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
-    RT <- prod[0:XLEN-1]
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# Multiply High Doubleword Unsigned
-
-XO-Form
-
-* mulhdu RT,RA,RB (Rc=0)
-* mulhdu.  RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- (RA) * (RB)
-    RT <- prod[0:XLEN-1]
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# Multiply-Add High Doubleword VA-Form
-
-VA-Form
-
-* maddhd RT,RA,RB,RC
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
-    sum[0:(XLEN*2)-1] <- prod + EXTS(RC)[0:XLEN*2]
-    RT <- sum[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Multiply-Add High Doubleword Unsigned
-
-VA-Form
-
-* maddhdu RT,RA,RB,RC
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- (RA) * (RB)
-    sum[0:(XLEN*2)-1] <- prod + EXTZ(RC)
-    RT <- sum[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# Multiply-Add Low Doubleword
-
-VA-Form
-
-* maddld RT,RA,RB,RC
-
-Pseudo-code:
-
-    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
-    sum[0:(XLEN*2)-1] <- prod + EXTS(RC)
-    RT <- sum[XLEN:(XLEN*2)-1]
-
-Special Registers Altered:
-
-    None
-
-# Divide Doubleword
-
-XO-Form
-
-* divd RT,RA,RB (OE=0 Rc=0)
-* divd.  RT,RA,RB (OE=0 Rc=1)
-* divdo RT,RA,RB (OE=1 Rc=0)
-* divdo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:XLEN-1] <- (RA)
-    divisor[0:XLEN-1] <- (RB)
-    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
-         (divisor = [1]*XLEN)) |
-         (divisor = [0]*XLEN)) then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT <- DIVS(dividend, divisor)
-        overflow <- 0
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Divide Doubleword Unsigned
-
-XO-Form
-
-* divdu RT,RA,RB (OE=0 Rc=0)
-* divdu.  RT,RA,RB (OE=0 Rc=1)
-* divduo RT,RA,RB (OE=1 Rc=0)
-* divduo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:XLEN-1] <- (RA)
-    divisor[0:XLEN-1] <- (RB)
-    if (divisor = [0]*XLEN) then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT <- dividend / divisor
-        overflow <- 0
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Divide Doubleword Extended
-
-XO-Form
-
-* divde RT,RA,RB (OE=0 Rc=0)
-* divde.  RT,RA,RB (OE=0 Rc=1)
-* divdeo RT,RA,RB (OE=1 Rc=0)
-* divdeo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
-    divisor[0:(XLEN*2)-1] <- EXTS128((RB))
-    if (((dividend = (0b1 || ([0b0] * ((XLEN*2)-1)))) &
-         (divisor = [1]*(XLEN*2))) |
-         (divisor = [0]*(XLEN*2))) then
-        overflow <- 1
-    else
-        result <- DIVS(dividend, divisor)
-        result_half[0:(XLEN*2)-1] <- EXTS128(result[XLEN:(XLEN*2)-1])
-        if (result_half = result) then
-            RT <- result[XLEN:(XLEN*2)-1]
-            overflow <- 0
-        else
-            overflow <- 1
-    if overflow = 1 then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Divide Doubleword Extended Unsigned
-
-XO-Form
-
-* divdeu RT,RA,RB (OE=0 Rc=0)
-* divdeu.  RT,RA,RB (OE=0 Rc=1)
-* divdeuo RT,RA,RB (OE=1 Rc=0)
-* divdeuo.  RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
-    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
-    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
-    if divisor = [0]*(XLEN*2) then
-        overflow <- 1
-    else
-        result <- dividend / divisor
-        if (RA) <u (RB) then
-            RT <- result[XLEN:(XLEN*2)-1]
-            overflow <- 0
-        else
-            overflow <- 1
-    if overflow = 1 then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-    SO OV OV32             (if OE=1)
-
-# Modulo Signed Doubleword
-
-X-Form
-
-* modsd RT,RA,RB
-
-Pseudo-code:
-
-    dividend <- (RA)
-    divisor <- (RB)
-    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
-         (divisor = [1]*XLEN)) |
-         (divisor = [0]*XLEN)) then
-        RT[0:63] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT <- MODS(dividend, divisor)
-        overflow <- 0
-
-Special Registers Altered:
-
-    None
-
-# Modulo Unsigned Doubleword
-
-X-Form
-
-* modud RT,RA,RB
-
-Pseudo-code:
-
-    dividend <- (RA)
-    divisor <- (RB)
-    if (divisor = [0]*XLEN) then
-        RT[0:XLEN-1] <- undefined([0]*XLEN)
-        overflow <- 1
-    else
-        RT <- dividend % divisor
-        overflow <- 0
-
-Special Registers Altered:
-
-    None
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/fixedarith/modud" raw="yes"]]
diff --git a/openpower/isa/fixedarith/add.mdwn b/openpower/isa/fixedarith/add.mdwn
new file mode 100644
index 00000000..d35fca2e
--- /dev/null
+++ b/openpower/isa/fixedarith/add.mdwn
@@ -0,0 +1,17 @@
+# Add
+
+XO-Form
+
+* add RT,RA,RB (OE=0 Rc=0)
+* add.  RT,RA,RB (OE=0 Rc=1)
+* addo RT,RA,RB (OE=1 Rc=0)
+* addo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/add_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/add_code.mdwn b/openpower/isa/fixedarith/add_code.mdwn
new file mode 100644
index 00000000..056a1532
--- /dev/null
+++ b/openpower/isa/fixedarith/add_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + (RB)
diff --git a/openpower/isa/fixedarith/addc.mdwn b/openpower/isa/fixedarith/addc.mdwn
new file mode 100644
index 00000000..359e844c
--- /dev/null
+++ b/openpower/isa/fixedarith/addc.mdwn
@@ -0,0 +1,18 @@
+# Add Carrying
+
+XO-Form
+
+* addc RT,RA,RB (OE=0 Rc=0)
+* addc.  RT,RA,RB (OE=0 Rc=1)
+* addco RT,RA,RB (OE=1 Rc=0)
+* addco.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/addc_code.mdwn b/openpower/isa/fixedarith/addc_code.mdwn
new file mode 100644
index 00000000..056a1532
--- /dev/null
+++ b/openpower/isa/fixedarith/addc_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + (RB)
diff --git a/openpower/isa/fixedarith/adde.mdwn b/openpower/isa/fixedarith/adde.mdwn
new file mode 100644
index 00000000..1b2c0640
--- /dev/null
+++ b/openpower/isa/fixedarith/adde.mdwn
@@ -0,0 +1,18 @@
+# Add Extended
+
+XO-Form
+
+* adde RT,RA,RB (OE=0 Rc=0)
+* adde.  RT,RA,RB (OE=0 Rc=1)
+* addeo RT,RA,RB (OE=1 Rc=0)
+* addeo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/adde_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/adde_code.mdwn b/openpower/isa/fixedarith/adde_code.mdwn
new file mode 100644
index 00000000..2f3ce726
--- /dev/null
+++ b/openpower/isa/fixedarith/adde_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + (RB) + CA
diff --git a/openpower/isa/fixedarith/addex.mdwn b/openpower/isa/fixedarith/addex.mdwn
new file mode 100644
index 00000000..a18238c9
--- /dev/null
+++ b/openpower/isa/fixedarith/addex.mdwn
@@ -0,0 +1,13 @@
+# Add Extended using alternate carry bit
+
+Z23-Form
+
+* addex RT,RA,RB,CY
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addex_code" raw="yes"]]
+
+Special Registers Altered:
+
+    OV OV32                (if CY=0 )
diff --git a/openpower/isa/fixedarith/addex_code.mdwn b/openpower/isa/fixedarith/addex_code.mdwn
new file mode 100644
index 00000000..2d9bb4fd
--- /dev/null
+++ b/openpower/isa/fixedarith/addex_code.mdwn
@@ -0,0 +1 @@
+    if CY=0 then RT <- (RA) + (RB) + OV
diff --git a/openpower/isa/fixedarith/addi.mdwn b/openpower/isa/fixedarith/addi.mdwn
new file mode 100644
index 00000000..f8ecaca7
--- /dev/null
+++ b/openpower/isa/fixedarith/addi.mdwn
@@ -0,0 +1,13 @@
+# Add Immediate
+
+D-Form
+
+* addi RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/addi_code.mdwn b/openpower/isa/fixedarith/addi_code.mdwn
new file mode 100644
index 00000000..5d226be1
--- /dev/null
+++ b/openpower/isa/fixedarith/addi_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA|0) + EXTS(SI)
diff --git a/openpower/isa/fixedarith/addic..mdwn b/openpower/isa/fixedarith/addic..mdwn
new file mode 100644
index 00000000..dec27d5d
--- /dev/null
+++ b/openpower/isa/fixedarith/addic..mdwn
@@ -0,0 +1,13 @@
+# Add Immediate Carrying and Record
+
+D-Form
+
+* addic. RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addic._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 CA CA32
diff --git a/openpower/isa/fixedarith/addic._code.mdwn b/openpower/isa/fixedarith/addic._code.mdwn
new file mode 100644
index 00000000..c90b4dd0
--- /dev/null
+++ b/openpower/isa/fixedarith/addic._code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + EXTS(SI)
diff --git a/openpower/isa/fixedarith/addic.mdwn b/openpower/isa/fixedarith/addic.mdwn
new file mode 100644
index 00000000..798a2138
--- /dev/null
+++ b/openpower/isa/fixedarith/addic.mdwn
@@ -0,0 +1,13 @@
+# Add Immediate Carrying
+
+D-Form
+
+* addic RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addic_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
diff --git a/openpower/isa/fixedarith/addic_code.mdwn b/openpower/isa/fixedarith/addic_code.mdwn
new file mode 100644
index 00000000..c90b4dd0
--- /dev/null
+++ b/openpower/isa/fixedarith/addic_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + EXTS(SI)
diff --git a/openpower/isa/fixedarith/addis.mdwn b/openpower/isa/fixedarith/addis.mdwn
new file mode 100644
index 00000000..e5a02a70
--- /dev/null
+++ b/openpower/isa/fixedarith/addis.mdwn
@@ -0,0 +1,13 @@
+# Add Immediate Shifted
+
+D-Form
+
+* addis RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/addis_code.mdwn b/openpower/isa/fixedarith/addis_code.mdwn
new file mode 100644
index 00000000..5ea3670d
--- /dev/null
+++ b/openpower/isa/fixedarith/addis_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA|0) + EXTS(SI || [0]*16)
diff --git a/openpower/isa/fixedarith/addme.mdwn b/openpower/isa/fixedarith/addme.mdwn
new file mode 100644
index 00000000..64e089d8
--- /dev/null
+++ b/openpower/isa/fixedarith/addme.mdwn
@@ -0,0 +1,18 @@
+# Add to Minus One Extended
+
+XO-Form
+
+* addme RT,RA (OE=0 Rc=0)
+* addme.  RT,RA (OE=0 Rc=1)
+* addmeo RT,RA (OE=1 Rc=0)
+* addmeo.  RT,RA (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addme_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/addme_code.mdwn b/openpower/isa/fixedarith/addme_code.mdwn
new file mode 100644
index 00000000..240998ff
--- /dev/null
+++ b/openpower/isa/fixedarith/addme_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + CA - 1
diff --git a/openpower/isa/fixedarith/addpcis.mdwn b/openpower/isa/fixedarith/addpcis.mdwn
new file mode 100644
index 00000000..ad6fef9c
--- /dev/null
+++ b/openpower/isa/fixedarith/addpcis.mdwn
@@ -0,0 +1,13 @@
+# Add PC Immediate Shifted
+
+DX-Form
+
+* addpcis RT,D
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addpcis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/addpcis_code.mdwn b/openpower/isa/fixedarith/addpcis_code.mdwn
new file mode 100644
index 00000000..64997567
--- /dev/null
+++ b/openpower/isa/fixedarith/addpcis_code.mdwn
@@ -0,0 +1,2 @@
+    D <- d0||d1||d2
+    RT <- NIA + EXTS(D || [0]*16)
diff --git a/openpower/isa/fixedarith/addze.mdwn b/openpower/isa/fixedarith/addze.mdwn
new file mode 100644
index 00000000..0163af0f
--- /dev/null
+++ b/openpower/isa/fixedarith/addze.mdwn
@@ -0,0 +1,18 @@
+# Add to Zero Extended
+
+XO-Form
+
+* addze RT,RA (OE=0 Rc=0)
+* addze.  RT,RA (OE=0 Rc=1)
+* addzeo RT,RA (OE=1 Rc=0)
+* addzeo.  RT,RA (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/addze_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/addze_code.mdwn b/openpower/isa/fixedarith/addze_code.mdwn
new file mode 100644
index 00000000..e290a92d
--- /dev/null
+++ b/openpower/isa/fixedarith/addze_code.mdwn
@@ -0,0 +1 @@
+    RT <- (RA) + CA
diff --git a/openpower/isa/fixedarith/darn.mdwn b/openpower/isa/fixedarith/darn.mdwn
new file mode 100644
index 00000000..5322b996
--- /dev/null
+++ b/openpower/isa/fixedarith/darn.mdwn
@@ -0,0 +1,13 @@
+# Deliver A Random Number
+
+X-Form
+
+* darn RT,L3
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/darn_code" raw="yes"]]
+
+Special Registers Altered:
+
+    none
diff --git a/openpower/isa/fixedarith/darn_code.mdwn b/openpower/isa/fixedarith/darn_code.mdwn
new file mode 100644
index 00000000..22aea604
--- /dev/null
+++ b/openpower/isa/fixedarith/darn_code.mdwn
@@ -0,0 +1 @@
+    RT <- random(L3)
diff --git a/openpower/isa/fixedarith/divd.mdwn b/openpower/isa/fixedarith/divd.mdwn
new file mode 100644
index 00000000..fd23e7b1
--- /dev/null
+++ b/openpower/isa/fixedarith/divd.mdwn
@@ -0,0 +1,17 @@
+# Divide Doubleword
+
+XO-Form
+
+* divd RT,RA,RB (OE=0 Rc=0)
+* divd.  RT,RA,RB (OE=0 Rc=1)
+* divdo RT,RA,RB (OE=1 Rc=0)
+* divdo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/divd_code.mdwn b/openpower/isa/fixedarith/divd_code.mdwn
new file mode 100644
index 00000000..0206b44d
--- /dev/null
+++ b/openpower/isa/fixedarith/divd_code.mdwn
@@ -0,0 +1,10 @@
+    dividend[0:XLEN-1] <- (RA)
+    divisor[0:XLEN-1] <- (RB)
+    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
+         (divisor = [1]*XLEN)) |
+         (divisor = [0]*XLEN)) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT <- DIVS(dividend, divisor)
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/divde.mdwn b/openpower/isa/fixedarith/divde.mdwn
new file mode 100644
index 00000000..9777b6ff
--- /dev/null
+++ b/openpower/isa/fixedarith/divde.mdwn
@@ -0,0 +1,17 @@
+# Divide Doubleword Extended
+
+XO-Form
+
+* divde RT,RA,RB (OE=0 Rc=0)
+* divde.  RT,RA,RB (OE=0 Rc=1)
+* divdeo RT,RA,RB (OE=1 Rc=0)
+* divdeo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divde_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/divde_code.mdwn b/openpower/isa/fixedarith/divde_code.mdwn
new file mode 100644
index 00000000..bc4707ec
--- /dev/null
+++ b/openpower/isa/fixedarith/divde_code.mdwn
@@ -0,0 +1,16 @@
+    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
+    divisor[0:(XLEN*2)-1] <- EXTS128((RB))
+    if (((dividend = (0b1 || ([0b0] * ((XLEN*2)-1)))) &
+         (divisor = [1]*(XLEN*2))) |
+         (divisor = [0]*(XLEN*2))) then
+        overflow <- 1
+    else
+        result <- DIVS(dividend, divisor)
+        result_half[0:(XLEN*2)-1] <- EXTS128(result[XLEN:(XLEN*2)-1])
+        if (result_half = result) then
+            RT <- result[XLEN:(XLEN*2)-1]
+            overflow <- 0
+        else
+            overflow <- 1
+    if overflow = 1 then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
diff --git a/openpower/isa/fixedarith/divdeu.mdwn b/openpower/isa/fixedarith/divdeu.mdwn
new file mode 100644
index 00000000..eb47f6da
--- /dev/null
+++ b/openpower/isa/fixedarith/divdeu.mdwn
@@ -0,0 +1,17 @@
+# Divide Doubleword Extended Unsigned
+
+XO-Form
+
+* divdeu RT,RA,RB (OE=0 Rc=0)
+* divdeu.  RT,RA,RB (OE=0 Rc=1)
+* divdeuo RT,RA,RB (OE=1 Rc=0)
+* divdeuo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divdeu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/divdeu_code.mdwn b/openpower/isa/fixedarith/divdeu_code.mdwn
new file mode 100644
index 00000000..f44a9fe8
--- /dev/null
+++ b/openpower/isa/fixedarith/divdeu_code.mdwn
@@ -0,0 +1,13 @@
+    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
+    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
+    if divisor = [0]*(XLEN*2) then
+        overflow <- 1
+    else
+        result <- dividend / divisor
+        if (RA) <u (RB) then
+            RT <- result[XLEN:(XLEN*2)-1]
+            overflow <- 0
+        else
+            overflow <- 1
+    if overflow = 1 then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
diff --git a/openpower/isa/fixedarith/divdu.mdwn b/openpower/isa/fixedarith/divdu.mdwn
new file mode 100644
index 00000000..0f4ed86b
--- /dev/null
+++ b/openpower/isa/fixedarith/divdu.mdwn
@@ -0,0 +1,17 @@
+# Divide Doubleword Unsigned
+
+XO-Form
+
+* divdu RT,RA,RB (OE=0 Rc=0)
+* divdu.  RT,RA,RB (OE=0 Rc=1)
+* divduo RT,RA,RB (OE=1 Rc=0)
+* divduo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divdu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/divdu_code.mdwn b/openpower/isa/fixedarith/divdu_code.mdwn
new file mode 100644
index 00000000..d44bbd20
--- /dev/null
+++ b/openpower/isa/fixedarith/divdu_code.mdwn
@@ -0,0 +1,8 @@
+    dividend[0:XLEN-1] <- (RA)
+    divisor[0:XLEN-1] <- (RB)
+    if (divisor = [0]*XLEN) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT <- dividend / divisor
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/divw.mdwn b/openpower/isa/fixedarith/divw.mdwn
new file mode 100644
index 00000000..5d7b9df7
--- /dev/null
+++ b/openpower/isa/fixedarith/divw.mdwn
@@ -0,0 +1,17 @@
+# Divide Word
+
+XO-Form
+
+* divw RT,RA,RB (OE=0 Rc=0)
+* divw.  RT,RA,RB (OE=0 Rc=1)
+* divwo RT,RA,RB (OE=1 Rc=0)
+* divwo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+    SO OV OV32                              (if OE=1)
diff --git a/openpower/isa/fixedarith/divw_code.mdwn b/openpower/isa/fixedarith/divw_code.mdwn
new file mode 100644
index 00000000..32f1aca7
--- /dev/null
+++ b/openpower/isa/fixedarith/divw_code.mdwn
@@ -0,0 +1,11 @@
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
+    divisor[0:(XLEN/2)-1] <- (RB) [XLEN/2:XLEN-1]
+    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
+         (divisor = [1]*(XLEN/2))) |
+         (divisor = [0]*(XLEN/2))) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT[XLEN/2:XLEN-1] <- DIVS(dividend, divisor)
+        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/divwe.mdwn b/openpower/isa/fixedarith/divwe.mdwn
new file mode 100644
index 00000000..da2c80ea
--- /dev/null
+++ b/openpower/isa/fixedarith/divwe.mdwn
@@ -0,0 +1,17 @@
+# Divide Word Extended
+
+XO-Form
+
+* divwe RT,RA,RB (OE=0 Rc=0)
+* divwe.  RT,RA,RB (OE=0 Rc=1)
+* divweo RT,RA,RB (OE=1 Rc=0)
+* divweo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divwe_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+    SO OV OV32                              (if OE=1)
diff --git a/openpower/isa/fixedarith/divwe_code.mdwn b/openpower/isa/fixedarith/divwe_code.mdwn
new file mode 100644
index 00000000..002d119b
--- /dev/null
+++ b/openpower/isa/fixedarith/divwe_code.mdwn
@@ -0,0 +1,17 @@
+    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
+    divisor[0:XLEN-1] <- EXTS64((RB)[XLEN/2:XLEN-1])
+    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
+         (divisor = [1]*XLEN)) |
+         (divisor = [0]*XLEN)) then
+        overflow <- 1
+    else
+        result <- DIVS(dividend, divisor)
+        result_half[0:XLEN-1] <- EXTS64(result[XLEN/2:XLEN-1])
+        if (result_half = result) then
+            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
+            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+            overflow <- 0
+        else
+            overflow <- 1
+    if overflow = 1 then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
diff --git a/openpower/isa/fixedarith/divweu.mdwn b/openpower/isa/fixedarith/divweu.mdwn
new file mode 100644
index 00000000..e9fdced6
--- /dev/null
+++ b/openpower/isa/fixedarith/divweu.mdwn
@@ -0,0 +1,17 @@
+# Divide Word Extended Unsigned
+
+XO-Form
+
+* divweu RT,RA,RB (OE=0 Rc=0)
+* divweu.  RT,RA,RB (OE=0 Rc=1)
+* divweuo RT,RA,RB (OE=1 Rc=0)
+* divweuo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divweu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+    SO OV OV32                              (if OE=1)
diff --git a/openpower/isa/fixedarith/divweu_code.mdwn b/openpower/isa/fixedarith/divweu_code.mdwn
new file mode 100644
index 00000000..5c7de09e
--- /dev/null
+++ b/openpower/isa/fixedarith/divweu_code.mdwn
@@ -0,0 +1,14 @@
+    dividend[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] || [0]*(XLEN/2)
+    divisor[0:XLEN-1] <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1]
+    if (divisor = [0]*XLEN) then
+        overflow <- 1
+    else
+        result <- dividend / divisor
+        if RA[XLEN/2:XLEN-1] <u RB[XLEN/2:XLEN-1] then
+            RT[XLEN/2:XLEN-1] <- result[XLEN/2:XLEN-1]
+            RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+            overflow <- 0
+        else
+            overflow <- 1
+    if overflow = 1 then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
diff --git a/openpower/isa/fixedarith/divwu.mdwn b/openpower/isa/fixedarith/divwu.mdwn
new file mode 100644
index 00000000..7970e969
--- /dev/null
+++ b/openpower/isa/fixedarith/divwu.mdwn
@@ -0,0 +1,17 @@
+# Divide Word Unsigned
+
+XO-Form
+
+* divwu RT,RA,RB (OE=0 Rc=0)
+* divwu.  RT,RA,RB (OE=0 Rc=1)
+* divwuo RT,RA,RB (OE=1 Rc=0)
+* divwuo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/divwu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+    SO OV OV32                              (if OE=1)
diff --git a/openpower/isa/fixedarith/divwu_code.mdwn b/openpower/isa/fixedarith/divwu_code.mdwn
new file mode 100644
index 00000000..d3cfce4b
--- /dev/null
+++ b/openpower/isa/fixedarith/divwu_code.mdwn
@@ -0,0 +1,9 @@
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
+    divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
+    if divisor != 0 then
+        RT[XLEN/2:XLEN-1] <- dividend / divisor
+        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+        overflow <- 0
+    else
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
diff --git a/openpower/isa/fixedarith/maddhd.mdwn b/openpower/isa/fixedarith/maddhd.mdwn
new file mode 100644
index 00000000..e85326b6
--- /dev/null
+++ b/openpower/isa/fixedarith/maddhd.mdwn
@@ -0,0 +1,13 @@
+# Multiply-Add High Doubleword VA-Form
+
+VA-Form
+
+* maddhd RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/maddhd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/maddhd_code.mdwn b/openpower/isa/fixedarith/maddhd_code.mdwn
new file mode 100644
index 00000000..7b73ad67
--- /dev/null
+++ b/openpower/isa/fixedarith/maddhd_code.mdwn
@@ -0,0 +1,3 @@
+    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
+    sum[0:(XLEN*2)-1] <- prod + EXTS(RC)[0:XLEN*2]
+    RT <- sum[0:XLEN-1]
diff --git a/openpower/isa/fixedarith/maddhdu.mdwn b/openpower/isa/fixedarith/maddhdu.mdwn
new file mode 100644
index 00000000..5751fb71
--- /dev/null
+++ b/openpower/isa/fixedarith/maddhdu.mdwn
@@ -0,0 +1,13 @@
+# Multiply-Add High Doubleword Unsigned
+
+VA-Form
+
+* maddhdu RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/maddhdu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/maddhdu_code.mdwn b/openpower/isa/fixedarith/maddhdu_code.mdwn
new file mode 100644
index 00000000..7823e095
--- /dev/null
+++ b/openpower/isa/fixedarith/maddhdu_code.mdwn
@@ -0,0 +1,3 @@
+    prod[0:(XLEN*2)-1] <- (RA) * (RB)
+    sum[0:(XLEN*2)-1] <- prod + EXTZ(RC)
+    RT <- sum[0:XLEN-1]
diff --git a/openpower/isa/fixedarith/maddld.mdwn b/openpower/isa/fixedarith/maddld.mdwn
new file mode 100644
index 00000000..02c702bf
--- /dev/null
+++ b/openpower/isa/fixedarith/maddld.mdwn
@@ -0,0 +1,13 @@
+# Multiply-Add Low Doubleword
+
+VA-Form
+
+* maddld RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/maddld_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/maddld_code.mdwn b/openpower/isa/fixedarith/maddld_code.mdwn
new file mode 100644
index 00000000..ee52c739
--- /dev/null
+++ b/openpower/isa/fixedarith/maddld_code.mdwn
@@ -0,0 +1,3 @@
+    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
+    sum[0:(XLEN*2)-1] <- prod + EXTS(RC)
+    RT <- sum[XLEN:(XLEN*2)-1]
diff --git a/openpower/isa/fixedarith/modsd.mdwn b/openpower/isa/fixedarith/modsd.mdwn
new file mode 100644
index 00000000..1d38d33e
--- /dev/null
+++ b/openpower/isa/fixedarith/modsd.mdwn
@@ -0,0 +1,13 @@
+# Modulo Signed Doubleword
+
+X-Form
+
+* modsd RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/modsd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/modsd_code.mdwn b/openpower/isa/fixedarith/modsd_code.mdwn
new file mode 100644
index 00000000..944d430d
--- /dev/null
+++ b/openpower/isa/fixedarith/modsd_code.mdwn
@@ -0,0 +1,10 @@
+    dividend <- (RA)
+    divisor <- (RB)
+    if (((dividend = (0b1 || ([0b0] * (XLEN-1)))) &
+         (divisor = [1]*XLEN)) |
+         (divisor = [0]*XLEN)) then
+        RT[0:63] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT <- MODS(dividend, divisor)
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/modsw.mdwn b/openpower/isa/fixedarith/modsw.mdwn
new file mode 100644
index 00000000..2bcdbf1f
--- /dev/null
+++ b/openpower/isa/fixedarith/modsw.mdwn
@@ -0,0 +1,13 @@
+# Modulo Signed Word
+
+X-Form
+
+* modsw RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/modsw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/modsw_code.mdwn b/openpower/isa/fixedarith/modsw_code.mdwn
new file mode 100644
index 00000000..6b935bf7
--- /dev/null
+++ b/openpower/isa/fixedarith/modsw_code.mdwn
@@ -0,0 +1,11 @@
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
+    divisor[0:(XLEN/2)-1] <- (RB)[XLEN/2:XLEN-1]
+    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
+         (divisor = [1]*(XLEN/2))) |
+         (divisor = [0]*(XLEN/2))) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT[0:XLEN-1] <- EXTS64(MODS(dividend, divisor))
+        RT[0:(XLEN/2)-1] <- undefined(RT[0:(XLEN/2)-1])
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/modud.mdwn b/openpower/isa/fixedarith/modud.mdwn
new file mode 100644
index 00000000..11e6464b
--- /dev/null
+++ b/openpower/isa/fixedarith/modud.mdwn
@@ -0,0 +1,15 @@
+# Modulo Unsigned Doubleword
+
+X-Form
+
+* modud RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/modud_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Checked March 2021 -->
diff --git a/openpower/isa/fixedarith/modud_code.mdwn b/openpower/isa/fixedarith/modud_code.mdwn
new file mode 100644
index 00000000..86f74f4f
--- /dev/null
+++ b/openpower/isa/fixedarith/modud_code.mdwn
@@ -0,0 +1,8 @@
+    dividend <- (RA)
+    divisor <- (RB)
+    if (divisor = [0]*XLEN) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
+        overflow <- 1
+    else
+        RT <- dividend % divisor
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/moduw.mdwn b/openpower/isa/fixedarith/moduw.mdwn
new file mode 100644
index 00000000..9c7c712a
--- /dev/null
+++ b/openpower/isa/fixedarith/moduw.mdwn
@@ -0,0 +1,13 @@
+# Modulo Unsigned Word
+
+X-Form
+
+* moduw RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/moduw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/moduw_code.mdwn b/openpower/isa/fixedarith/moduw_code.mdwn
new file mode 100644
index 00000000..26c75a4a
--- /dev/null
+++ b/openpower/isa/fixedarith/moduw_code.mdwn
@@ -0,0 +1,9 @@
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:63]
+    divisor [0:(XLEN/2)-1] <- (RB)[XLEN/2:63]
+    if divisor = [0]*(XLEN/2) then
+        RT[0:XLEN-1] <- undefined([0]*64)
+        overflow <- 1
+    else
+        RT[XLEN/2:XLEN-1] <- dividend % divisor
+        RT[0:(XLEN/2)-1] <- undefined([0]*(XLEN/2))
+        overflow <- 0
diff --git a/openpower/isa/fixedarith/mulhd.mdwn b/openpower/isa/fixedarith/mulhd.mdwn
new file mode 100644
index 00000000..78822504
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhd.mdwn
@@ -0,0 +1,14 @@
+# Multiply High Doubleword
+
+XO-Form
+
+* mulhd RT,RA,RB (Rc=0)
+* mulhd.  RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulhd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/fixedarith/mulhd_code.mdwn b/openpower/isa/fixedarith/mulhd_code.mdwn
new file mode 100644
index 00000000..69d287c0
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhd_code.mdwn
@@ -0,0 +1,2 @@
+    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
+    RT <- prod[0:XLEN-1]
diff --git a/openpower/isa/fixedarith/mulhdu.mdwn b/openpower/isa/fixedarith/mulhdu.mdwn
new file mode 100644
index 00000000..98f81c5f
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhdu.mdwn
@@ -0,0 +1,14 @@
+# Multiply High Doubleword Unsigned
+
+XO-Form
+
+* mulhdu RT,RA,RB (Rc=0)
+* mulhdu.  RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulhdu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/fixedarith/mulhdu_code.mdwn b/openpower/isa/fixedarith/mulhdu_code.mdwn
new file mode 100644
index 00000000..d455f52e
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhdu_code.mdwn
@@ -0,0 +1,2 @@
+    prod[0:(XLEN*2)-1] <- (RA) * (RB)
+    RT <- prod[0:XLEN-1]
diff --git a/openpower/isa/fixedarith/mulhw.mdwn b/openpower/isa/fixedarith/mulhw.mdwn
new file mode 100644
index 00000000..05d01b9b
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhw.mdwn
@@ -0,0 +1,14 @@
+# Multiply High Word
+
+XO-Form
+
+* mulhw RT,RA,RB (Rc=0)
+* mulhw.  RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulhw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
diff --git a/openpower/isa/fixedarith/mulhw_code.mdwn b/openpower/isa/fixedarith/mulhw_code.mdwn
new file mode 100644
index 00000000..ec4384f2
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhw_code.mdwn
@@ -0,0 +1,3 @@
+    prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
+    RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
+    RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
diff --git a/openpower/isa/fixedarith/mulhwu.mdwn b/openpower/isa/fixedarith/mulhwu.mdwn
new file mode 100644
index 00000000..709b5fcf
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhwu.mdwn
@@ -0,0 +1,14 @@
+# Multiply High Word Unsigned
+
+XO-Form
+
+* mulhwu RT,RA,RB (Rc=0)
+* mulhwu.  RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulhwu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
diff --git a/openpower/isa/fixedarith/mulhwu_code.mdwn b/openpower/isa/fixedarith/mulhwu_code.mdwn
new file mode 100644
index 00000000..227c0b20
--- /dev/null
+++ b/openpower/isa/fixedarith/mulhwu_code.mdwn
@@ -0,0 +1,3 @@
+    prod[0:XLEN-1] <- (RA)[XLEN/2:XLEN-1] * (RB)[XLEN/2:XLEN-1]
+    RT[XLEN/2:XLEN-1] <- prod[0:(XLEN/2)-1]
+    RT[0:(XLEN/2)-1] <- undefined(prod[0:(XLEN/2)-1])
diff --git a/openpower/isa/fixedarith/mulld.mdwn b/openpower/isa/fixedarith/mulld.mdwn
new file mode 100644
index 00000000..3b8b57ba
--- /dev/null
+++ b/openpower/isa/fixedarith/mulld.mdwn
@@ -0,0 +1,17 @@
+# Multiply Low Doubleword
+
+XO-Form
+
+* mulld RT,RA,RB (OE=0 Rc=0)
+* mulld.  RT,RA,RB (OE=0 Rc=1)
+* mulldo RT,RA,RB (OE=1 Rc=0)
+* mulldo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulld_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/mulld_code.mdwn b/openpower/isa/fixedarith/mulld_code.mdwn
new file mode 100644
index 00000000..2a3ebeb5
--- /dev/null
+++ b/openpower/isa/fixedarith/mulld_code.mdwn
@@ -0,0 +1,4 @@
+    prod[0:(XLEN*2)-1] <- MULS((RA), (RB))
+    RT <- prod[XLEN:(XLEN*2)-1]
+    overflow <- ((prod[0:XLEN] != [0]*(XLEN+1)) &
+                 (prod[0:XLEN] != [1]*(XLEN+1)))
diff --git a/openpower/isa/fixedarith/mulli.mdwn b/openpower/isa/fixedarith/mulli.mdwn
new file mode 100644
index 00000000..765f46b8
--- /dev/null
+++ b/openpower/isa/fixedarith/mulli.mdwn
@@ -0,0 +1,13 @@
+# Multiply Low Immediate
+
+D-Form
+
+* mulli RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mulli_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/fixedarith/mulli_code.mdwn b/openpower/isa/fixedarith/mulli_code.mdwn
new file mode 100644
index 00000000..5db27b8c
--- /dev/null
+++ b/openpower/isa/fixedarith/mulli_code.mdwn
@@ -0,0 +1,2 @@
+    prod[0:(XLEN*2)-1] <- MULS((RA), EXTS(SI))
+    RT <- prod[XLEN:(XLEN*2)-1]
diff --git a/openpower/isa/fixedarith/mullw.mdwn b/openpower/isa/fixedarith/mullw.mdwn
new file mode 100644
index 00000000..74ff59c8
--- /dev/null
+++ b/openpower/isa/fixedarith/mullw.mdwn
@@ -0,0 +1,17 @@
+# Multiply Low Word
+
+XO-Form
+
+* mullw RT,RA,RB (OE=0 Rc=0)
+* mullw.  RT,RA,RB (OE=0 Rc=1)
+* mullwo RT,RA,RB (OE=1 Rc=0)
+* mullwo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/mullw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/mullw_code.mdwn b/openpower/isa/fixedarith/mullw_code.mdwn
new file mode 100644
index 00000000..8bcddcf5
--- /dev/null
+++ b/openpower/isa/fixedarith/mullw_code.mdwn
@@ -0,0 +1,4 @@
+    prod[0:XLEN-1] <- MULS((RA)[XLEN/2:XLEN-1], (RB)[XLEN/2:XLEN-1])
+    RT <- prod
+    overflow <- ((prod[0:XLEN/2] != [0]*((XLEN/2)+1)) &
+                 (prod[0:XLEN/2] != [1]*((XLEN/2)+1)))
diff --git a/openpower/isa/fixedarith/neg.mdwn b/openpower/isa/fixedarith/neg.mdwn
new file mode 100644
index 00000000..e71c279b
--- /dev/null
+++ b/openpower/isa/fixedarith/neg.mdwn
@@ -0,0 +1,17 @@
+# Negate
+
+XO-Form
+
+* neg RT,RA (OE=0 Rc=0)
+* neg.  RT,RA (OE=0 Rc=1)
+* nego RT,RA (OE=1 Rc=0)
+* nego.  RT,RA (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/neg_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/neg_code.mdwn b/openpower/isa/fixedarith/neg_code.mdwn
new file mode 100644
index 00000000..99e7911b
--- /dev/null
+++ b/openpower/isa/fixedarith/neg_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + 1
diff --git a/openpower/isa/fixedarith/subf.mdwn b/openpower/isa/fixedarith/subf.mdwn
new file mode 100644
index 00000000..c286eb73
--- /dev/null
+++ b/openpower/isa/fixedarith/subf.mdwn
@@ -0,0 +1,17 @@
+# Subtract From
+
+XO-Form
+
+* subf RT,RA,RB (OE=0 Rc=0)
+* subf.  RT,RA,RB (OE=0 Rc=1)
+* subfo RT,RA,RB (OE=1 Rc=0)
+* subfo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subf_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/subf_code.mdwn b/openpower/isa/fixedarith/subf_code.mdwn
new file mode 100644
index 00000000..36749efc
--- /dev/null
+++ b/openpower/isa/fixedarith/subf_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + (RB) + 1
diff --git a/openpower/isa/fixedarith/subfc.mdwn b/openpower/isa/fixedarith/subfc.mdwn
new file mode 100644
index 00000000..d6af11a0
--- /dev/null
+++ b/openpower/isa/fixedarith/subfc.mdwn
@@ -0,0 +1,18 @@
+# Subtract From Carrying
+
+XO-Form
+
+* subfc RT,RA,RB (OE=0 Rc=0)
+* subfc.  RT,RA,RB (OE=0 Rc=1)
+* subfco RT,RA,RB (OE=1 Rc=0)
+* subfco.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subfc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/subfc_code.mdwn b/openpower/isa/fixedarith/subfc_code.mdwn
new file mode 100644
index 00000000..36749efc
--- /dev/null
+++ b/openpower/isa/fixedarith/subfc_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + (RB) + 1
diff --git a/openpower/isa/fixedarith/subfe.mdwn b/openpower/isa/fixedarith/subfe.mdwn
new file mode 100644
index 00000000..4347c1ec
--- /dev/null
+++ b/openpower/isa/fixedarith/subfe.mdwn
@@ -0,0 +1,18 @@
+# Subtract From Extended
+
+XO-Form
+
+* subfe RT,RA,RB (OE=0 Rc=0)
+* subfe.  RT,RA,RB (OE=0 Rc=1)
+* subfeo RT,RA,RB (OE=1 Rc=0)
+* subfeo.  RT,RA,RB (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subfe_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/subfe_code.mdwn b/openpower/isa/fixedarith/subfe_code.mdwn
new file mode 100644
index 00000000..0227b884
--- /dev/null
+++ b/openpower/isa/fixedarith/subfe_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + (RB) + CA
diff --git a/openpower/isa/fixedarith/subfic.mdwn b/openpower/isa/fixedarith/subfic.mdwn
new file mode 100644
index 00000000..7ba300e8
--- /dev/null
+++ b/openpower/isa/fixedarith/subfic.mdwn
@@ -0,0 +1,13 @@
+# Subtract From Immediate Carrying
+
+D-Form
+
+* subfic RT,RA,SI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subfic_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
diff --git a/openpower/isa/fixedarith/subfic_code.mdwn b/openpower/isa/fixedarith/subfic_code.mdwn
new file mode 100644
index 00000000..a930d909
--- /dev/null
+++ b/openpower/isa/fixedarith/subfic_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + EXTS(SI) + 1
diff --git a/openpower/isa/fixedarith/subfme.mdwn b/openpower/isa/fixedarith/subfme.mdwn
new file mode 100644
index 00000000..4be00906
--- /dev/null
+++ b/openpower/isa/fixedarith/subfme.mdwn
@@ -0,0 +1,18 @@
+# Subtract From Minus One Extended
+
+XO-Form
+
+* subfme RT,RA (OE=0 Rc=0)
+* subfme.  RT,RA (OE=0 Rc=1)
+* subfmeo RT,RA (OE=1 Rc=0)
+* subfmeo.  RT,RA (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subfme_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/subfme_code.mdwn b/openpower/isa/fixedarith/subfme_code.mdwn
new file mode 100644
index 00000000..46eaf19e
--- /dev/null
+++ b/openpower/isa/fixedarith/subfme_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + CA - 1
diff --git a/openpower/isa/fixedarith/subfze.mdwn b/openpower/isa/fixedarith/subfze.mdwn
new file mode 100644
index 00000000..bb3c68ca
--- /dev/null
+++ b/openpower/isa/fixedarith/subfze.mdwn
@@ -0,0 +1,18 @@
+# Subtract From Zero Extended
+
+XO-Form
+
+* subfze RT,RA (OE=0 Rc=0)
+* subfze.  RT,RA (OE=0 Rc=1)
+* subfzeo RT,RA (OE=1 Rc=0)
+* subfzeo.  RT,RA (OE=1 Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedarith/subfze_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CA CA32
+    CR0                     (if Rc=1)
+    SO OV OV32             (if OE=1)
diff --git a/openpower/isa/fixedarith/subfze_code.mdwn b/openpower/isa/fixedarith/subfze_code.mdwn
new file mode 100644
index 00000000..158c16e9
--- /dev/null
+++ b/openpower/isa/fixedarith/subfze_code.mdwn
@@ -0,0 +1 @@
+    RT <- ¬(RA) + CA