From: Claire Wolf <claire@symbioticeda.com>
Date: Sun, 17 May 2020 09:31:11 +0000 (+0200)
Subject: Revert "Add support for non-power-of-two mem chunks in verific importer"
X-Git-Tag: working-ls180~550
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa;p=yosys.git

Revert "Add support for non-power-of-two mem chunks in verific importer"

This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5f8a78e48..fe4bda68e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			int numchunks = int(inst->OutputSize()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
 
-			if ((numchunks * memory->width) != int(inst->OutputSize()))
+			if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0)
 				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
 
 			for (int i = 0; i < numchunks; i++)
@@ -1273,11 +1273,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
 				RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
 
-				if ((numchunks & (numchunks - 1)) != 0) {
-					addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
-					addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
-				}
-
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
 						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
 				cell->parameters[ID::MEMID] = memory->name.str();
@@ -1300,7 +1295,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			int numchunks = int(inst->Input2Size()) / memory->width;
 			int chunksbits = ceil_log2(numchunks);
 
-			if ((numchunks * memory->width) != int(inst->Input2Size()))
+			if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0)
 				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
 
 			for (int i = 0; i < numchunks; i++)
@@ -1308,11 +1303,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
 				RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
 
-				if ((numchunks & (numchunks - 1)) != 0) {
-					addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
-					addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
-				}
-
 				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
 						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
 				cell->parameters[ID::MEMID] = memory->name.str();