From: H.J. Lu <hjl.tools@gmail.com>
Date: Tue, 23 Dec 2008 15:14:15 +0000 (+0000)
Subject: gas/
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa99fab2229b2e05faf2d2939e841c1d4a0b82b6;p=binutils-gdb.git

gas/

2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (match_template): Changed to return
	 const template *.  Handle i.swap_operand for 3 operands.
	 (build_vex_prefix): Take const template *.  Swap operand for
	 2-byte VEX prefix if possible.
	 (md_assemble): Updated.
	 (build_modrm_byte): Handle RegMem bit for SSE2AVX.

gas/testsuite/

2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.

	* gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
	vmovss.
	* gas/i386/x86-64-opts.s: Likewise.

	* gas/i386/opts.d: Updated.
	* gas/i386/opts-intel.d: Likewise.
	* gas/i386/sse2avx-opts.d: Likewise.
	* gas/i386/sse2avx-opts-intel.d: Likewise.
	* gas/i386/x86-64-opts.d: Likewise.
	* gas/i386/x86-64-opts-intel.d: Likewise.
	* gas/i386/x86-64-sse2avx-opts.d: Likewise.
	* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.

	* gas/i386/x86-64-avx-swap.d: New.
	* gas/i386/x86-64-avx-swap.s: Likewise.
	* gas/i386/x86-64-avx-swap-intel.d: Likewise.

opcodes/

2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (EXdS): New.
	(EXdVexS): Likewise.
	(EXqVexS): Likewise.
	(d_swap_mode): Likewise.
	(q_mode): Updated.
	(prefix_table): Use EXdS on movss and EXqS on movsd.
	(vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
	(intel_operand_size): Handle d_swap_mode.
	(OP_EX): Likewise.

	* i386-opc.h (S): Update comments.

	* i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
	* i386-tbl.h: Regenerated.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b39d7cbb209..7029e6a28ed 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,10 +1,19 @@
+2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Changed to return
+	 const template *.  Handle i.swap_operand for 3 operands.
+	 (build_vex_prefix): Take const template *.  Swap operand for
+	 2-byte VEX prefix if possible.
+	 (md_assemble): Updated.
+	 (build_modrm_byte): Handle RegMem bit for SSE2AVX.
+
 2008-12-23  Anatoly Sokolov  <aesok@post.ru>
 
-        * config/tc-avr.c (mcu_types): Add attiny87, attiny327, atmega4hvd,
-        atmega8hvd, atmega16hvb, atmega32hvb, atmega64c1, atmega16m1, 
-        atmega64m1, atmega32u6, atmega128rfa1,  at90pwm81, at90scr100, 
-        m3000f, m3000s and m3001b devices.
-        * doc/c-avr.texi: Likewise.
+	* config/tc-avr.c (mcu_types): Add attiny87, attiny327, atmega4hvd,
+	atmega8hvd, atmega16hvb, atmega32hvb, atmega64c1, atmega16m1, 
+	atmega64m1, atmega32u6, atmega128rfa1,  at90pwm81, at90scr100, 
+	m3000f, m3000s and m3001b devices.
+	* doc/c-avr.texi: Likewise.
 
 2008-12-23  Nick Clifton  <nickc@redhat.com>
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5505d5cd517..d3f5d86ce1b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -180,7 +180,7 @@ static void swap_operands (void);
 static void swap_2_operands (int, int);
 static void optimize_imm (void);
 static void optimize_disp (void);
-static int match_template (void);
+static const template *match_template (void);
 static int check_string (void);
 static int process_suffix (void);
 static int check_byte_reg (void);
@@ -2543,7 +2543,7 @@ intel_float_operand (const char *mnemonic)
 /* Build the VEX prefix.  */
 
 static void
-build_vex_prefix (void)
+build_vex_prefix (const template *t)
 {
   unsigned int register_specifier;
   unsigned int implied_prefix;
@@ -2560,6 +2560,36 @@ build_vex_prefix (void)
   else
     register_specifier = 0xf;
 
+  /* Use 2-byte VEX prefix by swappping destination and source
+     operand.  */
+  if (!i.swap_operand
+      && i.operands == i.reg_operands
+      && i.tm.opcode_modifier.vex0f
+      && i.tm.opcode_modifier.s
+      && i.rex == REX_B)
+    {
+      unsigned int xchg = i.operands - 1;
+      union i386_op temp_op;
+      i386_operand_type temp_type;
+
+      temp_type = i.types[xchg];
+      i.types[xchg] = i.types[0];
+      i.types[0] = temp_type;
+      temp_op = i.op[xchg];
+      i.op[xchg] = i.op[0];
+      i.op[0] = temp_op;
+
+      assert (i.rm.mode == 3);
+
+      i.rex = REX_R;
+      xchg = i.rm.regmem;
+      i.rm.regmem = i.rm.reg;
+      i.rm.reg = xchg;
+
+      /* Use the next insn.  */
+      i.tm = t[1];
+    }
+
   vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
 
   switch ((i.tm.base_opcode >> 8) & 0xff)
@@ -2691,6 +2721,7 @@ md_assemble (char *line)
 {
   unsigned int j;
   char mnemonic[MAX_MNEM_SIZE];
+  const template *t;
 
   /* Initialize globals.  */
   memset (&i, '\0', sizeof (i));
@@ -2748,7 +2779,7 @@ md_assemble (char *line)
      making sure the overlap of the given operands types is consistent
      with the template operand types.  */
 
-  if (!match_template ())
+  if (!(t = match_template ()))
     return;
 
   if (sse_check != sse_check_none
@@ -2829,7 +2860,7 @@ md_assemble (char *line)
     }
 
   if (i.tm.opcode_modifier.vex)
-    build_vex_prefix ();
+    build_vex_prefix (t);
 
   /* Handle conversion of 'int $3' --> special int3 insn.  */
   if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
@@ -3548,7 +3579,7 @@ VEX_check_operands (const template *t)
   return 0;
 }
 
-static int
+static const template *
 match_template (void)
 {
   /* Points to template once we've found it.  */
@@ -3742,6 +3773,9 @@ match_template (void)
 	    }
 
 	case 3:
+	  /* If we swap operand in encoding, we match the next one.  */
+	  if (i.swap_operand && t->opcode_modifier.s)
+	    continue;
 	case 4:
 	case 5:
 	  overlap1 = operand_type_and (i.types[1], operand_types[1]);
@@ -3866,7 +3900,7 @@ check_reverse:
       else
 	as_bad (_("suffix or operands invalid for `%s'"),
 		current_templates->start->name);
-      return 0;
+      return NULL;
     }
 
   if (!quiet_warnings)
@@ -3906,7 +3940,7 @@ check_reverse:
       i.tm.operand_types[1] = operand_types[0];
     }
 
-  return 1;
+  return t;
 }
 
 static int
@@ -5325,12 +5359,13 @@ build_modrm_byte (void)
 	    {
 	      /* For instructions with VexNDS, the register-only
 		 source operand must be XMM or YMM register. It is
-		 encoded in VEX prefix.  */
+		 encoded in VEX prefix.  We need to clear RegMem bit
+		 before calling operand_type_equal.  */
+	      i386_operand_type op = i.tm.operand_types[dest];
+	      op.bitfield.regmem = 0;
 	      if ((dest + 1) >= i.operands
-		  || (!operand_type_equal (&i.tm.operand_types[dest],
-					   &regxmm)
-		      && !operand_type_equal (&i.tm.operand_types[dest],
-					      &regymm)))
+		  || (!operand_type_equal (&op, &regxmm)
+		      && !operand_type_equal (&op, &regymm)))
 		abort ();
 	      i.vex.register_specifier = i.op[dest].regs;
 	      dest++;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 587c0704bbd..25e94a50963 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,24 @@
+2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.
+
+	* gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
+	vmovss.
+	* gas/i386/x86-64-opts.s: Likewise.
+
+	* gas/i386/opts.d: Updated.
+	* gas/i386/opts-intel.d: Likewise.
+	* gas/i386/sse2avx-opts.d: Likewise.
+	* gas/i386/sse2avx-opts-intel.d: Likewise.
+	* gas/i386/x86-64-opts.d: Likewise.
+	* gas/i386/x86-64-opts-intel.d: Likewise.
+	* gas/i386/x86-64-sse2avx-opts.d: Likewise.
+	* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
+
+	* gas/i386/x86-64-avx-swap.d: New.
+	* gas/i386/x86-64-avx-swap.s: Likewise.
+	* gas/i386/x86-64-avx-swap-intel.d: Likewise.
+
 2008-12-23  Nick Clifton  <nickc@redhat.com>
 
 	* gas/elf/type.s: Remove test of STT_IFUNC support.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1d9ed4f6e9a..a0ad99728ed 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -301,6 +301,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-opts-intel"
     run_dump_test "x86-64-sse2avx-opts"
     run_dump_test "x86-64-sse2avx-opts-intel"
+    run_dump_test "x86-64-avx-swap"
+    run_dump_test "x86-64-avx-swap-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/opts-intel.d b/gas/testsuite/gas/i386/opts-intel.d
index e7f5f41d34d..e51a659f3c6 100644
--- a/gas/testsuite/gas/i386/opts-intel.d
+++ b/gas/testsuite/gas/i386/opts-intel.d
@@ -42,6 +42,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups xmm6,xmm4
@@ -60,6 +64,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 [ 	]*[a-f0-9]+:	88 d1                	mov    cl,dl
@@ -90,6 +98,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups xmm6,xmm4
@@ -108,6 +120,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 #pass
diff --git a/gas/testsuite/gas/i386/opts.d b/gas/testsuite/gas/i386/opts.d
index f0f1e0bfab9..5292ad3d0f0 100644
--- a/gas/testsuite/gas/i386/opts.d
+++ b/gas/testsuite/gas/i386/opts.d
@@ -41,6 +41,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups %xmm4,%xmm6
@@ -59,6 +63,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 [ 	]*[a-f0-9]+:	88 d1                	movb   %dl,%cl
@@ -89,6 +97,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups %xmm4,%xmm6
@@ -107,6 +119,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 #pass
diff --git a/gas/testsuite/gas/i386/opts.s b/gas/testsuite/gas/i386/opts.s
index 0a66017a9ba..dfa773b6b9e 100644
--- a/gas/testsuite/gas/i386/opts.s
+++ b/gas/testsuite/gas/i386/opts.s
@@ -43,6 +43,10 @@ _start:
 	movdqu.s %xmm4,%xmm6
 	movq %xmm4,%xmm6
 	movq.s %xmm4,%xmm6
+	movsd %xmm4,%xmm6
+	movsd.s %xmm4,%xmm6
+	movss %xmm4,%xmm6
+	movss.s %xmm4,%xmm6
 	movupd %xmm4,%xmm6
 	movupd.s %xmm4,%xmm6
 	movups %xmm4,%xmm6
@@ -62,6 +66,12 @@ _start:
 	vmovups %xmm4,%xmm6
 	vmovups.s %xmm4,%xmm6
 
+# Tests for op xmm, xmm, xmm
+	vmovsd %xmm4,%xmm6,%xmm2
+	vmovsd.s %xmm4,%xmm6,%xmm2
+	vmovss %xmm4,%xmm6,%xmm2
+	vmovss.s %xmm4,%xmm6,%xmm2
+
 # Tests for op mm, mm
 	movq %mm0,%mm4
 	movq.s %mm0,%mm4
@@ -101,6 +111,10 @@ _start:
 	movdqu.s xmm6,xmm4
 	movq xmm6,xmm4
 	movq.s xmm6,xmm4
+	movsd xmm6,xmm4
+	movsd.s xmm6,xmm4
+	movss xmm6,xmm4
+	movss.s xmm6,xmm4
 	movupd xmm6,xmm4
 	movupd.s xmm6,xmm4
 	movups xmm6,xmm4
@@ -120,6 +134,12 @@ _start:
 	vmovups xmm6,xmm4
 	vmovups.s xmm6,xmm4
 
+# Tests for op xmm, xmm, xmm
+	vmovsd xmm2,xmm6,xmm4
+	vmovsd.s xmm2,xmm6,xmm4
+	vmovss xmm2,xmm6,xmm4
+	vmovss.s xmm2,xmm6,xmm4
+
 # Tests for op mm, mm
 	movq mm4,mm0
 	movq.s mm4,mm0
diff --git a/gas/testsuite/gas/i386/sse2avx-opts-intel.d b/gas/testsuite/gas/i386/sse2avx-opts-intel.d
index 66ec7bd65b1..4c1334fdbfd 100644
--- a/gas/testsuite/gas/i386/sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts-intel.d
@@ -43,6 +43,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s xmm6,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
@@ -61,6 +65,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 [ 	]*[a-f0-9]+:	88 d1                	mov    cl,dl
@@ -91,6 +99,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s xmm6,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
@@ -109,6 +121,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 #pass
diff --git a/gas/testsuite/gas/i386/sse2avx-opts.d b/gas/testsuite/gas/i386/sse2avx-opts.d
index 0054c0abf5e..5c091e94dd5 100644
--- a/gas/testsuite/gas/i386/sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts.d
@@ -43,6 +43,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s %xmm4,%xmm6,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
@@ -61,6 +65,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 [ 	]*[a-f0-9]+:	88 d1                	movb   %dl,%cl
@@ -91,6 +99,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s %xmm4,%xmm6,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
@@ -109,6 +121,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-swap-intel.d b/gas/testsuite/gas/i386/x86-64-avx-swap-intel.d
new file mode 100644
index 00000000000..2bdfe0bf623
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-swap-intel.d
@@ -0,0 +1,60 @@
+#as: -msse2avx
+#objdump: -drwMintel
+#name: x86-64 AVX swap (Intel mode)
+#source: x86-64-avx-swap.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c5 7d 29 c6          	vmovapd ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7c 29 c6          	vmovaps ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7d 7f c6          	vmovdqa ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7e 7f c6          	vmovdqu ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7d 11 c6          	vmovupd ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7c 11 c6          	vmovups ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4b 11 c6          	vmovsd xmm6,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4a 11 c6          	vmovss xmm6,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4b 11 c2          	vmovsd xmm2,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4a 11 c2          	vmovss xmm2,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 7d 29 c6          	vmovapd ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7c 29 c6          	vmovaps ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7d 7f c6          	vmovdqa ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7e 7f c6          	vmovdqu ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7d 11 c6          	vmovupd ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 7c 11 c6          	vmovups ymm6,ymm8
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4b 11 c6          	vmovsd xmm6,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4a 11 c6          	vmovss xmm6,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4b 11 c2          	vmovsd xmm2,xmm6,xmm8
+[ 	]*[a-f0-9]+:	c5 4a 11 c2          	vmovss xmm2,xmm6,xmm8
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-swap.d b/gas/testsuite/gas/i386/x86-64-avx-swap.d
new file mode 100644
index 00000000000..356f4e4e422
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-swap.d
@@ -0,0 +1,59 @@
+#as: -msse2avx
+#objdump: -drw
+#name: x86-64 AVX swap
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c5 7d 29 c6          	vmovapd %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7c 29 c6          	vmovaps %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7d 7f c6          	vmovdqa %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7e 7f c6          	vmovdqu %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7d 11 c6          	vmovupd %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7c 11 c6          	vmovups %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 4b 11 c6          	vmovsd %xmm8,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 4a 11 c6          	vmovss %xmm8,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 4b 11 c2          	vmovsd %xmm8,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 4a 11 c2          	vmovss %xmm8,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 7d 29 c6          	vmovapd %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7c 29 c6          	vmovaps %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7d 7f c6          	vmovdqa %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7e 7f c6          	vmovdqu %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7d 11 c6          	vmovupd %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 7c 11 c6          	vmovups %ymm8,%ymm6
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 4b 11 c6          	vmovsd %xmm8,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 4a 11 c6          	vmovss %xmm8,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 29 c6          	vmovapd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 29 c6          	vmovaps %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 7f c6          	vmovdqa %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 7a 7f c6          	vmovdqu %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 d6 c6          	vmovq  %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 79 11 c6          	vmovupd %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 78 11 c6          	vmovups %xmm8,%xmm6
+[ 	]*[a-f0-9]+:	c5 4b 11 c2          	vmovsd %xmm8,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 4a 11 c2          	vmovss %xmm8,%xmm6,%xmm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-swap.s b/gas/testsuite/gas/i386/x86-64-avx-swap.s
new file mode 100644
index 00000000000..5afe5ccba26
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-swap.s
@@ -0,0 +1,67 @@
+# Check 64bit instructions with encoding options
+
+	.allow_index_reg
+	.text
+_start:
+
+# Tests for op ymm, ymm
+	vmovapd %ymm8,%ymm6
+	vmovaps %ymm8,%ymm6
+	vmovdqa %ymm8,%ymm6
+	vmovdqu %ymm8,%ymm6
+	vmovupd %ymm8,%ymm6
+	vmovups %ymm8,%ymm6
+
+# Tests for op xmm, xmm
+	movapd %xmm8,%xmm6
+	movaps %xmm8,%xmm6
+	movdqa %xmm8,%xmm6
+	movdqu %xmm8,%xmm6
+	movq %xmm8,%xmm6
+	movsd %xmm8,%xmm6
+	movss %xmm8,%xmm6
+	movupd %xmm8,%xmm6
+	movups %xmm8,%xmm6
+	vmovapd %xmm8,%xmm6
+	vmovaps %xmm8,%xmm6
+	vmovdqa %xmm8,%xmm6
+	vmovdqu %xmm8,%xmm6
+	vmovq %xmm8,%xmm6
+	vmovupd %xmm8,%xmm6
+	vmovups %xmm8,%xmm6
+
+# Tests for op xmm, xmm, xmm
+	vmovsd %xmm8,%xmm6,%xmm2
+	vmovss %xmm8,%xmm6,%xmm2
+
+	.intel_syntax noprefix
+
+# Tests for op ymm, ymm
+	vmovapd ymm6,ymm8
+	vmovaps ymm6,ymm8
+	vmovdqa ymm6,ymm8
+	vmovdqu ymm6,ymm8
+	vmovupd ymm6,ymm8
+	vmovups ymm6,ymm8
+
+# Tests for op xmm, xmm
+	movapd xmm6,xmm8
+	movaps xmm6,xmm8
+	movdqa xmm6,xmm8
+	movdqu xmm6,xmm8
+	movq xmm6,xmm8
+	movsd xmm6,xmm8
+	movss xmm6,xmm8
+	movupd xmm6,xmm8
+	movups xmm6,xmm8
+	vmovapd xmm6,xmm8
+	vmovaps xmm6,xmm8
+	vmovdqa xmm6,xmm8
+	vmovdqu xmm6,xmm8
+	vmovq xmm6,xmm8
+	vmovupd xmm6,xmm8
+	vmovups xmm6,xmm8
+
+# Tests for op xmm, xmm, xmm
+	vmovsd xmm2,xmm6,xmm8
+	vmovss xmm2,xmm6,xmm8
diff --git a/gas/testsuite/gas/i386/x86-64-opts-intel.d b/gas/testsuite/gas/i386/x86-64-opts-intel.d
index 3a92cb7e0ab..779d13542d9 100644
--- a/gas/testsuite/gas/i386/x86-64-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-opts-intel.d
@@ -46,6 +46,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups xmm6,xmm4
@@ -64,6 +68,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 [ 	]*[a-f0-9]+:	88 d1                	mov    cl,dl
@@ -96,6 +104,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  xmm6,xmm4
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups xmm6,xmm4
@@ -114,6 +126,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-opts.d b/gas/testsuite/gas/i386/x86-64-opts.d
index 43084cbb491..d50b4e86e0b 100644
--- a/gas/testsuite/gas/i386/x86-64-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-opts.d
@@ -45,6 +45,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups %xmm4,%xmm6
@@ -63,6 +67,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 [ 	]*[a-f0-9]+:	88 d1                	movb   %dl,%cl
@@ -95,6 +103,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f 7f e6          	movdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	f3 0f 7e f4          	movq   %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f d6 e6          	movq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 10 f4          	movsd  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f2 0f 11 e6          	movsd.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 10 f4          	movss  %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	f3 0f 11 e6          	movss.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 10 f4          	movupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	66 0f 11 e6          	movupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	0f 10 f4             	movups %xmm4,%xmm6
@@ -113,6 +125,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-opts.s b/gas/testsuite/gas/i386/x86-64-opts.s
index fc3aa67c19a..aa8e706a66e 100644
--- a/gas/testsuite/gas/i386/x86-64-opts.s
+++ b/gas/testsuite/gas/i386/x86-64-opts.s
@@ -47,6 +47,10 @@ _start:
 	movdqu.s %xmm4,%xmm6
 	movq %xmm4,%xmm6
 	movq.s %xmm4,%xmm6
+	movsd %xmm4,%xmm6
+	movsd.s %xmm4,%xmm6
+	movss %xmm4,%xmm6
+	movss.s %xmm4,%xmm6
 	movupd %xmm4,%xmm6
 	movupd.s %xmm4,%xmm6
 	movups %xmm4,%xmm6
@@ -66,6 +70,12 @@ _start:
 	vmovups %xmm4,%xmm6
 	vmovups.s %xmm4,%xmm6
 
+# Tests for op xmm, xmm, xmm
+	vmovsd %xmm4,%xmm6,%xmm2
+	vmovsd.s %xmm4,%xmm6,%xmm2
+	vmovss %xmm4,%xmm6,%xmm2
+	vmovss.s %xmm4,%xmm6,%xmm2
+
 # Tests for op mm, mm
 	movq %mm0,%mm4
 	movq.s %mm0,%mm4
@@ -107,6 +117,10 @@ _start:
 	movdqu.s xmm6,xmm4
 	movq xmm6,xmm4
 	movq.s xmm6,xmm4
+	movsd xmm6,xmm4
+	movsd.s xmm6,xmm4
+	movss xmm6,xmm4
+	movss.s xmm6,xmm4
 	movupd xmm6,xmm4
 	movupd.s xmm6,xmm4
 	movups xmm6,xmm4
@@ -126,6 +140,12 @@ _start:
 	vmovups xmm6,xmm4
 	vmovups.s xmm6,xmm4
 
+# Tests for op xmm, xmm, xmm
+	vmovsd xmm2,xmm6,xmm4
+	vmovsd.s xmm2,xmm6,xmm4
+	vmovss xmm2,xmm6,xmm4
+	vmovss.s xmm2,xmm6,xmm4
+
 # Tests for op mm, mm
 	movq mm4,mm0
 	movq.s mm4,mm0
diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d b/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
index b1b7f3d6466..23513ba0c41 100644
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
@@ -47,6 +47,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s xmm6,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
@@ -65,6 +69,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 [ 	]*[a-f0-9]+:	88 d1                	mov    cl,dl
@@ -97,6 +105,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss xmm6,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s xmm6,xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
@@ -115,6 +127,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups xmm6,xmm4
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss xmm2,xmm6,xmm4
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s xmm2,xmm6,xmm4
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   mm4,mm0
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s mm4,mm0
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d b/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
index e6009179b50..6637fafcd55 100644
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
@@ -47,6 +47,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s %xmm4,%xmm6,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
@@ -65,6 +69,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 [ 	]*[a-f0-9]+:	88 d1                	movb   %dl,%cl
@@ -97,6 +105,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 fa 7f e6          	vmovdqu.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 fa 7e f4          	vmovq  %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 d6 e6          	vmovq.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 f4          	vmovsd %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 11 e6          	vmovsd.s %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 10 f4          	vmovss %xmm4,%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	c5 ca 11 e6          	vmovss.s %xmm4,%xmm6,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 10 f4          	vmovupd %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
@@ -115,6 +127,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 f9 11 e6          	vmovupd.s %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 10 f4          	vmovups %xmm4,%xmm6
 [ 	]*[a-f0-9]+:	c5 f8 11 e6          	vmovups.s %xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c5 cb 10 d4          	vmovsd %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 cb 11 e2          	vmovsd.s %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 10 d4          	vmovss %xmm4,%xmm6,%xmm2
+[ 	]*[a-f0-9]+:	c5 ca 11 e2          	vmovss.s %xmm4,%xmm6,%xmm2
 [ 	]*[a-f0-9]+:	0f 6f e0             	movq   %mm0,%mm4
 [ 	]*[a-f0-9]+:	0f 7f c4             	movq.s %mm0,%mm4
 #pass
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 25f81a689b2..962bdde1835 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,20 @@
+2008-12-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (EXdS): New.
+	(EXdVexS): Likewise.
+	(EXqVexS): Likewise.
+	(d_swap_mode): Likewise.
+	(q_mode): Updated.
+	(prefix_table): Use EXdS on movss and EXqS on movsd.
+	(vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
+	(intel_operand_size): Handle d_swap_mode.
+	(OP_EX): Likewise.
+
+	* i386-opc.h (S): Update comments.
+
+	* i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
+	* i386-tbl.h: Regenerated.
+
 2008-12-23  Nick Clifton  <nickc@redhat.com>
 
 	* po/ga.po: Updated Irish translation.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 50088d08678..e89f200295e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -362,6 +362,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define EMx { OP_EM, x_mode }
 #define EXw { OP_EX, w_mode }
 #define EXd { OP_EX, d_mode }
+#define EXdS { OP_EX, d_swap_mode }
 #define EXq { OP_EX, q_mode }
 #define EXqS { OP_EX, q_swap_mode }
 #define EXx { OP_EX, x_mode }
@@ -384,7 +385,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define VexFMA { OP_VEX_FMA, vex_mode }
 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 #define EXdVex { OP_EX_Vex, d_mode }
+#define EXdVexS { OP_EX_Vex, d_swap_mode }
 #define EXqVex { OP_EX_Vex, q_mode }
+#define EXqVexS { OP_EX_Vex, q_swap_mode }
 #define EXVexW { OP_EX_VexW, x_mode }
 #define EXdVexW { OP_EX_VexW, d_mode }
 #define EXqVexW { OP_EX_VexW, q_mode }
@@ -427,8 +430,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define w_mode			(v_swap_mode + 1)
 /* double word operand  */
 #define d_mode			(w_mode + 1)
+/* double word operand with operand swapped */
+#define d_swap_mode		(d_mode + 1)
 /* quad word operand */
-#define q_mode			(d_mode + 1)
+#define q_mode			(d_swap_mode + 1)
 /* quad word operand with operand swapped */
 #define q_swap_mode		(q_mode + 1)
 /* ten-byte operand */
@@ -2427,9 +2432,9 @@ static const struct dis386 prefix_table[][4] = {
   /* PREFIX_0F11 */
   {
     { "movups",	{ EXxS, XM } },
-    { "movss",	{ EXd, XM } },
+    { "movss",	{ EXdS, XM } },
     { "movupd",	{ EXxS, XM } },
-    { "movsd",	{ EXq, XM } },
+    { "movsd",	{ EXqS, XM } },
   },
 
   /* PREFIX_0F12 */
@@ -7843,13 +7848,13 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_11_P_1 */
   {
-    { "vmovss",		{ EXdVex, Vex128, XM } },
+    { "vmovss",		{ EXdVexS, Vex128, XM } },
     { "(bad)",		{ XX } },
   },
 
   /* VEX_LEN_11_P_3 */
   {
-    { "vmovsd",		{ EXqVex, Vex128, XM } },
+    { "vmovsd",		{ EXqVexS, Vex128, XM } },
     { "(bad)",		{ XX } },
   },
 
@@ -11415,6 +11420,7 @@ intel_operand_size (int bytemode, int sizeflag)
       used_prefixes |= (prefixes & PREFIX_DATA);
       break;
     case d_mode:
+    case d_swap_mode:
     case dqd_mode:
       oappend ("DWORD PTR ");
       break;
@@ -12652,7 +12658,9 @@ OP_EX (int bytemode, int sizeflag)
     add = 0;
 
   if ((sizeflag & SUFFIX_ALWAYS)
-      && (bytemode == x_swap_mode || bytemode == q_swap_mode))
+      && (bytemode == x_swap_mode
+	  || bytemode == d_swap_mode
+	  || bytemode == q_swap_mode))
     swap_operand ();
 
   /* Skip mod/rm byte.  */
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 13e874efbdf..7fa61c2d265 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -166,7 +166,8 @@ typedef union i386_cpu_flags
 #define D			0
 /* set if operands can be words or dwords encoded the canonical way */
 #define W			(D + 1)
-/* Swap operand in encoding. */
+/* Skip the current insn and use the next insn in i386-opc.tbl to swap
+   operand in encoding.  */
 #define S			(W + 1)
 /* insn has a modrm byte. */
 #define Modrm			(S + 1)
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 190a7206c66..29d3a0f1868 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1224,8 +1224,9 @@ movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|
 movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movss, 2, 0xf30f10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+movss, 2, 0xf310, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
+movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|RegMem }
+movss, 2, 0xf30f10, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
 movups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
@@ -1396,8 +1397,9 @@ movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
 movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movsd, 2, 0xf20f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+movsd, 2, 0xf210, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
+movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|Regmem }
+movsd, 2, 0xf20f10, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
 movupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
@@ -2076,12 +2078,12 @@ vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bS
 vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 // vmovd really shouldn't allow for 64bit operand (vmovq is the right
 // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
@@ -2095,12 +2097,12 @@ vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_w
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
@@ -2126,21 +2128,23 @@ vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_w
 vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
 vmovsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vmovsd, 3, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovsd, 3, 0xf210, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
 vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
-vmovss, 3, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovss, 3, 0xf310, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
 vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
+vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
 vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
 vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
 vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index ba48468d1ed..553582e0aaa 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -10462,7 +10462,7 @@ const template i386_optab[] =
   { "movss", 2, 0xf310, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -10471,10 +10471,22 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
+  { "movss", 2, 0xf311, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "movss", 2, 0xf30f10, None, 2,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -12484,7 +12496,7 @@ const template i386_optab[] =
   { "movsd", 2, 0xf210, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -12493,10 +12505,22 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
+  { "movsd", 2, 0xf211, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "movsd", 2, 0xf20f10, None, 2,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21073,18 +21097,6 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovapd", 2, 0x6628, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovapd", 2, 0x6629, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21097,6 +21109,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovapd", 2, 0x6628, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovapd", 2, 0x6629, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21121,18 +21145,6 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovaps", 2, 0x28, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovaps", 2, 0x29, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21145,6 +21157,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovaps", 2, 0x28, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovaps", 2, 0x29, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21241,18 +21265,6 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovdqa", 2, 0x666f, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovdqa", 2, 0x667f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21265,6 +21277,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovdqa", 2, 0x666f, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovdqa", 2, 0x667f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21289,18 +21313,6 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovdqu", 2, 0xf36f, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovdqu", 2, 0xf37f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21313,6 +21325,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovdqu", 2, 0xf36f, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovdqu", 2, 0xf37f, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21634,7 +21658,7 @@ const template i386_optab[] =
   { "vmovsd", 3, 0xf210, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21646,6 +21670,21 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
+  { "vmovsd", 3, 0xf211, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovshdup", 2, 0xf316, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21721,7 +21760,7 @@ const template i386_optab[] =
   { "vmovss", 3, 0xf310, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
@@ -21733,28 +21772,31 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovupd", 2, 0x6610, None, 1,
+  { "vmovss", 3, 0xf311, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+      1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 0, 1, 0, 0, 0 } },
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovupd", 2, 0x6610, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 0, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovupd", 2, 0x6611, None, 1,
@@ -21769,6 +21811,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovupd", 2, 0x6610, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovupd", 2, 0x6611, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21793,18 +21847,6 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
-  { "vmovups", 2, 0x10, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 1, 1, 0, 0, 0 } },
-      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovups", 2, 0x11, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -21817,6 +21859,18 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  1, 0, 1, 0, 0, 0 } } } },
+  { "vmovups", 2, 0x10, None, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+        0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+      1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 1, 1, 0, 0, 0 } },
+      { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  0, 0, 0, 0, 0, 0 } } } },
   { "vmovups", 2, 0x11, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },