From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 13 Feb 2021 18:59:17 +0000 (-0300)
Subject: Fix imports and whitespace
X-Git-Tag: convert-csv-opcode-to-binary~231^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fab47551b729849a2b302e646f9e0429756a17a9;p=soc.git

Fix imports and whitespace
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index bf785010..c8e98524 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -1,8 +1,7 @@
-import random
-from soc.fu.test.common import (TestCase, TestAccumulatorBase)
+from soc.fu.test.common import TestAccumulatorBase
 from soc.config.endian import bigendian
 from soc.simulator.program import Program
-from soc.decoder.isa.caller import special_sprs
+from soc.decoder.isa.caller import SVP64State
 from soc.sv.trans.svp64 import SVP64Asm
 
 
@@ -10,21 +9,20 @@ class SVP64ALUTestCase(TestAccumulatorBase):
 
     def case_1_sv_add(self):
         # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
-                       ])
+        #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
+        #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
+        isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
         lst = list(isa)
-        print ("listing", lst)
+        print("listing", lst)
         initial_regs = [0] * 32
         initial_regs[9] = 0x1234
         initial_regs[10] = 0x1111
         initial_regs[5] = 0x4321
         initial_regs[6] = 0x2223
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl[0:7] = 2  # VL
+        svstate.maxvl[0:7] = 2  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)