From: lkcl <lkcl@web>
Date: Thu, 9 Jun 2022 12:53:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1896
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fabfb35565e5b16b40a806403491fab9770c9bb3;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 664357eef..e46e3feb3 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -2,7 +2,7 @@
 
 [[!toc]]
 
-SVP64 is designed around these fundamental and inviolate principles:
+SVP64 is designed around these fundamental and inviolate RISC principles:
 
 1. There are no actual Vector instructions: Scalar instructions
    are the sole exclusive bedrock.
@@ -61,6 +61,8 @@ also having it as a Scalar un-prefixed instruction is that if the
 then how can a Vectorised version of that new instruction ever be added?
 Bottom line here is that the fundamental RISC Principle is strictly adhered
 to, even though these are Advanced 64-bit Vector instructions.
+Advocates of the RISC Principle will appreciate the uniformity of
+SVP64 and the level of systematic abstraction kept between Prefix and Suffix.
 
 # Instruction Groups