From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 11:04:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1091
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fad225b8c3add43a169d261d503d912c13b583e1;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 09788b519..6d1c137c8 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -12,12 +12,15 @@ instructions vertical and registers horizontal otherwise it will be
 difficult to grasp and appreciate its RISC simplicity.
 
 Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
-ubiquitous: the ISA uniform.  GPUs may implement massive-wide
-SIMD back-ends, focussing on
-number-crunching.  Existing Multi-issue Superscalar implementations may
-insert Simple-V between decode and issue with minimal disruption.
-Single-issue in-order implementations are very straightforward.  All
-implementations regardless of back-end capability may execute the exact
+ubiquitous, the ISA uniform.
+
+* GPUs may implement massive-wide SIMD back-ends, focussing on
+  number-crunching.
+* Existing Multi-issue Superscalar implementations may
+  insert Simple-V between decode and issue with minimal disruption.
+* Single-issue in-order implementations are very straightforward.
+
+All implementations regardless of back-end capability may execute the exact
 same binaries *(this is known to be extremely important to the Power ISA
 ecosystem)*.