From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 3 Apr 2021 18:21:37 +0000 (-0300)
Subject: Signal the simulator when completing a VL loop
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fad3cd5f00155f88148c608d3abe85e25c416a11;p=soc.git

Signal the simulator when completing a VL loop

When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 8d9bec5e..075655f1 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -628,6 +628,8 @@ class TestIssuerInternal(Elaboratable):
                             comb += new_svstate.srcstep.eq(0)
                             comb += new_svstate.dststep.eq(0)
                             comb += update_svstate.eq(1)
+                            # synchronize with the simulator
+                            comb += self.insn_done.eq(1)
                             # go back to Issue
                             m.next = "ISSUE_START"
                         with m.Else():