From: lkcl <lkcl@web>
Date: Sat, 24 Sep 2022 23:35:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fad757394f23ea40314840cb679918f733ef47ae;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index ca45a8515..fc84c0a85 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -229,3 +229,16 @@ confirming the definition of registers (RA as the same example):
      W0 = H0||H1, W1 = H2||H3
      D0 = W0||W1
      RA = D0
+
+If we then perform the following **arithmetic** operations (assuming
+starting all zeros):
+
+    RA = 1 << 63
+    RB = 128
+    RT = 3 + 4
+
+The following bits are set (all others zero):
+
+    RA.b0 = 1    RA.B0 = 0x80  RA.H0 = 0x8000  RA.W0 = 0x80000000
+    RB.b56 = 1   RB.B7 = 0x08  RB.H3 = 0x0008  RB.W1 = 0x00000008
+    RT.b61-3 = 1 RT.B7 = 0x07  RT.H3 = 0x0007  RT.W1 = 0x00000007