From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 09:43:38 +0000 (+0100)
Subject: Added $_DFFE_??_ cell types
X-Git-Tag: yosys-0.5~264
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4;p=yosys.git

Added $_DFFE_??_ cell types
---

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 3d9e4cf93..f58ae14c4 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -156,6 +156,10 @@ struct CellTypes
 		for (auto c1 : list_np)
 			setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"});
 
+		for (auto c1 : list_np)
+		for (auto c2 : list_np)
+			setup_type(stringf("$_DFFE_%c%c_", c1, c2), {"\\C", "\\D", "\\E"}, {"\\Q"});
+
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 803d783af..321c39e10 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -892,6 +892,11 @@ namespace {
 			if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
 			if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
 
+			if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
+			if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
+			if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
+			if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
+
 			if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
 			if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
 			if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 88566411a..eb62d7830 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -163,6 +163,38 @@ always @(posedge C) begin
 end
 endmodule
 
+module  \$_DFFE_NN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+	if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_NP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+	if (E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+	if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+	if (E) Q <= D;
+end
+endmodule
+
 module  \$_DFF_NN0_ (D, Q, C, R);
 input D, C, R;
 output reg Q;