From: Florent Kermarrec Date: Mon, 15 Dec 2014 18:48:22 +0000 (+0100) Subject: bist: add count to bist parameters X-Git-Tag: 24jan2021_ls180~2572^2~110 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fadd21fae2afda80db5b5f3b9eba71c473bf823d;p=litex.git bist: add count to bist parameters --- diff --git a/lib/sata/__init__.py b/lib/sata/__init__.py index 7c76dcf6..d9f56e4a 100644 --- a/lib/sata/__init__.py +++ b/lib/sata/__init__.py @@ -6,9 +6,9 @@ from lib.sata.transport import SATATransport from lib.sata.command import SATACommand class SATACON(Module): - def __init__(self, phy, sector_size=512, max_count=16): + def __init__(self, phy, sector_size=512, max_count=8): self.submodules.link = SATALink(phy) self.submodules.transport = SATATransport(self.link) - self.submodules.command = SATACommand(self.transport) + self.submodules.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count) self.sink, self.source = self.command.sink, self.command.source diff --git a/lib/sata/bist.py b/lib/sata/bist.py index e6539736..c5d793c1 100644 --- a/lib/sata/bist.py +++ b/lib/sata/bist.py @@ -5,12 +5,13 @@ from lib.sata.common import * from lib.sata.link.scrambler import Scrambler class SATABIST(Module): - def __init__(self, sector_size=512, max_count=1): + def __init__(self, sector_size=512): self.sink = sink = Sink(command_rx_description(32)) self.source = source = Source(command_tx_description(32)) self.start = Signal() self.sector = Signal(48) + self.count = Signal(4) self.done = Signal() self.ctrl_errors = Signal(32) self.data_errors = Signal(32) @@ -42,10 +43,10 @@ class SATABIST(Module): fsm.act("SEND_WRITE_CMD_AND_DATA", source.stb.eq(1), source.sop.eq((counter.value == 0)), - source.eop.eq((counter.value == (sector_size*max_count)//4-1)), + source.eop.eq((counter.value == (sector_size//4*self.count)-1)), source.write.eq(1), source.sector.eq(self.sector), - source.count.eq(max_count), + source.count.eq(self.count), source.data.eq(scrambler.value), counter.ce.eq(source.ack), If(source.stb & source.eop & source.ack, @@ -67,7 +68,7 @@ class SATABIST(Module): source.eop.eq(1), source.read.eq(1), source.sector.eq(self.sector), - source.count.eq(max_count), + source.count.eq(self.count), If(source.ack, NextState("WAIT_READ_ACK") ) diff --git a/lib/sata/test/bist_tb.py b/lib/sata/test/bist_tb.py index 51744158..c48141cc 100644 --- a/lib/sata/test/bist_tb.py +++ b/lib/sata/test/bist_tb.py @@ -18,7 +18,7 @@ class TB(Module): transport_debug=False, transport_loopback=False, hdd_debug=True) self.submodules.controller = SATACON(self.hdd.phy) - self.submodules.bist = SATABIST(max_count=2) + self.submodules.bist = SATABIST() self.comb += [ self.bist.source.connect(self.controller.sink), self.controller.source.connect(self.bist.sink) @@ -27,6 +27,8 @@ class TB(Module): def gen_simulation(self, selfp): hdd = self.hdd hdd.malloc(0, 64) + selfp.bist.sector = 0 + selfp.bist.count = 4 while True: selfp.bist.start = 1 yield @@ -36,6 +38,7 @@ class TB(Module): yield print("ctrl_errors: {} / data_errors {}".format(selfp.bist.ctrl_errors, selfp.bist.data_errors)) selfp.bist.sector += 1 + selfp.bist.count = max((selfp.bist.count + 1)%8, 1) if __name__ == "__main__": - run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True) + run_simulation(TB(), ncycles=8192*2, vcd_name="my.vcd", keep_files=True)