From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 20 Sep 2023 22:22:06 +0000 (-0700)
Subject: Revert "fix PowerDecoder2 to properly decode scalar EXTRA2"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fafe81deaabb98e055483b9cb78ad9b43ab43c1e;p=openpower-isa.git

Revert "fix PowerDecoder2 to properly decode scalar EXTRA2"

Luke wants all changes to EXTRA2/3 decoding to be in one commit, restore to original state

This reverts commit 630dfa6c8b6633d66d1a41368dfad927754846ed.
---

diff --git a/src/openpower/decoder/power_svp64_extra.py b/src/openpower/decoder/power_svp64_extra.py
index 620f0660..c956eb99 100644
--- a/src/openpower/decoder/power_svp64_extra.py
+++ b/src/openpower/decoder/power_svp64_extra.py
@@ -105,11 +105,8 @@ class SVP64RegExtra(SVP64ExtraSpec):
         with m.If(self.isvec):
             # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
             comb += self.reg_out.eq(Cat(spec_aug, self.reg_in))
-        with m.Elif(self.etype == SVEType.EXTRA2):
-            # Scalar EXTRA2: not shifted up, extra in MSBs RA | (spec[1] << 5)
-            comb += self.reg_out.eq(Cat(self.reg_in, spec_aug[1]))
-        with m.Elif(self.etype == SVEType.EXTRA3):
-            # Scalar EXTRA3: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
+        with m.Else():
+            # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
             comb += self.reg_out.eq(Cat(self.reg_in, spec_aug))
 
         return m