From: Jason Ekstrand Date: Sat, 12 Nov 2016 17:35:37 +0000 (-0800) Subject: intel/genxml: Make some 3DSTATE_PS fields more consistent X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb02d2d13b76646c7050055f461e4acd09035a62;p=mesa.git intel/genxml: Make some 3DSTATE_PS fields more consistent Reviewed-by: Timothy Arceri Reviewed-by: Kristian H. Kristensen --- diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 07c335aee52..4a98371e6f6 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -630,9 +630,9 @@ blorp_emit_ps_config(struct blorp_batch *batch, #endif if (prog_data) { - ps.DispatchGRFStartRegisterforConstantSetupData0 = + ps.DispatchGRFStartRegisterForConstantSetupData0 = prog_data->base.dispatch_grf_start_reg; - ps.DispatchGRFStartRegisterforConstantSetupData2 = + ps.DispatchGRFStartRegisterForConstantSetupData2 = prog_data->dispatch_grf_start_reg_2; ps.KernelStartPointer0 = params->wm_prog_kernel; @@ -692,9 +692,9 @@ blorp_emit_ps_config(struct blorp_batch *batch, if (prog_data) { wm.ThreadDispatchEnable = true; - wm.DispatchGRFStartRegisterforConstantSetupData0 = + wm.DispatchGRFStartRegisterForConstantSetupData0 = prog_data->base.dispatch_grf_start_reg; - wm.DispatchGRFStartRegisterforConstantSetupData2 = + wm.DispatchGRFStartRegisterForConstantSetupData2 = prog_data->dispatch_grf_start_reg_2; wm.KernelStartPointer0 = params->wm_prog_kernel; diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index ad130d95738..60e403a6d34 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1459,9 +1459,9 @@ - - - + + + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 9bf38143445..7ac421fed60 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -1393,9 +1393,9 @@ - - - + + + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 280e7c4aba3..2e61e7bea07 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -1624,9 +1624,9 @@ - - - + + + diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index 3765d14b909..40e1d8130cb 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -168,10 +168,10 @@ genX(graphics_pipeline_create)( ps._16PixelDispatchEnable = wm_prog_data->dispatch_16; ps._8PixelDispatchEnable = wm_prog_data->dispatch_8; - ps.DispatchGRFStartRegisterforConstantSetupData0 = + ps.DispatchGRFStartRegisterForConstantSetupData0 = wm_prog_data->base.dispatch_grf_start_reg, - ps.DispatchGRFStartRegisterforConstantSetupData1 = 0, - ps.DispatchGRFStartRegisterforConstantSetupData2 = + ps.DispatchGRFStartRegisterForConstantSetupData1 = 0, + ps.DispatchGRFStartRegisterForConstantSetupData2 = wm_prog_data->dispatch_grf_start_reg_2; /* Haswell requires the sample mask to be set in this packet as well as