From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 13 Jul 2019 07:52:21 +0000 (-0700)
Subject: Add comment
X-Git-Tag: working-ls180~1190^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb062c3426e8acb5b3f54dfed7209631208fec81;p=yosys.git

Add comment
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 4a6ec3a47..658bb1225 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -787,6 +787,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				sink_cell->setParam("\\LUT", mask);
 			}
 
+			// Since we have rewritten all sinks (which we know
+			// to be only LUTs) to be after the inverter, we can
+			// go ahead and clone the LUT with the expectation
+			// that the original driving LUT will become dangling
+			// and get cleaned away
 clone_lut:
 			driver_mask = driver_lut->getParam("\\LUT");
 			for (auto &b : driver_mask.bits) {