From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 22:03:21 +0000 (-0700)
Subject: Undo iterator based Module::remove() for cells, as containers will not
X-Git-Tag: working-ls180~1237^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb30fcb7c582406f627ebb15833791411091f738;p=yosys.git

Undo iterator based Module::remove() for cells, as containers will not
invalidate
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 502b45cfd..a09f4a0d1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1592,21 +1592,13 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 
 void RTLIL::Module::remove(RTLIL::Cell *cell)
 {
-	auto it = cells_.find(cell->name);
-	log_assert(it != cells_.end());
-	remove(it);
-}
-
-dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
-{
-	RTLIL::Cell *cell = it->second;
 	while (!cell->connections_.empty())
 		cell->unsetPort(cell->connections_.begin()->first);
 
+	log_assert(cells_.count(cell->name) != 0);
 	log_assert(refcount_cells_ == 0);
-	it = cells_.erase(it);
+	cells_.erase(cell->name);
 	delete cell;
-	return it;
 }
 
 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4a0f8b4f8..f4fcf5dcf 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1040,7 +1040,6 @@ public:
 	// Removing wires is expensive. If you have to remove wires, remove them all at once.
 	void remove(const pool<RTLIL::Wire*> &wires);
 	void remove(RTLIL::Cell *cell);
-	dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it);
 
 	void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
 	void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);