From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 18:17:08 +0000 (+0000) Subject: convert from public static functions/properties for regspecs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb3528750f912a762984a79654cce6601c52a994;p=soc.git convert from public static functions/properties for regspecs to member functions to obtain regspecs this allows pspec (containing XLEN) to be passed to the regspecs, which in turn allows them to be dynamically set by issuer_verilog.py and unit tests --- diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 1e552ff6..572ec9a6 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -3,30 +3,36 @@ from soc.fu.pipe_data import FUBaseData, CommonPipeSpec class ALUInputData(FUBaseData): - regspec = [('INT', 'ra', '0:63'), # RA - ('INT', 'rb', '0:63'), # RB/immediate - ('XER', 'xer_so', '32'), # XER bit 32: SO - ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32 - def __init__(self, pspec): super().__init__(pspec, False) # convenience self.a, self.b = self.ra, self.rb + @property + def regspec(self): + return [('INT', 'ra', self.intrange), # RA + ('INT', 'rb', self.intrange), # RB/immediate + ('XER', 'xer_so', '32'), # XER bit 32: SO + ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32 + + class ALUOutputData(FUBaseData): - regspec = [('INT', 'o', '0:63'), + def __init__(self, pspec): + super().__init__(pspec, True) + # convenience + self.cr0 = self.cr_a + + @property + def regspec(self): + return [('INT', 'o', self.intrange), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32 ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32 ('XER', 'xer_so', '32')] - def __init__(self, pspec): - super().__init__(pspec, True) - # convenience - self.cr0 = self.cr_a class ALUPipeSpec(CommonPipeSpec): - regspec = (ALUInputData.regspec, ALUOutputData.regspec) opsubsetkls = CompALUOpSubset + regspecklses = (ALUInputData, ALUOutputData) diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index a2f5bcf2..8a6c0071 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -57,5 +57,5 @@ class BranchOutputData(FUBaseData): class BranchPipeSpec(CommonPipeSpec): - regspec = (BranchInputData.regspec, BranchOutputData.regspec) + regspecklses = (BranchInputData, BranchOutputData) opsubsetkls = CompBROpSubset diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 1f6e2097..873a09df 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -120,7 +120,11 @@ class FunctionUnitBaseSingle(MultiCompUnit): # spec (NNNPipeSpec instance) pspec = speckls(id_wid=2, parent_pspec=parent_pspec) opsubset = pspec.opsubsetkls # get the operand subset class - regspec = pspec.regspec # get the regspec + rsk = pspec.regspecklses # get the regspec classes + regspec = [] + for kls in rsk: + regspec.append(kls(pspec).regspec) + print ("regspecs", regspec) alu = pipekls(pspec) # create actual NNNBasePipe self.pspec = pspec super().__init__(regspec, alu, opsubset, name=alu_name) # MultiCompUnit @@ -160,10 +164,14 @@ class FunctionUnitBaseMulti(ReservationStations2): # spec (NNNPipeSpec instance) pspec = speckls(id_wid=id_wid, parent_pspec=parent_pspec) - opsubset = pspec.opsubsetkls # get the operand subset class - regspec = pspec.regspec # get the regspec - alu = pipekls(pspec) # create actual NNNBasePipe self.pspec = pspec + opsubset = pspec.opsubsetkls # get the operand subset class + rsk = pspec.regspecklses # get the regspec classes + regspec = [] + for kls in rsk: + regspec.append(kls(pspec).regspec) + print ("regspecs", regspec) + alu = pipekls(pspec) # create actual NNNBasePipe alu_name = self.fnunit.name.lower() super().__init__(alu, num_rows, alu_name) # initialise fan-in/fan-out self.cu = [] @@ -284,7 +292,11 @@ class LDSTFunctionUnit(LDSTCompUnit): # spec (NNNPipeSpec instance) pspec = LDSTPipeSpec(id_wid=2, parent_pspec=parent_pspec) opsubset = pspec.opsubsetkls # get the operand subset class - regspec = pspec.regspec # get the regspec + rsk = pspec.regspecklses # get the regspec classes + regspec = [] + for kls in rsk: + regspec.append(kls(pspec).regspec) + print ("regspecs", regspec) self.opsubsetkls = opsubset super().__init__(pi, regspec, awid, opsubset, name=alu_name) diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index edcad2e9..f1c6d349 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -30,5 +30,5 @@ class CROutputData(FUBaseData): class CRPipeSpec(CommonPipeSpec): - regspec = (CRInputData.regspec, CROutputData.regspec) + regspecklses = (CRInputData, CROutputData) opsubsetkls = CompCROpSubset diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index f79f9806..dd4d1bed 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -134,7 +134,7 @@ class DivPipeSpec(CommonPipeSpec): self.div_pipe_kind = div_pipe_kind self.core_config = div_pipe_kind.config.core_config - regspec = (DivInputData.regspec, DivMulOutputData.regspec) + regspecklses = (DivInputData, DivMulOutputData) opsubsetkls = CompLogicalOpSubset diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py index fe45b6e8..caf8bf5a 100644 --- a/src/soc/fu/ldst/pipe_data.py +++ b/src/soc/fu/ldst/pipe_data.py @@ -32,5 +32,5 @@ class LDSTOutputData(FUBaseData): class LDSTPipeSpec(CommonPipeSpec): - regspec = (LDSTInputData.regspec, LDSTOutputData.regspec) + regspecklses = (LDSTInputData, LDSTOutputData) opsubsetkls = CompLDSTOpSubset diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 3d9077aa..40a18bc2 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -40,5 +40,5 @@ class LogicalOutputDataFinal(FUBaseData): class LogicalPipeSpec(CommonPipeSpec): - regspec = (LogicalInputData.regspec, LogicalOutputDataFinal.regspec) + regspecklses = (LogicalInputData, LogicalOutputDataFinal) opsubsetkls = CompLogicalOpSubset diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py index 9cc1ff08..7272a225 100644 --- a/src/soc/fu/mmu/pipe_data.py +++ b/src/soc/fu/mmu/pipe_data.py @@ -37,5 +37,5 @@ class MMUOutputData(FUBaseData): class MMUPipeSpec(CommonPipeSpec): - regspec = (MMUInputData.regspec, MMUOutputData.regspec) + regspecklses = (MMUInputData, MMUOutputData) opsubsetkls = CompMMUOpSubset diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py index a55e80d1..072c5da6 100644 --- a/src/soc/fu/mul/pipe_data.py +++ b/src/soc/fu/mul/pipe_data.py @@ -27,5 +27,5 @@ class MulOutputData(FUBaseData): class MulPipeSpec(CommonPipeSpec): - regspec = (DivInputData.regspec, DivMulOutputData.regspec) + regspecklses = (DivInputData, DivMulOutputData) opsubsetkls = CompMULOpSubset diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index dc17150c..427f5c6a 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -17,12 +17,14 @@ class FUBaseData: """ def __init__(self, pspec, output, exc_kls=None): + self.pspec = pspec self.ctx = PipeContext(pspec) # context for ReservationStation usage self.muxid = self.ctx.muxid self.data = [] self.is_output = output # take regspec and create data attributes (in or out) # TODO: use widspec to create reduced bit mapping. + print (self.regspec) for i, (regfile, regname, widspec) in enumerate(self.regspec): wid = get_regspec_bitwidth([self.regspec], 0, i) if output: @@ -42,6 +44,11 @@ class FUBaseData: if hasattr(self, "exception"): yield from self.exception.ports() + # convenience function to return 0:63 if XLEN=64, 0:31 if XLEN=32 etc. + @property + def intrange(self): + return "0:%d" % (self.pspec.XLEN-1) + def eq(self, i): eqs = [self.ctx.eq(i.ctx)] assert len(self.data) == len(i.data), \ diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py index 6804c593..f5971aad 100644 --- a/src/soc/fu/regspec.py +++ b/src/soc/fu/regspec.py @@ -39,6 +39,7 @@ def get_regspec_bitwidth(regspec, srcdest, idx): class RegSpec: def __init__(self, rwid, n_src=None, n_dst=None, name=None): self._rwid = rwid + print ("RegSpec", rwid) if isinstance(rwid, int): # rwid: integer (covers all registers) self._n_src, self._n_dst = n_src, n_dst diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index fd2336dd..276320db 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -42,5 +42,5 @@ class ShiftRotOutputDataFinal(FUBaseData): class ShiftRotPipeSpec(CommonPipeSpec): - regspec = (ShiftRotInputData.regspec, ShiftRotOutputDataFinal.regspec) + regspecklses = (ShiftRotInputData, ShiftRotOutputDataFinal) opsubsetkls = CompSROpSubset diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py index a6677750..5cc7835e 100644 --- a/src/soc/fu/spr/pipe_data.py +++ b/src/soc/fu/spr/pipe_data.py @@ -42,5 +42,5 @@ class SPROutputData(FUBaseData): class SPRPipeSpec(CommonPipeSpec): - regspec = (SPRInputData.regspec, SPROutputData.regspec) + regspecklses = (SPRInputData, SPROutputData) opsubsetkls = CompSPROpSubset diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 93a135b8..b9c829bc 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -36,5 +36,5 @@ class TrapOutputData(FUBaseData): class TrapPipeSpec(CommonPipeSpec): - regspec = (TrapInputData.regspec, TrapOutputData.regspec) + regspecklses = (TrapInputData, TrapOutputData) opsubsetkls = CompTrapOpSubset