From: Andreas Krebbel Date: Tue, 27 May 2008 11:49:40 +0000 (+0000) Subject: s390.md: Replace all occurences of the 'm' constraint with 'RT'. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb492564aa82ad959013c482cfac1121521be535;p=gcc.git s390.md: Replace all occurences of the 'm' constraint with 'RT'. 2008-05-27 Andreas Krebbel * config/s390/s390.md: Replace all occurences of the 'm' constraint with 'RT'. From-SVN: r136014 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42457ba2c08..a6d1e210d1e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2008-05-27 Andreas Krebbel + + * config/s390/s390.md: Replace all occurences of the 'm' + constraint with 'RT'. + 2008-05-27 Andreas Krebbel * config/s390/s390.md ("cpu_facility", "enabled"): Attribute diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index c6a4e05292b..03ebfcde5b8 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -551,7 +551,7 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m") + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") (match_operand:GPR 1 "const0_operand" ""))) (set (match_operand:GPR 2 "register_operand" "=d,d") (match_dup 0))] @@ -564,7 +564,7 @@ ; ltr, lt, ltgr, ltg (define_insn "*tst_cconly_extimm" [(set (reg CC_REGNUM) - (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m") + (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") (match_operand:GPR 1 "const0_operand" ""))) (clobber (match_scratch:GPR 2 "=X,d"))] "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" @@ -693,7 +693,7 @@ (define_insn "*cmpdi_cct" [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") - (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))] + (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" "@ cgr\t%0,%1 @@ -722,7 +722,7 @@ (define_insn "*cmpdi_ccs_sign" [(set (reg CC_REGNUM) - (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) + (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" "@ @@ -759,7 +759,7 @@ (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) - (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) + (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" "@ @@ -770,7 +770,7 @@ (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ") - (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))] + (match_operand:DI 1 "general_operand" "d,Op,RT,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" "@ clgr\t%0,%1 @@ -891,7 +891,7 @@ (define_insn "movti" [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") - (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))] + (match_operand:TI 1 "general_operand" "QS,d,dPRT,d,Q"))] "TARGET_64BIT" "@ lmg\t%0,%N0,%S1 @@ -1017,9 +1017,9 @@ (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,f,d,d,d,d, - m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") + RT,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") (match_operand:DI 1 "general_operand" - "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,m, + "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,RT, d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] "TARGET_64BIT" "@ @@ -1089,7 +1089,7 @@ (define_insn "*movdi_31" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") - (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))] + (match_operand:DI 1 "general_operand" "Q,S,d,d,dPRT,d,*f,R,T,*f,*f,Q"))] "!TARGET_64BIT" "@ lm\t%0,%N0,%S1 @@ -1505,7 +1505,7 @@ (define_insn "*mov_64" [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q") - (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dm,d,Q"))] + (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d,Q"))] "TARGET_64BIT" "@ lzxr\t%0 @@ -1622,9 +1622,9 @@ (define_insn "*mov_64dfp" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,d,f,f,R,T,d,d,m,?Q") + "=f,f,f,d,f,f,R,T,d,d,RT,?Q") (match_operand:DD_DF 1 "general_operand" - "G,f,d,f,R,T,f,f,d,m,d,?Q"))] + "G,f,d,f,R,T,f,f,d,RT,d,?Q"))] "TARGET_64BIT && TARGET_DFP" "@ lzdr\t%0 @@ -1644,8 +1644,8 @@ fstoredf,fstoredf,lr,load,store,*")]) (define_insn "*mov_64" - [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") - (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] + [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q") + (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d,?Q"))] "TARGET_64BIT" "@ lzdr\t%0 @@ -1664,9 +1664,9 @@ (define_insn "*mov_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" - "=f,f,f,f,R,T,d,d,Q,S, d,o,Q") + "=f,f,f,f,R,T,d,d,Q,S, d,o,Q") (match_operand:DD_DF 1 "general_operand" - " G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] + " G,f,R,T,f,f,Q,S,d,d,dPRT,d,Q"))] "!TARGET_64BIT" "@ lzdr\t%0 @@ -2868,7 +2868,7 @@ (define_insn "*extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")))] "TARGET_64BIT" "@ lgfr\t%0,%1 @@ -2909,7 +2909,7 @@ (define_insn "*extendhidi2_extimm" [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] + (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,RT")))] "TARGET_64BIT && TARGET_EXTIMM" "@ lghr\t%0,%1 @@ -2918,7 +2918,7 @@ (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] + (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] "TARGET_64BIT" "lgh\t%0,%1" [(set_attr "op_type" "RXY")]) @@ -2953,7 +2953,7 @@ ; lbr, lgbr, lb, lgb (define_insn "*extendqi2_extimm" [(set (match_operand:GPR 0 "register_operand" "=d,d") - (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))] + (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] "TARGET_EXTIMM" "@ lbr\t%0,%1 @@ -2963,7 +2963,7 @@ ; lb, lgb (define_insn "*extendqi2" [(set (match_operand:GPR 0 "register_operand" "=d") - (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))] + (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "lb\t%0,%1" [(set_attr "op_type" "RXY")]) @@ -3008,7 +3008,7 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT")))] "TARGET_64BIT" "@ llgfr\t%0,%1 @@ -3021,7 +3021,7 @@ (define_insn "*llgt_sidi" [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (const_int 2147483647)))] "TARGET_64BIT" "llgt\t%0,%1" @@ -3029,7 +3029,7 @@ (define_insn_and_split "*llgt_sidi_split" [(set (match_operand:DI 0 "register_operand" "=d") - (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) (const_int 2147483647))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" @@ -3042,7 +3042,7 @@ (define_insn "*llgt_sisi" [(set (match_operand:SI 0 "register_operand" "=d,d") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") (const_int 2147483647)))] "TARGET_ZARCH" "@ @@ -3115,7 +3115,7 @@ ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend2_extimm" [(set (match_operand:GPR 0 "register_operand" "=d,d") - (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] + (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] "TARGET_EXTIMM" "@ llr\t%0,%1 @@ -3125,7 +3125,7 @@ ; llgh, llgc (define_insn "*zero_extend2" [(set (match_operand:GPR 0 "register_operand" "=d") - (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))] + (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg\t%0,%1" [(set_attr "op_type" "RXY")]) @@ -3145,7 +3145,7 @@ (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] + (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_ZARCH" "#" "&& reload_completed" @@ -3169,14 +3169,14 @@ (define_insn "*zero_extendqihi2_64" [(set (match_operand:HI 0 "register_operand" "=d") - (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] + (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") - (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] + (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_ZARCH" "#" "&& reload_completed" @@ -3633,7 +3633,7 @@ (define_insn "*adddi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) + (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" @@ -3644,7 +3644,7 @@ (define_insn "*adddi3_zero_cc" [(set (reg CC_REGNUM) - (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) + (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") @@ -3657,7 +3657,7 @@ (define_insn "*adddi3_zero_cconly" [(set (reg CC_REGNUM) - (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) + (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -3669,7 +3669,7 @@ (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) + (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" @@ -3997,7 +3997,7 @@ (define_insn "*subdi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) + (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ @@ -4008,7 +4008,7 @@ (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] @@ -4021,7 +4021,7 @@ (define_insn "*subdi3_zero_cconly" [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" @@ -4033,7 +4033,7 @@ (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") - (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) + (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ @@ -4289,7 +4289,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_dup 1))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -4305,7 +4305,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_dup 1))) (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" @@ -4322,7 +4322,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_dup 2))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -4338,7 +4338,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_dup 2))) (clobber (match_scratch:GPR 0 "=d,d"))] "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" @@ -4353,7 +4353,7 @@ (compare (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] @@ -4368,7 +4368,7 @@ [(set (match_operand:GPR 0 "register_operand" "=d,d") (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) - (match_operand:GPR 2 "general_operand" "d,m"))) + (match_operand:GPR 2 "general_operand" "d,RT"))) (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ @@ -4381,7 +4381,7 @@ [(set (reg CC_REGNUM) (compare (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 3 "s390_slb_comparison" "")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d,d") @@ -4396,7 +4396,7 @@ (define_insn "*sub3_slb" [(set (match_operand:GPR 0 "register_operand" "=d,d") (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") - (match_operand:GPR 2 "general_operand" "d,m")) + (match_operand:GPR 2 "general_operand" "d,RT")) (match_operand:GPR 3 "s390_slb_comparison" ""))) (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" @@ -4499,7 +4499,7 @@ (define_insn "*muldi3_sign" [(set (match_operand:DI 0 "register_operand" "=d,d") - (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) + (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,RT")) (match_operand:DI 1 "register_operand" "0,0")))] "TARGET_64BIT" "@ @@ -4511,7 +4511,7 @@ (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:DI 2 "general_operand" "d,K,m")))] + (match_operand:DI 2 "general_operand" "d,K,RT")))] "TARGET_64BIT" "@ msgr\t%0,%2 @@ -4572,7 +4572,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,0")) (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] + (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "@ mlr\t%0,%2 @@ -4662,7 +4662,7 @@ (ashift:TI (zero_extend:TI (mod:DI (match_operand:DI 1 "register_operand" "0,0") - (match_operand:DI 2 "general_operand" "d,m"))) + (match_operand:DI 2 "general_operand" "d,RT"))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] "TARGET_64BIT" @@ -4679,7 +4679,7 @@ (zero_extend:TI (mod:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,m")))) + (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) (const_int 64)) (zero_extend:TI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] @@ -4738,7 +4738,7 @@ (truncate:DI (umod:TI (match_operand:TI 1 "register_operand" "0,0") (zero_extend:TI - (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) + (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) (const_int 64)) (zero_extend:TI (truncate:DI @@ -4856,7 +4856,7 @@ (truncate:SI (umod:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) + (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) (const_int 32)) (zero_extend:DI (truncate:SI @@ -5076,7 +5076,7 @@ (define_insn "*anddi3_cc" [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (and:DI (match_dup 1) (match_dup 2)))] @@ -5089,7 +5089,7 @@ (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT @@ -5105,7 +5105,7 @@ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%d,o,0,0,0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" - "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q"))) + "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ @@ -5361,7 +5361,7 @@ (define_insn "*iordi3_cc" [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (ior:DI (match_dup 1) (match_dup 2)))] @@ -5374,7 +5374,7 @@ (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" @@ -5387,7 +5387,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" - "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q"))) + "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ @@ -5634,7 +5634,7 @@ (define_insn "*xordi3_cc" [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d,d") (xor:DI (match_dup 1) (match_dup 2)))] @@ -5647,7 +5647,7 @@ (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") - (match_operand:DI 2 "general_operand" "d,m")) + (match_operand:DI 2 "general_operand" "d,RT")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" @@ -5659,7 +5659,7 @@ (define_insn "*xordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q"))) + (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ @@ -7327,7 +7327,7 @@ (define_insn "*tls_load_64" [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:DI 1 "memory_operand" "m") + (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") (match_operand:DI 2 "" "")] UNSPEC_TLS_LOAD))] "TARGET_64BIT"