From: kessam <61152217+kessam@users.noreply.github.com> Date: Sun, 5 Apr 2020 15:56:29 +0000 (+0200) Subject: Fix timing constraints X-Git-Tag: 24jan2021_ls180~504^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb532f5e922135746014a8318aac820be2506ffe;p=litex.git Fix timing constraints --- diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 014b5ca2..2a8b91d2 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -268,23 +268,24 @@ class XilinxVivadoToolchain: # The asynchronous input to a MultiReg is a false path platform.add_platform_command( "set_false_path -quiet " - "-to [get_nets -quiet -filter {{mr_ff == TRUE}}]" + "-through [get_nets -hierarchical -filter {{mr_ff == TRUE}}]" ) # The asychronous reset input to the AsyncResetSynchronizer is a false path platform.add_platform_command( "set_false_path -quiet " - "-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} " - "-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" + "-to [get_pins -filter {{REF_PIN_NAME == PRE}} " + "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" ) - # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs + # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs platform.add_platform_command( "set_max_delay 2 -quiet " - "-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} " - "-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] " - "-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} " - "-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]" + "-from [get_pins -filter {{REF_PIN_NAME == C}} " + "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] " + "-to [get_pins -filter {{REF_PIN_NAME == D}} " + "-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]" ) + def build(self, platform, fragment, build_dir = "build", build_name = "top",