From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 21:31:55 +0000 (-0700)
Subject: Fix compile error
X-Git-Tag: working-ls180~1039^2~264^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb568ddb4e2ccaab352d9d062f6b4926aca75680;p=yosys.git

Fix compile error
---

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 5e87d6497..45d7a34df 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
+			SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
 			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
+			SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
 			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 }