From: Florent Kermarrec Date: Thu, 12 Dec 2019 11:41:25 +0000 (+0100) Subject: soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate... X-Git-Tag: 24jan2021_ls180~811 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb6b0786b6654202af274468e1d6e2095a423f06;p=litex.git soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 76da0e48..ca670ff0 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -138,7 +138,6 @@ class SoCCore(Module): self.integrated_main_ram_size = integrated_main_ram_size assert csr_data_width in [8, 32, 64] - assert 2**(csr_address_width + 2) <= 0x1000000 self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width @@ -266,7 +265,7 @@ class SoCCore(Module): address_width = csr_address_width, data_width = csr_data_width)) self.add_csr_master(self.wishbone2csr.csr) - self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000) + self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2)) # Methods --------------------------------------------------------------------------------------