From: Tobias Platen Date: Wed, 14 Jul 2021 18:38:11 +0000 (+0200) Subject: add more debug outputs, pass dcbz to loadstore/dcache X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb8ee264a1d8d71c5520d4cd0131695ab1661303;p=soc.git add more debug outputs, pass dcbz to loadstore/dcache --- diff --git a/src/soc/experiment/test/test_dcbz_pi.py b/src/soc/experiment/test/test_dcbz_pi.py index 789dbb0a..8da01503 100644 --- a/src/soc/experiment/test/test_dcbz_pi.py +++ b/src/soc/experiment/test/test_dcbz_pi.py @@ -126,11 +126,13 @@ def _test_dcbz_addr_zero(dut, mem): # size ==, msr_pr TODO ## causes hang in pi_dcbz -- investigate - yield from pi_st(pi, addr, data, 8, msr_pr=1) - yield - yield - yield Display("done_pi_st") + ##yield from pi_st(pi, addr, data, 8, msr_pr=1) + ##yield + ##yield + ##yield Display("done_pi_st") + ## verify this one first + ## is_dcbz 1 ## addrok 1 yield from pi_dcbz(pi, addr, data, 8, msr_pr=1) yield diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index d4db098c..47d89316 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -315,6 +315,8 @@ class LoadStore1(PortInterfaceBase): m.d.comb += d_out.priv_mode.eq(self.req.priv_mode) m.d.comb += d_out.virt_mode.eq(self.req.virt_mode) m.d.comb += self.align_intr.eq(self.req.align_intr) + m.d.comb += Display("validblip dcbz=%i addr=%x",self.req.dcbz,self.req.addr) + m.d.comb += d_out.dcbz.eq(self.req.dcbz) with m.Else(): m.d.comb += d_out.load.eq(ldst_r.load) m.d.comb += d_out.byte_sel.eq(ldst_r.byte_sel) @@ -323,6 +325,8 @@ class LoadStore1(PortInterfaceBase): m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode) m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode) m.d.comb += self.align_intr.eq(ldst_r.align_intr) + m.d.comb += Display("no_validblip dcbz=%i addr=%x",ldst_r.dcbz,ldst_r.addr) + m.d.comb += d_out.dcbz.eq(ldst_r.dcbz) # XXX these should be possible to remove but for some reason # cannot be... yet. TODO, investigate