From: Nick Clifton Date: Fri, 8 Jan 2021 11:29:43 +0000 (+0000) Subject: Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb932b57cbf99d01145cb4b5c0c64da9157c7f73;p=binutils-gdb.git Treat the AArch64 register id_aa64mmfr2_el1 as a core system register. PR 27139 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a core system register. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a4cd73cc720..0eef3ab55ea 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2021-01-08 Nick Clifton + + PR 27139 + * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a + core system register. + 2021-01-07 Samuel Thibault * configure: Regenerate. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ccebe2c8a61..eecee970bc6 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3943,7 +3943,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ), SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ), SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ), - SR_V8_2 ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ), + SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ), SR_CORE ("id_aa64afr0_el1", CPENC (3,0,C0,C5,4), F_REG_READ), SR_CORE ("id_aa64afr1_el1", CPENC (3,0,C0,C5,5), F_REG_READ), SR_SVE ("id_aa64zfr0_el1", CPENC (3,0,C0,C4,4), F_REG_READ),