From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Apr 2019 22:23:09 +0000 (+0100)
Subject: use RecordObject in output mux pipe
X-Git-Tag: ls180-24jan2020~1203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fb966df09443abf0e34d3a65bde9cb2b4db629d3;p=ieee754fpu.git

use RecordObject in output mux pipe
---

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index f1b0774f..9f420f07 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -5,24 +5,15 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMuxOutPipe
-from singlepipe import SimpleHandshake, PassThroughHandshake
+from singlepipe import SimpleHandshake, PassThroughHandshake, RecordObject
 
 
-class PassInData:
+class PassInData(RecordObject):
     def __init__(self):
+        RecordObject.__init__(self)
         self.mid = Signal(2, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
-    def __iter__(self):
-        yield self.mid
-        yield self.data
-
-    def eq(self, i):
-        return [self.mid.eq(i.mid), self.data.eq(i.data)]
-
-    def ports(self):
-        return [self.mid, self.data]
-
 
 class PassThroughStage: