From: lkcl <lkcl@web>
Date: Wed, 17 Nov 2021 23:32:51 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3372
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fba231cfebe2aa94dcf3027925b632fc19c13975;p=libreriscv.git

---

diff --git a/shakti/m_class/SPI.mdwn b/shakti/m_class/SPI.mdwn
index cb56f22a8..75b36a3b1 100644
--- a/shakti/m_class/SPI.mdwn
+++ b/shakti/m_class/SPI.mdwn
@@ -2,7 +2,7 @@
 
 see also [[QSPI]]
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
+* <http://bugs.libre-soc.org/show_bug.cgi?id=6>
 * Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
@@ -11,6 +11,5 @@ see also [[QSPI]]
 * ASIC-proven <https://opencores.org/project,spi_master_slave>
 https://opencores.org/websvn/filedetails?repname=spi_master_slave&path=%2Fspi_master_slave%2Ftrunk%2Frtl%2Fspi_master_slave%2Fspi_master.vhd
 * Wishbone-compliant <https://opencores.org/project,simple_spi>
-* Raptor Engineering litespi, improved <
-https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litespi>
+* Raptor Engineering litespi, improved <https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litespi>
 * Also Shakti E-Class peripheral set in BSV