From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Jul 2021 19:07:49 +0000 (+0100)
Subject: whoops, REMAP inverted
X-Git-Tag: xlen-bcd~343
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fba9451037447ad3f50619da6c39463c2051da8d;p=openpower-isa.git

whoops, REMAP inverted
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a73085cf..1ee2b51a 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1240,6 +1240,8 @@ class ISACaller:
         # after that, settle down (combinatorial) to let Vector reg numbers
         # work themselves out
         yield Settle()
+        remap_active = yield self.dec2.remap_active
+        print ("remap active", remap_active)
 
         # main input registers (RT, RA ...)
         inputs = []
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 274cf228..7df9ab52 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1285,9 +1285,9 @@ class PowerDecode2(PowerDecodeSubset):
                     selectstep = dststep if out else srcstep
                     step = Signal(7, name="step_%s" % rname.lower())
                     with m.If(self.remap_active):
-                        comb += step.eq(selectstep)
-                    with m.Else():
                         comb += step.eq(remapstep)
+                    with m.Else():
+                        comb += step.eq(selectstep)
                     # reverse gear goes the opposite way
                     with m.If(self.rm_dec.reverse_gear):
                         comb += to_reg.data.eq(offs+svdec.reg_out+(vl-1-step))