From: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Date: Mon, 3 Aug 2015 22:15:17 +0000 (-0700)
Subject: vk: Update generated headers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbb119061e7be6ecdaefd8630e3fae274886d297;p=mesa.git

vk: Update generated headers

This adds zeroing of reserved blocks of dwords and removes an
instruction definition.
---

diff --git a/src/vulkan/gen75_pack.h b/src/vulkan/gen75_pack.h
index 583c5f25003..82b4065b760 100644
--- a/src/vulkan/gen75_pack.h
+++ b/src/vulkan/gen75_pack.h
@@ -7060,6 +7060,11 @@ GEN75_SF_CLIP_VIEWPORT_pack(__gen_user_data *data, void * restrict dst,
       __gen_float(values->YMaxClipGuardband) |
       0;
 
+   for (uint32_t i = 0, j = 12; i < 4; i += 1, j++) {
+      dw[j] =
+         0;
+   }
+
 }
 
 #define GEN75_BLEND_STATE_length 0x00000002
@@ -7365,36 +7370,6 @@ GEN75_DEPTH_STENCIL_STATE_pack(__gen_user_data *data, void * restrict dst,
 
 #define GEN75_MEMORY_OBJECT_CONTROL_STATE_length 0x00000001
 
-#define GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_length 0x00000001
-
-struct GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS {
-#define     Highestpriority                                    0
-#define     Secondhighestpriority                              1
-#define     Thirdhighestpriority                               2
-#define     Lowestpriority                                     3
-   uint32_t                                     ArbitrationPriorityControl;
-#define     PTE                                                0
-#define     UC                                                 1
-#define     LLCeLLCWBcacheable                                 2
-#define     eLLCWBcacheable                                    3
-   uint32_t                                     LLCeLLCCacheabilityControlLLCCC;
-   uint32_t                                     L3CacheabilityControlL3CC;
-};
-
-static inline void
-GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_pack(__gen_user_data *data, void * restrict dst,
-                                                  const struct GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS * restrict values)
-{
-   uint32_t *dw = (uint32_t * restrict) dst;
-
-   dw[0] =
-      __gen_field(values->ArbitrationPriorityControl, 4, 5) |
-      __gen_field(values->LLCeLLCCacheabilityControlLLCCC, 1, 2) |
-      __gen_field(values->L3CacheabilityControlL3CC, 0, 0) |
-      0;
-
-}
-
 #define GEN75_INTERFACE_DESCRIPTOR_DATA_length 0x00000008
 
 struct GEN75_INTERFACE_DESCRIPTOR_DATA {
@@ -7701,6 +7676,11 @@ GEN75_SAMPLER_BORDER_COLOR_STATE_pack(__gen_user_data *data, void * restrict dst
       __gen_field(values->BorderColorAlpha, 0, 31) |
       0;
 
+   for (uint32_t i = 0, j = 4; i < 12; i += 1, j++) {
+      dw[j] =
+         0;
+   }
+
    dw[16] =
       __gen_field(values->BorderColor, 0, 127) |
       __gen_field(values->BorderColor, 0, 127) |
diff --git a/src/vulkan/gen7_pack.h b/src/vulkan/gen7_pack.h
index 05b800034e0..886a26c00a2 100644
--- a/src/vulkan/gen7_pack.h
+++ b/src/vulkan/gen7_pack.h
@@ -5816,6 +5816,11 @@ GEN7_SF_CLIP_VIEWPORT_pack(__gen_user_data *data, void * restrict dst,
       __gen_float(values->YMaxClipGuardband) |
       0;
 
+   for (uint32_t i = 0, j = 12; i < 4; i += 1, j++) {
+      dw[j] =
+         0;
+   }
+
 }
 
 #define GEN7_BLEND_STATE_length 0x00000002
diff --git a/src/vulkan/gen8_pack.h b/src/vulkan/gen8_pack.h
index 620b5a799c4..cafccc94741 100644
--- a/src/vulkan/gen8_pack.h
+++ b/src/vulkan/gen8_pack.h
@@ -4187,6 +4187,11 @@ GEN8_3DSTATE_SAMPLE_PATTERN_pack(__gen_user_data *data, void * restrict dst,
       __gen_field(values->DwordLength, 0, 7) |
       0;
 
+   for (uint32_t i = 0, j = 1; i < 4; i += 1, j++) {
+      dw[j] =
+         0;
+   }
+
    dw[5] =
       __gen_field(values->_8xSample7XOffset * (1 << 4), 28, 31) |
       __gen_field(values->_8xSample7YOffset * (1 << 4), 24, 27) |
@@ -8032,42 +8037,6 @@ GEN8_COLOR_CALC_STATE_pack(__gen_user_data *data, void * restrict dst,
 
 #define GEN8_MEMORY_OBJECT_CONTROL_STATE_length 0x00000001
 
-#define GEN8_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_length 0x00000001
-
-struct GEN8_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS {
-#define     UseCacheabilityControlsfrompagetableUCwithFenceifcoherentcycle       0
-#define     UncacheableUCnoncacheable                          1
-#define     WritethroughWT                                     2
-#define     WritebackWB                                        3
-   uint32_t                                     MemoryTypeLLCeLLCCacheabilityControlLeLLCCC;
-#define     eLLCOnly                                           0
-#define     LLCOnly                                            1
-#define     LLCeLLCAllowed                                     2
-#define     L3LLCeLLCAllowed                                   3
-   uint32_t                                     TargetCacheTC;
-   bool                                         EncryptedData;
-#define     PoorChance                                         3
-#define     NormalChance                                       2
-#define     BetterChance                                       1
-#define     BestChance                                         0
-   bool                                         AgeforQUADLRUAGE;
-};
-
-static inline void
-GEN8_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_pack(__gen_user_data *data, void * restrict dst,
-                                                  const struct GEN8_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS * restrict values)
-{
-   uint32_t *dw = (uint32_t * restrict) dst;
-
-   dw[0] =
-      __gen_field(values->MemoryTypeLLCeLLCCacheabilityControlLeLLCCC, 5, 6) |
-      __gen_field(values->TargetCacheTC, 3, 4) |
-      __gen_field(values->EncryptedData, 2, 2) |
-      __gen_field(values->AgeforQUADLRUAGE, 0, 1) |
-      0;
-
-}
-
 #define GEN8_INTERFACE_DESCRIPTOR_DATA_length 0x00000008
 
 struct GEN8_INTERFACE_DESCRIPTOR_DATA {