From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 May 2022 10:31:00 +0000 (+0100)
Subject: code-comments on madded and divmod2du should say RS=RT+MAXVL now
X-Git-Tag: sv_maxu_works-initial~444
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbb2dd8d05626d68a9edd404a3b1a9ba888ea602;p=openpower-isa.git

code-comments on madded and divmod2du should say RS=RT+MAXVL now
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index b4a39fab..7dfd4c55 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -7,7 +7,7 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
@@ -27,7 +27,7 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)