From: Grazvydas Ignotas <notasas@gmail.com>
Date: Wed, 2 Sep 2015 22:54:28 +0000 (+0300)
Subject: r600g: apply disable workaround on all scissors
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbb423b43380d0e43d14056e96846da412693148;p=mesa.git

r600g: apply disable workaround on all scissors

During review of the "r600g: make all scissor states use single atom" patch
Marek Olšák noticed that scissor disable workaround should be applied on
all scissor states and not just first one, so let's do so.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 64a22e6d305..c3db1437200 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -771,15 +771,15 @@ static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom
 	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct r600_scissor_state *rstate = &rctx->scissor;
 	struct pipe_scissor_state *state;
+	bool do_disable_workaround = false;
 	uint32_t dirty_mask;
 	unsigned i, offset;
+	uint32_t tl, br;
 
 	if (rctx->b.chip_class == R600 && !rctx->scissor.enable) {
-		radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
-		radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
-				     S_028240_WINDOW_OFFSET_DISABLE(1));
-		radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
-		return;
+		tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
+		br = S_028244_BR_X(8192) | S_028244_BR_Y(8192);
+		do_disable_workaround = true;
 	}
 
 	dirty_mask = rstate->dirty_mask;
@@ -787,11 +787,15 @@ static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom
 	{
 		i = u_bit_scan(&dirty_mask);
 		offset = i * 4 * 2;
-		state = &rstate->scissor[i];
 		radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
-		radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
-				     S_028240_WINDOW_OFFSET_DISABLE(1));
-		radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
+		if (!do_disable_workaround) {
+			state = &rstate->scissor[i];
+			tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
+				S_028240_WINDOW_OFFSET_DISABLE(1);
+			br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+		}
+		radeon_emit(cs, tl);
+		radeon_emit(cs, br);
 	}
 	rstate->dirty_mask = 0;
 	rstate->atom.num_dw = 0;
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index d2b6ebec6a4..0b3fe857591 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -374,6 +374,7 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 	if (rctx->b.chip_class == R600 &&
 	    rs->scissor_enable != rctx->scissor.enable) {
 		rctx->scissor.enable = rs->scissor_enable;
+		rctx->scissor.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
 		r600_mark_atom_dirty(rctx, &rctx->scissor.atom);
 	}