From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Nov 2020 15:35:48 +0000 (+0000)
Subject: note that mv is possible using addi.
X-Git-Tag: convert-csv-opcode-to-binary~1768
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbce3cbb32c91e357c5ff5f0299184bc035e1525;p=libreriscv.git

note that mv is possible using addi.
---

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 545a705d0..a3ee7b227 100644
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -115,8 +115,10 @@ Further Notes:
 * bc also has an immediate mode, listed below in Branch section
 * for LD/ST, offset is aligned.  8-byte: i2||imm||0b000 4-byte: 0b00
 * SV Prefix over-rides help provide alternative bitwidths for LD/ST
-* RB|0 if RB is zero, addi. becomes "li" (this only works if RT takes
-  part of opcode).
+* RB|0 if RB is zero, addi. becomes "li"
+ - this only works if RT takes part of opcode
+ - mv is also possible by specifying an immediate of zero
+
 
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