From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 22:35:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~588
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbcf8a77a0f0a28a79a3f65aa60b91c740d21636;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index f196cfd00..b71453154 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -29,7 +29,7 @@ add actual Vector Instructions, relying solely and exclusively on the
 **Scalar** ISA, it is **Scalar** instructions that need to be added to
 the **Scalar** Power ISA before Simple-V may orthogonally Vectorise them.
 
-Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER
+The goal of RED Semiconductor Ltd, an OpenPOWER
 Stakeholder, is to bring to market mass-volume general-purpose compute
 processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT
 desktop chromebook netbook smartphone laptop markets, performance-leveraged