From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 02:18:10 +0000 (+0100)
Subject: CR field on Br input data is specd as 0:3 range
X-Git-Tag: div_pipeline~924
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbdafb65de5ce9278c167b8c8c1d77ed35e3a3a1;p=soc.git

CR field on Br input data is specd as 0:3 range
---

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 28099eaa..b5aa4c0f 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -33,7 +33,7 @@ from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
 class BranchInputData(IntegerData):
     regspec = [('SPR', 'spr1', '0:63'),
                ('SPR', 'spr2', '0:63'),
-               ('CR', 'cr', '4'),
+               ('CR', 'cr', '0:3'),
                ('PC', 'cia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)