From: Michael Nolan <mtnolan2640@gmail.com>
Date: Mon, 23 Mar 2020 15:46:36 +0000 (-0400)
Subject: Add support for extended/indexed ld/st
X-Git-Tag: div_pipeline~1645
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbe2c0b9639d7243fbe928da08a9eefd185474a7;p=soc.git

Add support for extended/indexed ld/st
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 2f435dc7..cf71670d 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -96,9 +96,13 @@ class InternalOpSimulator:
         addr = self.regfile.read_reg(addr_reg)
         
         imm_ok = yield pdecode2.e.imm_data.ok
+        r2_ok = yield pdecode2.e.read_reg2.ok
         if imm_ok:
             imm = yield pdecode2.e.imm_data.data
             addr += imm
+        elif r2_ok:
+            r2_sel = yield pdecode2.e.read_reg2.data
+            addr += self.regfile.read_reg(r2_sel)
         if internal_op == InternalOp.OP_STORE.value:
             val_reg = yield pdecode2.e.read_reg3.data
             val = self.regfile.read_reg(val_reg)
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 3a5e37b9..94a9f39a 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -89,6 +89,21 @@ class DecoderTestCase(FHDLTestCase):
              2: 0x5678,
              3: 0x1234})
 
+    def test_ldst_extended(self):
+        lst = ["addi 1, 0, 0x1234",
+               "addi 2, 0, 0x5678",
+               "addi 4, 0, 0x40",
+               "stw  1, 0x40(2)",
+               "lwzx  3, 4, 2"]
+        gen = InstrList(lst)
+
+        simulator = InternalOpSimulator()
+
+        self.run_tst(gen, simulator)
+        simulator.regfile.assert_gprs(
+            {1: 0x1234,
+             2: 0x5678,
+             3: 0x1234})
 
 if __name__ == "__main__":
     unittest.main()