From: Jakub Jelinek Date: Wed, 18 Mar 2015 10:58:32 +0000 (+0100) Subject: re PR rtl-optimization/65078 (4.9 and 5.0 generate more spill-fill in comparison... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbf524de7b7f81d26b43a49c766ca6d1ac41457c;p=gcc.git re PR rtl-optimization/65078 (4.9 and 5.0 generate more spill-fill in comparison with 4.8.2) PR target/65078 * config/i386/sse.md (movsi/movdi -> vec_extract_*_0 splitter): New. * gcc.target/i386/pr65078-1.c: New test. * gcc.target/i386/pr65078-2.c: New test. * gcc.target/i386/pr65078-3.c: New test. * gcc.target/i386/pr65078-4.c: New test. * gcc.target/i386/pr65078-5.c: New test. * gcc.target/i386/pr65078-6.c: New test. From-SVN: r221485 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7120cc363e4..77abe6739f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-03-18 Jakub Jelinek + + PR target/65078 + * config/i386/sse.md (movsi/movdi -> vec_extract_*_0 splitter): New. + 2015-03-16 Georg-Johann Lay PR target/65296 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index af74b35d5ca..5800a3eebf2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12805,6 +12805,65 @@ operands[1] = adjust_address (operands[1], mode, offs); }) +;; Turn SImode or DImode extraction from arbitrary SSE/AVX/AVX512F +;; vector modes into vec_extract*. +(define_split + [(set (match_operand:SWI48x 0 "nonimmediate_operand") + (match_operand:SWI48x 1 "register_operand"))] + "can_create_pseudo_p () + && GET_CODE (operands[1]) == SUBREG + && REG_P (SUBREG_REG (operands[1])) + && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1]))) == MODE_VECTOR_INT + || (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[1]))) + == MODE_VECTOR_FLOAT)) + && SUBREG_BYTE (operands[1]) == 0 + && TARGET_SSE + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[1]))) == 16 + || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[1]))) == 32 + && TARGET_AVX) + || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[1]))) == 64 + && TARGET_AVX512F)) + && (mode == SImode || TARGET_64BIT || MEM_P (operands[0]))" + [(set (match_dup 0) (vec_select:SWI48x (match_dup 1) + (parallel [(const_int 0)])))] +{ + rtx tmp; + operands[1] = SUBREG_REG (operands[1]); + switch (GET_MODE_SIZE (GET_MODE (operands[1]))) + { + case 64: + if (mode == SImode) + { + tmp = gen_reg_rtx (V8SImode); + emit_insn (gen_vec_extract_lo_v16si (tmp, + gen_lowpart (V16SImode, + operands[1]))); + } + else + { + tmp = gen_reg_rtx (V4DImode); + emit_insn (gen_vec_extract_lo_v8di (tmp, + gen_lowpart (V8DImode, + operands[1]))); + } + operands[1] = tmp; + /* FALLTHRU */ + case 32: + tmp = gen_reg_rtx (mode); + if (mode == SImode) + emit_insn (gen_vec_extract_lo_v8si (tmp, gen_lowpart (V8SImode, + operands[1]))); + else + emit_insn (gen_vec_extract_lo_v4di (tmp, gen_lowpart (V4DImode, + operands[1]))); + operands[1] = tmp; + break; + case 16: + operands[1] = gen_lowpart (mode, operands[1]); + break; + } +}) + (define_insn "*vec_concatv2si_sse4_1" [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,x, Yr,*x,x, x, *y,*y") (vec_concat:V2SI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 16605f35f2a..406fec06f0e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2015-03-18 Jakub Jelinek + + PR target/65078 + * gcc.target/i386/pr65078-1.c: New test. + * gcc.target/i386/pr65078-2.c: New test. + * gcc.target/i386/pr65078-3.c: New test. + * gcc.target/i386/pr65078-4.c: New test. + * gcc.target/i386/pr65078-5.c: New test. + * gcc.target/i386/pr65078-6.c: New test. + 2015-03-18 Paolo Carlini PR c++/65340 diff --git a/gcc/testsuite/gcc.target/i386/pr65078-1.c b/gcc/testsuite/gcc.target/i386/pr65078-1.c new file mode 100644 index 00000000000..d8d0d85970c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-1.c @@ -0,0 +1,61 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-additional-options "-mregparm=2" { target ia32 } } */ +/* { dg-final { scan-assembler-not "\\(%\[er\]sp\\)" } } */ + +typedef unsigned char V __attribute__((vector_size (16))); +typedef unsigned long long W __attribute__((vector_size (16))); +typedef unsigned int T __attribute__((vector_size (16))); + +void +f1 (unsigned long long *x, V y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f2 (V y) +{ + return ((W)y)[0]; +} +#endif + +void +f3 (unsigned int *x, V y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f4 (V y) +{ + return ((T)y)[0]; +} + +void +f5 (unsigned long long *x, W y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f6 (W y) +{ + return ((W)y)[0]; +} +#endif + +void +f7 (unsigned int *x, T y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f8 (T y) +{ + return ((T)y)[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr65078-2.c b/gcc/testsuite/gcc.target/i386/pr65078-2.c new file mode 100644 index 00000000000..bf220cd5641 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-2.c @@ -0,0 +1,61 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ +/* { dg-additional-options "-mregparm=2" { target ia32 } } */ +/* { dg-final { scan-assembler-not "\\(%\[er\]sp\\)" } } */ + +typedef unsigned char V __attribute__((vector_size (32))); +typedef unsigned long long W __attribute__((vector_size (32))); +typedef unsigned int T __attribute__((vector_size (32))); + +void +f1 (unsigned long long *x, V y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f2 (V y) +{ + return ((W)y)[0]; +} +#endif + +void +f3 (unsigned int *x, V y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f4 (V y) +{ + return ((T)y)[0]; +} + +void +f5 (unsigned long long *x, W y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f6 (W y) +{ + return ((W)y)[0]; +} +#endif + +void +f7 (unsigned int *x, T y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f8 (T y) +{ + return ((T)y)[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr65078-3.c b/gcc/testsuite/gcc.target/i386/pr65078-3.c new file mode 100644 index 00000000000..d1b679f1c63 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-3.c @@ -0,0 +1,61 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-additional-options "-mregparm=2" { target ia32 } } */ +/* { dg-final { scan-assembler-not "\\(%\[er\]sp\\)" } } */ + +typedef unsigned char V __attribute__((vector_size (64))); +typedef unsigned long long W __attribute__((vector_size (64))); +typedef unsigned int T __attribute__((vector_size (64))); + +void +f1 (unsigned long long *x, V y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f2 (V y) +{ + return ((W)y)[0]; +} +#endif + +void +f3 (unsigned int *x, V y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f4 (V y) +{ + return ((T)y)[0]; +} + +void +f5 (unsigned long long *x, W y) +{ + *x = ((W)y)[0]; +} + +#if defined(__x86_64__) || defined(ALL) +unsigned long long +f6 (W y) +{ + return ((W)y)[0]; +} +#endif + +void +f7 (unsigned int *x, T y) +{ + *x = ((T)y)[0]; +} + +unsigned int +f8 (T y) +{ + return ((T)y)[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/pr65078-4.c b/gcc/testsuite/gcc.target/i386/pr65078-4.c new file mode 100644 index 00000000000..d6c52240602 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-4.c @@ -0,0 +1,5 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -DALL" } */ + +#include "pr65078-1.c" diff --git a/gcc/testsuite/gcc.target/i386/pr65078-5.c b/gcc/testsuite/gcc.target/i386/pr65078-5.c new file mode 100644 index 00000000000..9e787fe5f7a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-5.c @@ -0,0 +1,5 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -DALL" } */ + +#include "pr65078-2.c" diff --git a/gcc/testsuite/gcc.target/i386/pr65078-6.c b/gcc/testsuite/gcc.target/i386/pr65078-6.c new file mode 100644 index 00000000000..3fdc9059ede --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr65078-6.c @@ -0,0 +1,5 @@ +/* PR target/65078 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -DALL" } */ + +#include "pr65078-3.c"