From: Derek Hower <drh5@cs.wisc.edu>
Date: Wed, 5 Aug 2009 19:20:32 +0000 (-0500)
Subject: ruby: configuration supports multiple runs in same session
X-Git-Tag: Calvin_Submission~159^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbf7391bb0aa3c32289abb8a1b1066267df7c705;p=gem5.git

ruby: configuration supports multiple runs in same session

These changes allow to run Ruby-gems multiple times from the same
ruby-lang script with different configurations
---

diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb
index 451281f20..2b416e647 100644
--- a/src/mem/ruby/config/MI_example-homogeneous.rb
+++ b/src/mem/ruby/config/MI_example-homogeneous.rb
@@ -8,15 +8,17 @@
 
 require "cfg.rb"
 
+RubySystem.reset
+
 # default values
 
 num_cores = 2
-L1_CACHE_SIZE_KB = 32
-L1_CACHE_ASSOC = 8
-L1_CACHE_LATENCY = 1
+l1_cache_size_kb = 32
+l1_cache_assoc = 8
+l1_cache_latency = 1
 num_memories = 2
 memory_size_mb = 1024
-NUM_DMA = 1
+num_dma = 1
 protocol = "MI_example"
 
 # check for overrides
@@ -46,7 +48,7 @@ assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + p
 require protocol+".rb"
 
 num_cores.times { |n|
-  cache = SetAssociativeCache.new("l1u_"+n.to_s, L1_CACHE_SIZE_KB, L1_CACHE_LATENCY, L1_CACHE_ASSOC, "PSEUDO_LRU")
+  cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
   sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache)
   iface_ports << sequencer
   net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s,
@@ -61,7 +63,7 @@ num_memories.times { |n|
                                        "Directory",
                                        directory, memory_control)
 }
-NUM_DMA.times { |n|
+num_dma.times { |n|
   dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
   iface_ports << dma_sequencer
   net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer)
diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb
index 3196bb639..187dc7a68 100644
--- a/src/mem/ruby/config/MI_example.rb
+++ b/src/mem/ruby/config/MI_example.rb
@@ -1,4 +1,6 @@
 
+require "util.rb"
+
 class MI_example_CacheController < L1CacheController
   attr :cache
   def initialize(obj_name, mach_type, cache, sequencer)
@@ -21,6 +23,8 @@ class MI_example_DirectoryController < DirectoryController
   def argv()
     vec = super()
     vec += " directory_latency "+directory_latency.to_s
+    vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
+    vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
   end
 end
 
diff --git a/src/mem/ruby/config/MOESI_CMP_directory.rb b/src/mem/ruby/config/MOESI_CMP_directory.rb
index 34f7c1776..1e8a82fab 100644
--- a/src/mem/ruby/config/MOESI_CMP_directory.rb
+++ b/src/mem/ruby/config/MOESI_CMP_directory.rb
@@ -1,15 +1,6 @@
 
 require "cfg.rb"
-
-def log_int(n)
-  assert(n.is_a?(Fixnum), "log_int takes a number for an argument")
-  counter = 0
-  while n >= 2 do
-    counter += 1
-    n = n >> 1
-  end
-  return counter
-end
+require "util.rb"
 
 
 class MOESI_CMP_directory_L1CacheController < L1CacheController
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index 11cb7fb57..8a202d450 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -7,22 +7,24 @@
 
 require "cfg.rb"
 
+RubySystem.reset
+
 # default values
 
 num_cores = 2
-L1_ICACHE_SIZE_KB = 32
-L1_ICACHE_ASSOC = 8
-L1_ICACHE_LATENCY = 1
-L1_DCACHE_SIZE_KB = 32
-L1_DCACHE_ASSOC = 8
-L1_DCACHE_LATENCY = 1
-L2_CACHE_SIZE_KB = 2048 # total size (sum of all banks)
-L2_CACHE_ASSOC = 16
-L2_CACHE_LATENCY = 12
+l1_icache_size_kb = 32
+l1_icache_assoc = 8
+l1_icache_latency = 1
+l1_dcache_size_kb = 32
+l1_dcache_assoc = 8
+l1_dcache_latency = 1
+l2_cache_size_kb = 2048 # total size (sum of all banks)
+l2_cache_assoc = 16
+l2_cache_latency = 12
 num_l2_banks = num_cores
 num_memories = 1
 memory_size_mb = 1024
-NUM_DMA = 1
+num_dma = 1
 
 protocol = "MOESI_CMP_directory"
 
@@ -52,8 +54,8 @@ assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protoco
 require protocol+".rb"
 
 num_cores.times { |n|
-  icache = SetAssociativeCache.new("l1i_"+n.to_s, L1_ICACHE_SIZE_KB, L1_ICACHE_LATENCY, L1_ICACHE_ASSOC, "PSEUDO_LRU")
-  dcache = SetAssociativeCache.new("l1d_"+n.to_s, L1_DCACHE_SIZE_KB, L1_DCACHE_LATENCY, L1_DCACHE_ASSOC, "PSEUDO_LRU")
+  icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU")
+  dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU")
   sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache)
   iface_ports << sequencer
   if protocol == "MOESI_CMP_directory"
@@ -65,7 +67,7 @@ num_cores.times { |n|
   end
 }
 num_l2_banks.times { |n|
-  cache = SetAssociativeCache.new("l2u_"+n.to_s, L2_CACHE_SIZE_KB/num_l2_banks, L2_CACHE_LATENCY, L2_CACHE_ASSOC, "PSEUDO_LRU")
+  cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU")
   if protocol == "MOESI_CMP_directory"
     net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
                                                            "L2Cache",
@@ -82,7 +84,7 @@ num_memories.times { |n|
                                                              memory_control)
   end
 }
-NUM_DMA.times { |n|
+num_dma.times { |n|
   dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
   iface_ports << dma_sequencer
   if protocol == "MOESI_CMP_directory"
diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb
index 82fbb64a5..ffc36dd67 100644
--- a/src/mem/ruby/config/cfg.rb
+++ b/src/mem/ruby/config/cfg.rb
@@ -150,6 +150,9 @@ class NetPort < LibRubyObject
   def cppClassName
     "NetPort"
   end
+  def self.totalOfType(mach_type)
+    return @@type_cnt[mach_type]
+  end
 end
 
 class MemoryVector < LibRubyObject
@@ -190,6 +193,7 @@ end
 class RubySystem
 
   @@params = Hash.new
+  @@defaults = Hash.new
   @@network = nil
 
   def self.init(iface_ports, network)
@@ -197,6 +201,14 @@ class RubySystem
     @@network = network
   end
 
+  def self.reset()
+    @@iface_ports = nil
+    @@network = nil
+    @@params.each { |param_name, param|
+      param = @@defaults[param_name]
+    }
+  end
+
   def self.default_param(param_name, type, default)
     if default.is_a?(FalseClass) || default.is_a?(TrueClass)
       assert type.is_a?(Boolean), "default value of param \"#{param_name}\" must be either true or false"
@@ -204,6 +216,7 @@ class RubySystem
       assert default.is_a?(type), "default value of param \"#{param_name}\" does not match type #{type}"
     end
     @@params[param_name] = default
+    @@defaults[param_name] = default
     method_name = (param_name.to_s).to_sym
     instance_eval <<-EOS
        def #{method_name.to_s}
diff --git a/src/mem/ruby/config/util.rb b/src/mem/ruby/config/util.rb
new file mode 100644
index 000000000..a6aa8f6ab
--- /dev/null
+++ b/src/mem/ruby/config/util.rb
@@ -0,0 +1,10 @@
+
+def log_int(n)
+  assert(n.is_a?(Fixnum), "log_int takes a number for an argument")
+  counter = 0
+  while n >= 2 do
+    counter += 1
+    n = n >> 1
+  end
+  return counter
+end