From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jun 2020 03:41:05 +0000 (+0100)
Subject: set SRR0 in OP_SC
X-Git-Tag: div_pipeline~569
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fbf8a7b7c1afa8c3395bd752d7dec29f04107d12;p=soc.git

set SRR0 in OP_SC
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index a241a7d4..3fdfd81e 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -211,6 +211,8 @@ class TrapMainStage(PipeModBase):
                 comb += nia_o.ok.eq(1)
                 comb += srr1_o.data.eq(msr_i)
                 comb += srr1_o.ok.eq(1)
+                comb += srr0_o.data.eq(cia_i+4) # addr to begin from on return
+                comb += srr0_o.ok.eq(1)
 
             # TODO (later)
             #with m.Case(InternalOp.OP_ADDPCIS):