From: Catherine <whitequark@whitequark.org>
Date: Sat, 25 Dec 2021 01:06:10 +0000 (+0000)
Subject: cxxrtl: don't reset elided wires with \init attribute.
X-Git-Tag: yosys-0.13~15^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc049e84a91dcfbdbd654be6db222673f6c8f26c;p=yosys.git

cxxrtl: don't reset elided wires with \init attribute.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index ba11179c6..7a336f8c1 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1838,6 +1838,8 @@ struct CxxrtlWorker {
 		int mem_init_idx = 0;
 		inc_indent();
 			for (auto wire : module->wires()) {
+				const auto &wire_type = wire_types[wire];
+				if (!wire_type.is_named() || wire_type.is_local()) continue;
 				if (!wire_init.count(wire)) continue;
 
 				f << indent << mangle(wire) << " = ";