From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 2 Apr 2021 18:51:46 +0000 (-0300)
Subject: Disallow dm=xx on single predication
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc0c23dff502bd3644ffb02d7ea72054086f2b65;p=soc.git

Disallow dm=xx on single predication

Adjust test cases accordingly.
---

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 46486c2e..74255c68 100644
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -120,7 +120,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/dm=r3 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -151,7 +151,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/dm=ne 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 2e9bea07..da4311b7 100644
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -493,6 +493,8 @@ class SVP64Asm:
             if ptype == '1P':
                 assert not has_smask, \
                     "source-mask can only be specified on Twin-predicate ops"
+                assert not has_pmask, \
+                    "dest-mask can only be specified on Twin-predicate ops"
 
             # construct the mode field, doing sanity-checking along the way