From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 29 Aug 2017 21:17:29 +0000 (-0700)
Subject: Added blackbox $__COUNT_ cell model
X-Git-Tag: yosys-0.8~326^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc0c7f74dc9133bbf19aa9eafff26738a05135ef;p=yosys.git

Added blackbox $__COUNT_ cell model
---

diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 9c3efcb8d..b43fb7511 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -2,6 +2,7 @@
 OBJS += techlibs/greenpak4/synth_greenpak4.o
 OBJS += techlibs/greenpak4/greenpak4_dffinv.o
 
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
diff --git a/techlibs/greenpak4/cells_blackbox.v b/techlibs/greenpak4/cells_blackbox.v
new file mode 100644
index 000000000..8dd38a027
--- /dev/null
+++ b/techlibs/greenpak4/cells_blackbox.v
@@ -0,0 +1,17 @@
+module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
+
+	input wire CE;
+	input wire CLK;
+	output reg OUT;
+	output reg[WIDTH-1:0] POUT;
+	input wire RST;
+	input wire UP;
+
+	parameter COUNT_TO = 1;
+	parameter RESET_MODE = "RISING";
+	parameter HAS_POUT = 0;
+	parameter HAS_CE = 0;
+	parameter WIDTH = 8;
+	parameter DIRECTION = "DOWN";
+
+endmodule